Alex-2-Graf/LGT-Turbo-Sound-emulator
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Alex-2-Graf 2026-08-19 18:30:37 +02:00
parent 31ee768ed2
commit f0918e75b7
36 changed files with 14637 additions and 0 deletions
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BIN
Sources/AY_Emu/.vs/AY_Emu/v14/.atsuo Normal file
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Microsoft Visual Studio Solution File, Format Version 12.00
# Atmel Studio Solution File, Format Version 11.00
VisualStudioVersion = 14.0.23107.0
MinimumVisualStudioVersion = 10.0.40219.1
Project("{18226A42-8477-4023-8AD2-40C49DA407C9}") = "AY_Emu", "AY_Emu\AY_Emu.asmproj", "{59B1D629-9DCC-43ED-A0FD-8AB0E4D622AB}"
EndProject
Global
GlobalSection(SolutionConfigurationPlatforms) = preSolution
Debug|AVR = Debug|AVR
Release|AVR = Release|AVR
EndGlobalSection
GlobalSection(ProjectConfigurationPlatforms) = postSolution
{59B1D629-9DCC-43ED-A0FD-8AB0E4D622AB}.Debug|AVR.ActiveCfg = Debug|AVR
{59B1D629-9DCC-43ED-A0FD-8AB0E4D622AB}.Debug|AVR.Build.0 = Debug|AVR
{59B1D629-9DCC-43ED-A0FD-8AB0E4D622AB}.Release|AVR.ActiveCfg = Release|AVR
{59B1D629-9DCC-43ED-A0FD-8AB0E4D622AB}.Release|AVR.Build.0 = Release|AVR
EndGlobalSection
GlobalSection(SolutionProperties) = preSolution
HideSolutionNode = FALSE
EndGlobalSection
EndGlobal

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Sources/AY_Emu/AY_Emu/AY_Emu.asmproj Normal file
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<?xml version="1.0" encoding="utf-8"?>
<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
<PropertyGroup>
<SchemaVersion>2.0</SchemaVersion>
<ProjectVersion>7.0</ProjectVersion>
<ToolchainName>com.Atmel.AVRAssembler</ToolchainName>
<ProjectGuid>59B1D629-9DCC-43ed-A0FD-8AB0E4D622AB</ProjectGuid>
<avrdeviceseries>none</avrdeviceseries>
<avrdevice>ATmega328P</avrdevice>
<OutputFileName>$(MSBuildProjectName)</OutputFileName>
<OutputFileExtension>.obj</OutputFileExtension>
<OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
<Language>ASSEMBLY</Language>
<AssemblyName>AY_Emu</AssemblyName>
<Name>AY_Emu</Name>
<RootNamespace>AY_Emu</RootNamespace>
<ToolchainFlavour>Native</ToolchainFlavour>
<EntryFile>$(MSBuildProjectDirectory)\main.asm</EntryFile>
<KeepTimersRunning>true</KeepTimersRunning>
<OverrideVtor>false</OverrideVtor>
<CacheFlash>true</CacheFlash>
<ProgFlashFromRam>true</ProgFlashFromRam>
<RamSnippetAddress>0x20000000</RamSnippetAddress>
<UncachedRange />
<preserveEEPROM>true</preserveEEPROM>
<OverrideVtorValue>exception_table</OverrideVtorValue>
<BootSegment>2</BootSegment>
<ResetRule>0</ResetRule>
<eraseonlaunchrule>0</eraseonlaunchrule>
<EraseKey />
<AsfFrameworkConfig>
<framework-data xmlns="">
<options />
<configurations />
<files />
<documentation help="" />
<offline-documentation help="" />
<dependencies>
<content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.47.0" />
</dependencies>
</framework-data>
</AsfFrameworkConfig>
<avrtool>com.atmel.avrdbg.tool.simulator</avrtool>
<avrtoolserialnumber />
<avrdeviceexpectedsignature>0x1E950F</avrdeviceexpectedsignature>
<com_atmel_avrdbg_tool_simulator>
<ToolOptions xmlns="">
<InterfaceProperties>
</InterfaceProperties>
</ToolOptions>
<ToolType xmlns="">com.atmel.avrdbg.tool.simulator</ToolType>
<ToolNumber xmlns="">
</ToolNumber>
<ToolName xmlns="">Simulator</ToolName>
</com_atmel_avrdbg_tool_simulator>
</PropertyGroup>
<PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
<ToolchainSettings>
<AvrAssembler>
<avrasm.assembler.general.AdditionalIncludeDirectories>
<ListValues>
<Value>%24(PackRepoDir)\atmel\ATmega_DFP\1.3.300\avrasm\inc</Value>
</ListValues>
</avrasm.assembler.general.AdditionalIncludeDirectories>
<avrasm.assembler.general.IncludeFile>m328pdef.inc</avrasm.assembler.general.IncludeFile>
</AvrAssembler>
</ToolchainSettings>
<OutputType>Executable</OutputType>
</PropertyGroup>
<PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
<ToolchainSettings>
<AvrAssembler>
<avrasm.assembler.general.AdditionalIncludeDirectories>
<ListValues>
<Value>%24(PackRepoDir)\atmel\ATmega_DFP\1.3.300\avrasm\inc</Value>
</ListValues>
</avrasm.assembler.general.AdditionalIncludeDirectories>
<avrasm.assembler.general.IncludeFile>m328pdef.inc</avrasm.assembler.general.IncludeFile>
</AvrAssembler>
</ToolchainSettings>
<OutputType>Executable</OutputType>
</PropertyGroup>
<ItemGroup>
<Compile Include="main.asm">
<SubType>Code</SubType>
</Compile>
</ItemGroup>
<Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Assembler.targets" />
</Project>

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Sources/AY_Emu/AY_Emu/AY_Emu.componentinfo.xml Normal file
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<?xml version="1.0" encoding="utf-8"?>
<Store xmlns:i="http://www.w3.org/2001/XMLSchema-instance" xmlns="AtmelPackComponentManagement">
<ProjectComponents>
<ProjectComponent z:Id="i1" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/">
<CApiVersion></CApiVersion>
<CBundle></CBundle>
<CClass>Device</CClass>
<CGroup>Startup</CGroup>
<CSub></CSub>
<CVariant></CVariant>
<CVendor>Atmel</CVendor>
<CVersion>1.3.0</CVersion>
<DefaultRepoPath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs</DefaultRepoPath>
<DependentComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays" />
<Description></Description>
<Files xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
<d4p1:anyType i:type="FileInfo">
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.3.300\avrasm\inc</AbsolutePath>
<Attribute></Attribute>
<Category>include</Category>
<Condition>AVRASM</Condition>
<FileContentHash i:nil="true" />
<FileVersion></FileVersion>
<Name>avrasm/inc</Name>
<SelectString></SelectString>
<SourcePath></SourcePath>
</d4p1:anyType>
<d4p1:anyType i:type="FileInfo">
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.3.300\avrasm\inc\m328pdef.inc</AbsolutePath>
<Attribute></Attribute>
<Category>header</Category>
<Condition>AVRASM</Condition>
<FileContentHash>YpGdK/vCoyGIUkMyqjAbKQ==</FileContentHash>
<FileVersion></FileVersion>
<Name>avrasm/inc/m328pdef.inc</Name>
<SelectString></SelectString>
<SourcePath></SourcePath>
</d4p1:anyType>
<d4p1:anyType i:type="FileInfo">
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.3.300\avrasm\templates\main.asm</AbsolutePath>
<Attribute>template</Attribute>
<Category>source</Category>
<Condition>AVRASM</Condition>
<FileContentHash>kcl2t3QmvnUsYTi7C2+xBA==</FileContentHash>
<FileVersion></FileVersion>
<Name>avrasm/templates/main.asm</Name>
<SelectString>Main file (.asm)</SelectString>
<SourcePath></SourcePath>
</d4p1:anyType>
</Files>
<PackName>ATmega_DFP</PackName>
<PackPath>C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATmega_DFP/1.3.300/Atmel.ATmega_DFP.pdsc</PackPath>
<PackVersion>1.3.300</PackVersion>
<PresentInProject>true</PresentInProject>
<ReferenceConditionId>ATmega328P</ReferenceConditionId>
<RteComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
<d4p1:string></d4p1:string>
</RteComponents>
<Status>Resolved</Status>
<VersionMode>Fixed</VersionMode>
<IsComponentInAtProject>true</IsComponentInAtProject>
</ProjectComponent>
</ProjectComponents>
</Store>

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Sources/AY_Emu/AY_Emu/Debug/AY_Emu.hex Normal file
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Sources/AY_Emu/AY_Emu/Debug/AY_Emu.lss Normal file
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Sources/AY_Emu/AY_Emu/Debug/AY_Emu.map Normal file
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AVRASM ver. 2.2.7 D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm Tue Feb 03 21:02:51 2026
EQU SIGNATURE_000 0000001e
EQU SIGNATURE_001 00000095
EQU SIGNATURE_002 0000000f
EQU UDR0 000000c6
EQU UBRR0L 000000c4
EQU UBRR0H 000000c5
EQU UCSR0C 000000c2
EQU UCSR0B 000000c1
EQU UCSR0A 000000c0
EQU TWAMR 000000bd
EQU TWCR 000000bc
EQU TWDR 000000bb
EQU TWAR 000000ba
EQU TWSR 000000b9
EQU TWBR 000000b8
EQU ASSR 000000b6
EQU OCR2B 000000b4
EQU OCR2A 000000b3
EQU TCNT2 000000b2
EQU TCCR2B 000000b1
EQU TCCR2A 000000b0
EQU OCR1BL 0000008a
EQU OCR1BH 0000008b
EQU OCR1AL 00000088
EQU OCR1AH 00000089
EQU ICR1L 00000086
EQU ICR1H 00000087
EQU TCNT1L 00000084
EQU TCNT1H 00000085
EQU TCCR1C 00000082
EQU TCCR1B 00000081
EQU TCCR1A 00000080
EQU DIDR1 0000007f
EQU DIDR0 0000007e
EQU ADMUX 0000007c
EQU ADCSRB 0000007b
EQU ADCSRA 0000007a
EQU ADCH 00000079
EQU ADCL 00000078
EQU TIMSK2 00000070
EQU TIMSK1 0000006f
EQU TIMSK0 0000006e
EQU PCMSK1 0000006c
EQU PCMSK2 0000006d
EQU PCMSK0 0000006b
EQU EICRA 00000069
EQU PCICR 00000068
EQU OSCCAL 00000066
EQU PRR 00000064
EQU CLKPR 00000061
EQU WDTCSR 00000060
EQU SREG 0000003f
EQU SPL 0000003d
EQU SPH 0000003e
EQU SPMCSR 00000037
EQU MCUCR 00000035
EQU MCUSR 00000034
EQU SMCR 00000033
EQU ACSR 00000030
EQU SPDR 0000002e
EQU SPSR 0000002d
EQU SPCR 0000002c
EQU GPIOR2 0000002b
EQU GPIOR1 0000002a
EQU OCR0B 00000028
EQU OCR0A 00000027
EQU TCNT0 00000026
EQU TCCR0B 00000025
EQU TCCR0A 00000024
EQU GTCCR 00000023
EQU EEARH 00000022
EQU EEARL 00000021
EQU EEDR 00000020
EQU EECR 0000001f
EQU GPIOR0 0000001e
EQU EIMSK 0000001d
EQU EIFR 0000001c
EQU PCIFR 0000001b
EQU TIFR2 00000017
EQU TIFR1 00000016
EQU TIFR0 00000015
EQU PORTD 0000000b
EQU DDRD 0000000a
EQU PIND 00000009
EQU PORTC 00000008
EQU DDRC 00000007
EQU PINC 00000006
EQU PORTB 00000005
EQU DDRB 00000004
EQU PINB 00000003
EQU UDR0_0 00000000
EQU UDR0_1 00000001
EQU UDR0_2 00000002
EQU UDR0_3 00000003
EQU UDR0_4 00000004
EQU UDR0_5 00000005
EQU UDR0_6 00000006
EQU UDR0_7 00000007
EQU MPCM0 00000000
EQU U2X0 00000001
EQU UPE0 00000002
EQU DOR0 00000003
EQU FE0 00000004
EQU UDRE0 00000005
EQU TXC0 00000006
EQU RXC0 00000007
EQU TXB80 00000000
EQU RXB80 00000001
EQU UCSZ02 00000002
EQU TXEN0 00000003
EQU RXEN0 00000004
EQU UDRIE0 00000005
EQU TXCIE0 00000006
EQU RXCIE0 00000007
EQU UCPOL0 00000000
EQU UCSZ00 00000001
EQU UCPHA0 00000001
EQU UCSZ01 00000002
EQU UDORD0 00000002
EQU USBS0 00000003
EQU UPM00 00000004
EQU UPM01 00000005
EQU UMSEL00 00000006
EQU UMSEL0 00000006
EQU UMSEL01 00000007
EQU UMSEL1 00000007
EQU UBRR8 00000000
EQU UBRR9 00000001
EQU UBRR10 00000002
EQU UBRR11 00000003
EQU _UBRR0 00000000
EQU _UBRR1 00000001
EQU UBRR2 00000002
EQU UBRR3 00000003
EQU UBRR4 00000004
EQU UBRR5 00000005
EQU UBRR6 00000006
EQU UBRR7 00000007
EQU TWAM0 00000001
EQU TWAMR0 00000001
EQU TWAM1 00000002
EQU TWAMR1 00000002
EQU TWAM2 00000003
EQU TWAMR2 00000003
EQU TWAM3 00000004
EQU TWAMR3 00000004
EQU TWAM4 00000005
EQU TWAMR4 00000005
EQU TWAM5 00000006
EQU TWAMR5 00000006
EQU TWAM6 00000007
EQU TWAMR6 00000007
EQU TWBR0 00000000
EQU TWBR1 00000001
EQU TWBR2 00000002
EQU TWBR3 00000003
EQU TWBR4 00000004
EQU TWBR5 00000005
EQU TWBR6 00000006
EQU TWBR7 00000007
EQU TWIE 00000000
EQU TWEN 00000002
EQU TWWC 00000003
EQU TWSTO 00000004
EQU TWSTA 00000005
EQU TWEA 00000006
EQU TWINT 00000007
EQU TWPS0 00000000
EQU TWPS1 00000001
EQU TWS3 00000003
EQU TWS4 00000004
EQU TWS5 00000005
EQU TWS6 00000006
EQU TWS7 00000007
EQU TWD0 00000000
EQU TWD1 00000001
EQU TWD2 00000002
EQU TWD3 00000003
EQU TWD4 00000004
EQU TWD5 00000005
EQU TWD6 00000006
EQU TWD7 00000007
EQU TWGCE 00000000
EQU TWA0 00000001
EQU TWA1 00000002
EQU TWA2 00000003
EQU TWA3 00000004
EQU TWA4 00000005
EQU TWA5 00000006
EQU TWA6 00000007
EQU TOIE1 00000000
EQU OCIE1A 00000001
EQU OCIE1B 00000002
EQU ICIE1 00000005
EQU TOV1 00000000
EQU OCF1A 00000001
EQU OCF1B 00000002
EQU ICF1 00000005
EQU WGM10 00000000
EQU WGM11 00000001
EQU COM1B0 00000004
EQU COM1B1 00000005
EQU COM1A0 00000006
EQU COM1A1 00000007
EQU CS10 00000000
EQU CS11 00000001
EQU CS12 00000002
EQU WGM12 00000003
EQU WGM13 00000004
EQU ICES1 00000006
EQU ICNC1 00000007
EQU FOC1B 00000006
EQU FOC1A 00000007
EQU PSRSYNC 00000000
EQU TSM 00000007
EQU TOIE2 00000000
EQU TOIE2A 00000000
EQU OCIE2A 00000001
EQU OCIE2B 00000002
EQU TOV2 00000000
EQU OCF2A 00000001
EQU OCF2B 00000002
EQU WGM20 00000000
EQU WGM21 00000001
EQU COM2B0 00000004
EQU COM2B1 00000005
EQU COM2A0 00000006
EQU COM2A1 00000007
EQU CS20 00000000
EQU CS21 00000001
EQU CS22 00000002
EQU WGM22 00000003
EQU FOC2B 00000006
EQU FOC2A 00000007
EQU TCNT2_0 00000000
EQU TCNT2_1 00000001
EQU TCNT2_2 00000002
EQU TCNT2_3 00000003
EQU TCNT2_4 00000004
EQU TCNT2_5 00000005
EQU TCNT2_6 00000006
EQU TCNT2_7 00000007
EQU OCR2A_0 00000000
EQU OCR2A_1 00000001
EQU OCR2A_2 00000002
EQU OCR2A_3 00000003
EQU OCR2A_4 00000004
EQU OCR2A_5 00000005
EQU OCR2A_6 00000006
EQU OCR2A_7 00000007
EQU OCR2B_0 00000000
EQU OCR2B_1 00000001
EQU OCR2B_2 00000002
EQU OCR2B_3 00000003
EQU OCR2B_4 00000004
EQU OCR2B_5 00000005
EQU OCR2B_6 00000006
EQU OCR2B_7 00000007
EQU TCR2BUB 00000000
EQU TCR2AUB 00000001
EQU OCR2BUB 00000002
EQU OCR2AUB 00000003
EQU TCN2UB 00000004
EQU AS2 00000005
EQU EXCLK 00000006
EQU PSRASY 00000001
EQU PSR2 00000001
EQU MUX0 00000000
EQU MUX1 00000001
EQU MUX2 00000002
EQU MUX3 00000003
EQU ADLAR 00000005
EQU REFS0 00000006
EQU REFS1 00000007
EQU ADPS0 00000000
EQU ADPS1 00000001
EQU ADPS2 00000002
EQU ADIE 00000003
EQU ADIF 00000004
EQU ADATE 00000005
EQU ADSC 00000006
EQU ADEN 00000007
EQU ADTS0 00000000
EQU ADTS1 00000001
EQU ADTS2 00000002
EQU ACME 00000006
EQU ADCH0 00000000
EQU ADCH1 00000001
EQU ADCH2 00000002
EQU ADCH3 00000003
EQU ADCH4 00000004
EQU ADCH5 00000005
EQU ADCH6 00000006
EQU ADCH7 00000007
EQU ADCL0 00000000
EQU ADCL1 00000001
EQU ADCL2 00000002
EQU ADCL3 00000003
EQU ADCL4 00000004
EQU ADCL5 00000005
EQU ADCL6 00000006
EQU ADCL7 00000007
EQU ADC0D 00000000
EQU ADC1D 00000001
EQU ADC2D 00000002
EQU ADC3D 00000003
EQU ADC4D 00000004
EQU ADC5D 00000005
EQU ACIS0 00000000
EQU ACIS1 00000001
EQU ACIC 00000002
EQU ACIE 00000003
EQU ACI 00000004
EQU ACO 00000005
EQU ACBG 00000006
EQU ACD 00000007
EQU AIN0D 00000000
EQU AIN1D 00000001
EQU PORTB0 00000000
EQU PB0 00000000
EQU PORTB1 00000001
EQU PB1 00000001
EQU PORTB2 00000002
EQU PB2 00000002
EQU PORTB3 00000003
EQU PB3 00000003
EQU PORTB4 00000004
EQU PB4 00000004
EQU PORTB5 00000005
EQU PB5 00000005
EQU PORTB6 00000006
EQU PB6 00000006
EQU PORTB7 00000007
EQU PB7 00000007
EQU DDB0 00000000
EQU DDB1 00000001
EQU DDB2 00000002
EQU DDB3 00000003
EQU DDB4 00000004
EQU DDB5 00000005
EQU DDB6 00000006
EQU DDB7 00000007
EQU PINB0 00000000
EQU PINB1 00000001
EQU PINB2 00000002
EQU PINB3 00000003
EQU PINB4 00000004
EQU PINB5 00000005
EQU PINB6 00000006
EQU PINB7 00000007
EQU PORTC0 00000000
EQU PC0 00000000
EQU PORTC1 00000001
EQU PC1 00000001
EQU PORTC2 00000002
EQU PC2 00000002
EQU PORTC3 00000003
EQU PC3 00000003
EQU PORTC4 00000004
EQU PC4 00000004
EQU PORTC5 00000005
EQU PC5 00000005
EQU PORTC6 00000006
EQU PC6 00000006
EQU DDC0 00000000
EQU DDC1 00000001
EQU DDC2 00000002
EQU DDC3 00000003
EQU DDC4 00000004
EQU DDC5 00000005
EQU DDC6 00000006
EQU PINC0 00000000
EQU PINC1 00000001
EQU PINC2 00000002
EQU PINC3 00000003
EQU PINC4 00000004
EQU PINC5 00000005
EQU PINC6 00000006
EQU PORTD0 00000000
EQU PD0 00000000
EQU PORTD1 00000001
EQU PD1 00000001
EQU PORTD2 00000002
EQU PD2 00000002
EQU PORTD3 00000003
EQU PD3 00000003
EQU PORTD4 00000004
EQU PD4 00000004
EQU PORTD5 00000005
EQU PD5 00000005
EQU PORTD6 00000006
EQU PD6 00000006
EQU PORTD7 00000007
EQU PD7 00000007
EQU DDD0 00000000
EQU DDD1 00000001
EQU DDD2 00000002
EQU DDD3 00000003
EQU DDD4 00000004
EQU DDD5 00000005
EQU DDD6 00000006
EQU DDD7 00000007
EQU PIND0 00000000
EQU PIND1 00000001
EQU PIND2 00000002
EQU PIND3 00000003
EQU PIND4 00000004
EQU PIND5 00000005
EQU PIND6 00000006
EQU PIND7 00000007
EQU TOIE0 00000000
EQU OCIE0A 00000001
EQU OCIE0B 00000002
EQU TOV0 00000000
EQU OCF0A 00000001
EQU OCF0B 00000002
EQU WGM00 00000000
EQU WGM01 00000001
EQU COM0B0 00000004
EQU COM0B1 00000005
EQU COM0A0 00000006
EQU COM0A1 00000007
EQU CS00 00000000
EQU CS01 00000001
EQU CS02 00000002
EQU WGM02 00000003
EQU FOC0B 00000006
EQU FOC0A 00000007
EQU TCNT0_0 00000000
EQU TCNT0_1 00000001
EQU TCNT0_2 00000002
EQU TCNT0_3 00000003
EQU TCNT0_4 00000004
EQU TCNT0_5 00000005
EQU TCNT0_6 00000006
EQU TCNT0_7 00000007
EQU OCR0A_0 00000000
EQU OCR0A_1 00000001
EQU OCR0A_2 00000002
EQU OCR0A_3 00000003
EQU OCR0A_4 00000004
EQU OCR0A_5 00000005
EQU OCR0A_6 00000006
EQU OCR0A_7 00000007
EQU OCR0B_0 00000000
EQU OCR0B_1 00000001
EQU OCR0B_2 00000002
EQU OCR0B_3 00000003
EQU OCR0B_4 00000004
EQU OCR0B_5 00000005
EQU OCR0B_6 00000006
EQU OCR0B_7 00000007
EQU PSR10 00000000
EQU ISC00 00000000
EQU ISC01 00000001
EQU ISC10 00000002
EQU ISC11 00000003
EQU INT0 00000000
EQU INT1 00000001
EQU INTF0 00000000
EQU INTF1 00000001
EQU PCIE0 00000000
EQU PCIE1 00000001
EQU PCIE2 00000002
EQU PCINT16 00000000
EQU PCINT17 00000001
EQU PCINT18 00000002
EQU PCINT19 00000003
EQU PCINT20 00000004
EQU PCINT21 00000005
EQU PCINT22 00000006
EQU PCINT23 00000007
EQU PCINT8 00000000
EQU PCINT9 00000001
EQU PCINT10 00000002
EQU PCINT11 00000003
EQU PCINT12 00000004
EQU PCINT13 00000005
EQU PCINT14 00000006
EQU PCINT0 00000000
EQU PCINT1 00000001
EQU PCINT2 00000002
EQU PCINT3 00000003
EQU PCINT4 00000004
EQU PCINT5 00000005
EQU PCINT6 00000006
EQU PCINT7 00000007
EQU PCIF0 00000000
EQU PCIF1 00000001
EQU PCIF2 00000002
EQU SPDR0 00000000
EQU SPDR1 00000001
EQU SPDR2 00000002
EQU SPDR3 00000003
EQU SPDR4 00000004
EQU SPDR5 00000005
EQU SPDR6 00000006
EQU SPDR7 00000007
EQU SPI2X 00000000
EQU WCOL 00000006
EQU SPIF 00000007
EQU SPR0 00000000
EQU SPR1 00000001
EQU CPHA 00000002
EQU CPOL 00000003
EQU MSTR 00000004
EQU DORD 00000005
EQU SPE 00000006
EQU SPIE 00000007
EQU WDP0 00000000
EQU WDP1 00000001
EQU WDP2 00000002
EQU WDE 00000003
EQU WDCE 00000004
EQU WDP3 00000005
EQU WDIE 00000006
EQU WDIF 00000007
EQU SREG_C 00000000
EQU SREG_Z 00000001
EQU SREG_N 00000002
EQU SREG_V 00000003
EQU SREG_S 00000004
EQU SREG_H 00000005
EQU SREG_T 00000006
EQU SREG_I 00000007
EQU CAL0 00000000
EQU CAL1 00000001
EQU CAL2 00000002
EQU CAL3 00000003
EQU CAL4 00000004
EQU CAL5 00000005
EQU CAL6 00000006
EQU CAL7 00000007
EQU CLKPS0 00000000
EQU CLKPS1 00000001
EQU CLKPS2 00000002
EQU CLKPS3 00000003
EQU CLKPCE 00000007
EQU SELFPRGEN 00000000
EQU SPMEN 00000000
EQU PGERS 00000001
EQU PGWRT 00000002
EQU BLBSET 00000003
EQU RWWSRE 00000004
EQU SIGRD 00000005
EQU RWWSB 00000006
EQU SPMIE 00000007
EQU IVCE 00000000
EQU IVSEL 00000001
EQU PUD 00000004
EQU BODSE 00000005
EQU BODS 00000006
EQU PORF 00000000
EQU EXTRF 00000001
EQU EXTREF 00000001
EQU BORF 00000002
EQU WDRF 00000003
EQU SE 00000000
EQU SM0 00000001
EQU SM1 00000002
EQU SM2 00000003
EQU GPIOR20 00000000
EQU GPIOR21 00000001
EQU GPIOR22 00000002
EQU GPIOR23 00000003
EQU GPIOR24 00000004
EQU GPIOR25 00000005
EQU GPIOR26 00000006
EQU GPIOR27 00000007
EQU GPIOR10 00000000
EQU GPIOR11 00000001
EQU GPIOR12 00000002
EQU GPIOR13 00000003
EQU GPIOR14 00000004
EQU GPIOR15 00000005
EQU GPIOR16 00000006
EQU GPIOR17 00000007
EQU GPIOR00 00000000
EQU GPIOR01 00000001
EQU GPIOR02 00000002
EQU GPIOR03 00000003
EQU GPIOR04 00000004
EQU GPIOR05 00000005
EQU GPIOR06 00000006
EQU GPIOR07 00000007
EQU PRADC 00000000
EQU PRUSART0 00000001
EQU PRSPI 00000002
EQU PRTIM1 00000003
EQU PRTIM0 00000005
EQU PRTIM2 00000006
EQU PRTWI 00000007
EQU EEAR0 00000000
EQU EEAR1 00000001
EQU EEAR2 00000002
EQU EEAR3 00000003
EQU EEAR4 00000004
EQU EEAR5 00000005
EQU EEAR6 00000006
EQU EEAR7 00000007
EQU EEAR8 00000000
EQU EEAR9 00000001
EQU EEDR0 00000000
EQU EEDR1 00000001
EQU EEDR2 00000002
EQU EEDR3 00000003
EQU EEDR4 00000004
EQU EEDR5 00000005
EQU EEDR6 00000006
EQU EEDR7 00000007
EQU EERE 00000000
EQU EEPE 00000001
EQU EEMPE 00000002
EQU EERIE 00000003
EQU EEPM0 00000004
EQU EEPM1 00000005
EQU LB1 00000000
EQU LB2 00000001
EQU BLB01 00000002
EQU BLB02 00000003
EQU BLB11 00000004
EQU BLB12 00000005
EQU CKSEL0 00000000
EQU CKSEL1 00000001
EQU CKSEL2 00000002
EQU CKSEL3 00000003
EQU SUT0 00000004
EQU SUT1 00000005
EQU CKOUT 00000006
EQU CKDIV8 00000007
EQU BOOTRST 00000000
EQU BOOTSZ0 00000001
EQU BOOTSZ1 00000002
EQU EESAVE 00000003
EQU WDTON 00000004
EQU SPIEN 00000005
EQU DWEN 00000006
EQU RSTDISBL 00000007
EQU BODLEVEL0 00000000
EQU BODLEVEL1 00000001
EQU BODLEVEL2 00000002
DEF XH r27
DEF XL r26
DEF YH r29
DEF YL r28
DEF ZH r31
DEF ZL r30
EQU FLASHEND 00003fff
EQU IOEND 000000ff
EQU SRAM_START 00000100
EQU SRAM_SIZE 00000800
EQU RAMEND 000008ff
EQU XRAMEND 00000000
EQU E2END 000003ff
EQU EEPROMEND 000003ff
EQU EEADRBITS 0000000a
EQU NRWW_START_ADDR 00003800
EQU NRWW_STOP_ADDR 00003fff
EQU RWW_START_ADDR 00000000
EQU RWW_STOP_ADDR 000037ff
EQU PAGESIZE 00000040
EQU FIRSTBOOTSTART 00003f00
EQU SECONDBOOTSTART 00003e00
EQU THIRDBOOTSTART 00003c00
EQU FOURTHBOOTSTART 00003800
EQU SMALLBOOTSTART 00003f00
EQU LARGEBOOTSTART 00003800
EQU INT0addr 00000002
EQU INT1addr 00000004
EQU PCI0addr 00000006
EQU PCI1addr 00000008
EQU PCI2addr 0000000a
EQU WDTaddr 0000000c
EQU OC2Aaddr 0000000e
EQU OC2Baddr 00000010
EQU OVF2addr 00000012
EQU ICP1addr 00000014
EQU OC1Aaddr 00000016
EQU OC1Baddr 00000018
EQU OVF1addr 0000001a
EQU OC0Aaddr 0000001c
EQU OC0Baddr 0000001e
EQU OVF0addr 00000020
EQU SPIaddr 00000022
EQU URXCaddr 00000024
EQU UDREaddr 00000026
EQU UTXCaddr 00000028
EQU ADCCaddr 0000002a
EQU ERDYaddr 0000002c
EQU ACIaddr 0000002e
EQU TWIaddr 00000030
EQU SPMRaddr 00000032
EQU INT_VECTORS_SIZE 00000034
EQU b0 00000000
EQU b1 00000001
EQU b2 00000002
EQU b3 00000003
EQU b4 00000004
EQU b5 00000005
EQU b6 00000006
EQU b7 00000007
EQU CHIP_SELECTED 0000001e
DEF OutA r0
DEF OutC r1
DEF C1F r2
DEF CntN r3
DEF OutB r4
DEF BusOut1 r5
DEF NoiseAddon r6
DEF C00 r7
DEF CC0 r8
DEF TabE r9
DEF C04 r10
DEF C02 r11
DEF BusData r20
DEF EVal r12
DEF SREGSave r13
DEF RNGL r14
DEF RNGH r15
DEF TMP r16
DEF BusOut2 r17
DEF TabP r18
DEF TNLevel r19
DEF ADDR r30
EQU CCP 00000034
EQU CLKMSR 00000105
EQU BCR 00000107
EQU BOOTEND 00000108
EQU BODCR 00000104
EQU C0SR 00000050
EQU C0D 00000007
EQU C0BG 00000006
EQU C0O 00000005
EQU C0I 00000004
EQU C0IE 00000003
EQU C0IC 00000002
EQU C0IS1 00000001
EQU C0IS0 00000000
EQU C0XR 00000051
EQU C0OE 00000006
EQU C0HSYE 00000005
EQU C0PS0 00000004
EQU C0WKE 00000003
EQU C0FEN 00000002
EQU C0FS1 00000001
EQU C0FS0 00000000
EQU C0TR 00000052
EQU C1SR 0000002f
EQU C1D 00000007
EQU C1BG 00000006
EQU C1O 00000005
EQU C1I 00000004
EQU C1IE 00000003
EQU C1IC 00000002
EQU C1IS1 00000001
EQU C1IS0 00000000
EQU C1XR 0000003a
EQU C1OE 00000006
EQU C1HSYE 00000005
EQU C1PS0 00000004
EQU C1WKE 00000003
EQU C1FEN 00000002
EQU C1FS1 00000001
EQU C1FS0 00000000
EQU C1TR 0000005b
EQU FGPIOE 0000010a
EQU FGPIO 0000010b
EQU DSCR 00000020
EQU DSUEN 00000007
EQU DSMM 00000006
EQU DSD1 00000005
EQU DSD0 00000004
EQU DSN 00000002
EQU DSZ 00000001
EQU DSC 00000000
EQU DSIR 00000021
EQU DSSD 00000022
EQU DSDX 00000030
EQU DSDY 00000031
EQU DSAL 00000058
EQU DSAH 00000059
CSEG _LGT_INIT 00000080
CSEG _INT0_Handler 0000002d
CSEG _INT1_Handler 0000004f
CSEG Volumes 00000005
CSEG EVolumes 0000000d
CSEG Envelopes 0000001d
CSEG RegsMask 00000025
CSEG LATCH_REG_ADDR0 00000038
CSEG LOOP_NOT_INACTIVE 00000031
CSEG exit_int0 00000035
CSEG SELECT_CHIP_ADDR0 00000046
CSEG READ_CHIP0 00000042
DSEG AY1_REG00 00000310
CSEG SELECT_CHIP0_ADDR0 0000004b
CSEG SELECT_CHIP1_ADDR0 0000004d
CSEG LATCH_REG_ADDR1 0000006a
CSEG NO_ENVELOPE_CHANGED_P 00000066
CSEG exit_int1 00000067
CSEG SELECT_CHIP_ADDR1 00000077
CSEG READ_CHIP1 00000073
CSEG SELECT_CHIP0_ADDR1 0000007c
CSEG SELECT_CHIP1_ADDR1 0000007e
CSEG _RESET 000000ae
CSEG LOOP0 000000d2
CSEG _COPY 000001bc
CSEG LOOP1 000000f0
DSEG AY0_CntN 00000400
CSEG LOOP2 000000f8
DSEG Const_L 0000041e
CSEG _MAIN_LOOP 00000129
CSEG AY1_PROCESSING 0000016b
CSEG AY0_PROCESSING 00000130
CSEG RESTORE_AY0_STATE 000001b9
CSEG NOISE_GENERATOR_END_AY0 00000141
DSEG AY_REG06 00000116
DSEG AY_REG07 00000117
DSEG AY_REG08 00000118
DSEG AY_REG09 00000119
DSEG AY_REG10 0000011a
CSEG SAVE_AY0_STATE 000001b8
DSEG OutA0 00000420
DSEG OutC0 00000421
CSEG MAIN_LOOP_END 000001a7
CSEG RESTORE_AY1_STATE 000001bb
CSEG NOISE_GENERATOR_END_AY1 0000017c
DSEG AY1_REG06 00000316
DSEG AY1_CntAL 00000410
DSEG AY1_REG07 00000317
DSEG AY1_REG08 00000318
DSEG AY1_REG09 00000319
DSEG AY1_REG10 0000031a
DSEG OutA1 00000422
DSEG OutC1 00000423
CSEG SAVE_AY1_STATE 000001ba
DSEG AY_REG00 00000110
DSEG AY_REG01 00000111
DSEG AY_REG02 00000112
DSEG AY_REG03 00000113
DSEG AY_REG04 00000114
DSEG AY_REG05 00000115
DSEG AY_REG11 0000011b
DSEG AY_REG12 0000011c
DSEG AY_REG13 0000011d
DSEG AY_REG14 0000011e
DSEG AY_REG15 0000011f
DSEG AY1_REG01 00000311
DSEG AY1_REG02 00000312
DSEG AY1_REG03 00000313
DSEG AY1_REG04 00000314
DSEG AY1_REG05 00000315
DSEG AY1_REG11 0000031b
DSEG AY1_REG12 0000031c
DSEG AY1_REG13 0000031d
DSEG AY1_REG14 0000031e
DSEG AY1_REG15 0000031f
DSEG AY0_CntAL 00000401
DSEG AY0_CntAH 00000402
DSEG AY0_CntBL 00000403
DSEG AY0_CntBH 00000404
DSEG AY0_CntCL 00000405
DSEG AY0_CntCH 00000406
DSEG AY0_CntEL 00000407
DSEG AY0_CntEH 00000408
DSEG AY0_NoiseAddon 00000409
DSEG AY0_RNGH 0000040a
DSEG AY0_RNGL 0000040b
DSEG AY0_TabE 0000040c
DSEG AY0_TabP 0000040d
DSEG AY0_EVal 0000040e
DSEG AY1_CntN 0000040f
DSEG AY1_CntAH 00000411
DSEG AY1_CntBL 00000412
DSEG AY1_CntBH 00000413
DSEG AY1_CntCL 00000414
DSEG AY1_CntCH 00000415
DSEG AY1_CntEL 00000416
DSEG AY1_CntEH 00000417
DSEG AY1_NoiseAddon 00000418
DSEG AY1_RNGH 00000419
DSEG AY1_RNGL 0000041a
DSEG AY1_TabE 0000041b
DSEG AY1_TabP 0000041c
DSEG AY1_EVal 0000041d
DSEG Const_H 0000041f

BIN
Sources/AY_Emu/AY_Emu/Debug/AY_Emu.obj Normal file
View File

Binary file not shown.

130
Sources/AY_Emu/AY_Emu/Debug/AY_Emu.tmp Normal file
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@ -0,0 +1,130 @@
<ASSEMBLER_INFO>
<VERSION>2.2.7</VERSION>
<DEVICE>"ATmega328P"</DEVICE>
<WORKING_DIR>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\Debug</WORKING_DIR>
<INCLUDE_PATH>
<DIR>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.3.300\avrasm\inc</DIR>
<DIR>C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avrassembler\Include</DIR>
<DIR></DIR>
</INCLUDE_PATH>
<SOURCE_FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</SOURCE_FILE>
<INCLUDED_FILES>
<FILE>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.3.300\avrasm\inc\m328pdef.inc</FILE>
</INCLUDED_FILES>
<OBJECT_FILES>
<FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\Debug\AY_Emu.obj</FILE>
</OBJECT_FILES>
<HEX_FILES>
<FILE>AY_Emu.hex</FILE>
</HEX_FILES>
<OUTPUT_FILES>
<FILE>AY_Emu.map</FILE>
<FILE>AY_Emu.lss</FILE>
</OUTPUT_FILES>
<LABELS>
<_LGT_INIT><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>315</LINE></_LGT_INIT>
<_INT0_Handler><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>186</LINE></_INT0_Handler>
<_INT1_Handler><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>240</LINE></_INT1_Handler>
<Volumes><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>161</LINE></Volumes>
<EVolumes><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>163</LINE></EVolumes>
<Envelopes><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>178</LINE></Envelopes>
<RegsMask><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>182</LINE></RegsMask>
<LATCH_REG_ADDR0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>204</LINE></LATCH_REG_ADDR0>
<LOOP_NOT_INACTIVE><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>193</LINE></LOOP_NOT_INACTIVE>
<exit_int0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>199</LINE></exit_int0>
<SELECT_CHIP_ADDR0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>224</LINE></SELECT_CHIP_ADDR0>
<READ_CHIP0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>217</LINE></READ_CHIP0>
<AY1_REG00><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1030</LINE></AY1_REG00>
<SELECT_CHIP0_ADDR0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>231</LINE></SELECT_CHIP0_ADDR0>
<SELECT_CHIP1_ADDR0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>235</LINE></SELECT_CHIP1_ADDR0>
<LATCH_REG_ADDR1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>278</LINE></LATCH_REG_ADDR1>
<NO_ENVELOPE_CHANGED_P><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>271</LINE></NO_ENVELOPE_CHANGED_P>
<exit_int1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>273</LINE></exit_int1>
<SELECT_CHIP_ADDR1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>297</LINE></SELECT_CHIP_ADDR1>
<READ_CHIP1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>290</LINE></READ_CHIP1>
<SELECT_CHIP0_ADDR1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>304</LINE></SELECT_CHIP0_ADDR1>
<SELECT_CHIP1_ADDR1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>308</LINE></SELECT_CHIP1_ADDR1>
<_RESET><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>367</LINE></_RESET>
<LOOP0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>421</LINE></LOOP0>
<_COPY><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>982</LINE></_COPY>
<LOOP1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>462</LINE></LOOP1>
<AY0_CntN><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1065</LINE></AY0_CntN>
<LOOP2><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>473</LINE></LOOP2>
<Const_L><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1097</LINE></Const_L>
<_MAIN_LOOP><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>532</LINE></_MAIN_LOOP>
<AY1_PROCESSING><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>701</LINE></AY1_PROCESSING>
<AY0_PROCESSING><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>545</LINE></AY0_PROCESSING>
<RESTORE_AY0_STATE><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>927</LINE></RESTORE_AY0_STATE>
<NOISE_GENERATOR_END_AY0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>609</LINE></NOISE_GENERATOR_END_AY0>
<AY_REG06><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1007</LINE></AY_REG06>
<AY_REG07><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1009</LINE></AY_REG07>
<AY_REG08><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1011</LINE></AY_REG08>
<AY_REG09><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1013</LINE></AY_REG09>
<AY_REG10><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1015</LINE></AY_REG10>
<SAVE_AY0_STATE><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>908</LINE></SAVE_AY0_STATE>
<OutA0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1100</LINE></OutA0>
<OutC0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1101</LINE></OutC0>
<MAIN_LOOP_END><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>891</LINE></MAIN_LOOP_END>
<RESTORE_AY1_STATE><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>963</LINE></RESTORE_AY1_STATE>
<NOISE_GENERATOR_END_AY1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>764</LINE></NOISE_GENERATOR_END_AY1>
<AY1_REG06><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1042</LINE></AY1_REG06>
<AY1_CntAL><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1083</LINE></AY1_CntAL>
<AY1_REG07><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1044</LINE></AY1_REG07>
<AY1_REG08><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1046</LINE></AY1_REG08>
<AY1_REG09><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1048</LINE></AY1_REG09>
<AY1_REG10><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1050</LINE></AY1_REG10>
<OutA1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1102</LINE></OutA1>
<OutC1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1103</LINE></OutC1>
<SAVE_AY1_STATE><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>945</LINE></SAVE_AY1_STATE>
<AY_REG00><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>995</LINE></AY_REG00>
<AY_REG01><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>997</LINE></AY_REG01>
<AY_REG02><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>999</LINE></AY_REG02>
<AY_REG03><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1001</LINE></AY_REG03>
<AY_REG04><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1003</LINE></AY_REG04>
<AY_REG05><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1005</LINE></AY_REG05>
<AY_REG11><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1017</LINE></AY_REG11>
<AY_REG12><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1019</LINE></AY_REG12>
<AY_REG13><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1021</LINE></AY_REG13>
<AY_REG14><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1023</LINE></AY_REG14>
<AY_REG15><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1025</LINE></AY_REG15>
<AY1_REG01><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1032</LINE></AY1_REG01>
<AY1_REG02><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1034</LINE></AY1_REG02>
<AY1_REG03><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1036</LINE></AY1_REG03>
<AY1_REG04><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1038</LINE></AY1_REG04>
<AY1_REG05><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1040</LINE></AY1_REG05>
<AY1_REG11><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1052</LINE></AY1_REG11>
<AY1_REG12><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1054</LINE></AY1_REG12>
<AY1_REG13><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1056</LINE></AY1_REG13>
<AY1_REG14><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1058</LINE></AY1_REG14>
<AY1_REG15><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1060</LINE></AY1_REG15>
<AY0_CntAL><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1066</LINE></AY0_CntAL>
<AY0_CntAH><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1067</LINE></AY0_CntAH>
<AY0_CntBL><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1068</LINE></AY0_CntBL>
<AY0_CntBH><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1069</LINE></AY0_CntBH>
<AY0_CntCL><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1070</LINE></AY0_CntCL>
<AY0_CntCH><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1071</LINE></AY0_CntCH>
<AY0_CntEL><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1072</LINE></AY0_CntEL>
<AY0_CntEH><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1073</LINE></AY0_CntEH>
<AY0_NoiseAddon><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1074</LINE></AY0_NoiseAddon>
<AY0_RNGH><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1075</LINE></AY0_RNGH>
<AY0_RNGL><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1076</LINE></AY0_RNGL>
<AY0_TabE><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1077</LINE></AY0_TabE>
<AY0_TabP><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1078</LINE></AY0_TabP>
<AY0_EVal><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1079</LINE></AY0_EVal>
<AY1_CntN><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1082</LINE></AY1_CntN>
<AY1_CntAH><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1084</LINE></AY1_CntAH>
<AY1_CntBL><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1085</LINE></AY1_CntBL>
<AY1_CntBH><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1086</LINE></AY1_CntBH>
<AY1_CntCL><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1087</LINE></AY1_CntCL>
<AY1_CntCH><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1088</LINE></AY1_CntCH>
<AY1_CntEL><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1089</LINE></AY1_CntEL>
<AY1_CntEH><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1090</LINE></AY1_CntEH>
<AY1_NoiseAddon><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1091</LINE></AY1_NoiseAddon>
<AY1_RNGH><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1092</LINE></AY1_RNGH>
<AY1_RNGL><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1093</LINE></AY1_RNGL>
<AY1_TabE><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1094</LINE></AY1_TabE>
<AY1_TabP><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1095</LINE></AY1_TabP>
<AY1_EVal><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1096</LINE></AY1_EVal>
<Const_H><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1098</LINE></Const_H>
</LABELS>
</ASSEMBLER_INFO>

BIN
Sources/AY_Emu/AY_Emu/Release/AY_Emu.elf Normal file
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Binary file not shown.

2156
Sources/AY_Emu/AY_Emu/Release/AY_Emu.lss Normal file
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File diff suppressed because it is too large Load Diff

909
Sources/AY_Emu/AY_Emu/Release/AY_Emu.map Normal file
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@ -0,0 +1,909 @@
AVRASM ver. 2.2.7 D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm Wed Aug 19 17:36:34 2026
EQU SIGNATURE_000 0000001e
EQU SIGNATURE_001 00000095
EQU SIGNATURE_002 0000000f
EQU UDR0 000000c6
EQU UBRR0L 000000c4
EQU UBRR0H 000000c5
EQU UCSR0C 000000c2
EQU UCSR0B 000000c1
EQU UCSR0A 000000c0
EQU TWAMR 000000bd
EQU TWCR 000000bc
EQU TWDR 000000bb
EQU TWAR 000000ba
EQU TWSR 000000b9
EQU TWBR 000000b8
EQU ASSR 000000b6
EQU OCR2B 000000b4
EQU OCR2A 000000b3
EQU TCNT2 000000b2
EQU TCCR2B 000000b1
EQU TCCR2A 000000b0
EQU OCR1BL 0000008a
EQU OCR1BH 0000008b
EQU OCR1AL 00000088
EQU OCR1AH 00000089
EQU ICR1L 00000086
EQU ICR1H 00000087
EQU TCNT1L 00000084
EQU TCNT1H 00000085
EQU TCCR1C 00000082
EQU TCCR1B 00000081
EQU TCCR1A 00000080
EQU DIDR1 0000007f
EQU DIDR0 0000007e
EQU ADMUX 0000007c
EQU ADCSRB 0000007b
EQU ADCSRA 0000007a
EQU ADCH 00000079
EQU ADCL 00000078
EQU TIMSK2 00000070
EQU TIMSK1 0000006f
EQU TIMSK0 0000006e
EQU PCMSK1 0000006c
EQU PCMSK2 0000006d
EQU PCMSK0 0000006b
EQU EICRA 00000069
EQU PCICR 00000068
EQU OSCCAL 00000066
EQU PRR 00000064
EQU CLKPR 00000061
EQU WDTCSR 00000060
EQU SREG 0000003f
EQU SPL 0000003d
EQU SPH 0000003e
EQU SPMCSR 00000037
EQU MCUCR 00000035
EQU MCUSR 00000034
EQU SMCR 00000033
EQU ACSR 00000030
EQU SPDR 0000002e
EQU SPSR 0000002d
EQU SPCR 0000002c
EQU GPIOR2 0000002b
EQU GPIOR1 0000002a
EQU OCR0B 00000028
EQU OCR0A 00000027
EQU TCNT0 00000026
EQU TCCR0B 00000025
EQU TCCR0A 00000024
EQU GTCCR 00000023
EQU EEARH 00000022
EQU EEARL 00000021
EQU EEDR 00000020
EQU EECR 0000001f
EQU GPIOR0 0000001e
EQU EIMSK 0000001d
EQU EIFR 0000001c
EQU PCIFR 0000001b
EQU TIFR2 00000017
EQU TIFR1 00000016
EQU TIFR0 00000015
EQU PORTD 0000000b
EQU DDRD 0000000a
EQU PIND 00000009
EQU PORTC 00000008
EQU DDRC 00000007
EQU PINC 00000006
EQU PORTB 00000005
EQU DDRB 00000004
EQU PINB 00000003
EQU UDR0_0 00000000
EQU UDR0_1 00000001
EQU UDR0_2 00000002
EQU UDR0_3 00000003
EQU UDR0_4 00000004
EQU UDR0_5 00000005
EQU UDR0_6 00000006
EQU UDR0_7 00000007
EQU MPCM0 00000000
EQU U2X0 00000001
EQU UPE0 00000002
EQU DOR0 00000003
EQU FE0 00000004
EQU UDRE0 00000005
EQU TXC0 00000006
EQU RXC0 00000007
EQU TXB80 00000000
EQU RXB80 00000001
EQU UCSZ02 00000002
EQU TXEN0 00000003
EQU RXEN0 00000004
EQU UDRIE0 00000005
EQU TXCIE0 00000006
EQU RXCIE0 00000007
EQU UCPOL0 00000000
EQU UCSZ00 00000001
EQU UCPHA0 00000001
EQU UCSZ01 00000002
EQU UDORD0 00000002
EQU USBS0 00000003
EQU UPM00 00000004
EQU UPM01 00000005
EQU UMSEL00 00000006
EQU UMSEL0 00000006
EQU UMSEL01 00000007
EQU UMSEL1 00000007
EQU UBRR8 00000000
EQU UBRR9 00000001
EQU UBRR10 00000002
EQU UBRR11 00000003
EQU _UBRR0 00000000
EQU _UBRR1 00000001
EQU UBRR2 00000002
EQU UBRR3 00000003
EQU UBRR4 00000004
EQU UBRR5 00000005
EQU UBRR6 00000006
EQU UBRR7 00000007
EQU TWAM0 00000001
EQU TWAMR0 00000001
EQU TWAM1 00000002
EQU TWAMR1 00000002
EQU TWAM2 00000003
EQU TWAMR2 00000003
EQU TWAM3 00000004
EQU TWAMR3 00000004
EQU TWAM4 00000005
EQU TWAMR4 00000005
EQU TWAM5 00000006
EQU TWAMR5 00000006
EQU TWAM6 00000007
EQU TWAMR6 00000007
EQU TWBR0 00000000
EQU TWBR1 00000001
EQU TWBR2 00000002
EQU TWBR3 00000003
EQU TWBR4 00000004
EQU TWBR5 00000005
EQU TWBR6 00000006
EQU TWBR7 00000007
EQU TWIE 00000000
EQU TWEN 00000002
EQU TWWC 00000003
EQU TWSTO 00000004
EQU TWSTA 00000005
EQU TWEA 00000006
EQU TWINT 00000007
EQU TWPS0 00000000
EQU TWPS1 00000001
EQU TWS3 00000003
EQU TWS4 00000004
EQU TWS5 00000005
EQU TWS6 00000006
EQU TWS7 00000007
EQU TWD0 00000000
EQU TWD1 00000001
EQU TWD2 00000002
EQU TWD3 00000003
EQU TWD4 00000004
EQU TWD5 00000005
EQU TWD6 00000006
EQU TWD7 00000007
EQU TWGCE 00000000
EQU TWA0 00000001
EQU TWA1 00000002
EQU TWA2 00000003
EQU TWA3 00000004
EQU TWA4 00000005
EQU TWA5 00000006
EQU TWA6 00000007
EQU TOIE1 00000000
EQU OCIE1A 00000001
EQU OCIE1B 00000002
EQU ICIE1 00000005
EQU TOV1 00000000
EQU OCF1A 00000001
EQU OCF1B 00000002
EQU ICF1 00000005
EQU WGM10 00000000
EQU WGM11 00000001
EQU COM1B0 00000004
EQU COM1B1 00000005
EQU COM1A0 00000006
EQU COM1A1 00000007
EQU CS10 00000000
EQU CS11 00000001
EQU CS12 00000002
EQU WGM12 00000003
EQU WGM13 00000004
EQU ICES1 00000006
EQU ICNC1 00000007
EQU FOC1B 00000006
EQU FOC1A 00000007
EQU PSRSYNC 00000000
EQU TSM 00000007
EQU TOIE2 00000000
EQU TOIE2A 00000000
EQU OCIE2A 00000001
EQU OCIE2B 00000002
EQU TOV2 00000000
EQU OCF2A 00000001
EQU OCF2B 00000002
EQU WGM20 00000000
EQU WGM21 00000001
EQU COM2B0 00000004
EQU COM2B1 00000005
EQU COM2A0 00000006
EQU COM2A1 00000007
EQU CS20 00000000
EQU CS21 00000001
EQU CS22 00000002
EQU WGM22 00000003
EQU FOC2B 00000006
EQU FOC2A 00000007
EQU TCNT2_0 00000000
EQU TCNT2_1 00000001
EQU TCNT2_2 00000002
EQU TCNT2_3 00000003
EQU TCNT2_4 00000004
EQU TCNT2_5 00000005
EQU TCNT2_6 00000006
EQU TCNT2_7 00000007
EQU OCR2A_0 00000000
EQU OCR2A_1 00000001
EQU OCR2A_2 00000002
EQU OCR2A_3 00000003
EQU OCR2A_4 00000004
EQU OCR2A_5 00000005
EQU OCR2A_6 00000006
EQU OCR2A_7 00000007
EQU OCR2B_0 00000000
EQU OCR2B_1 00000001
EQU OCR2B_2 00000002
EQU OCR2B_3 00000003
EQU OCR2B_4 00000004
EQU OCR2B_5 00000005
EQU OCR2B_6 00000006
EQU OCR2B_7 00000007
EQU TCR2BUB 00000000
EQU TCR2AUB 00000001
EQU OCR2BUB 00000002
EQU OCR2AUB 00000003
EQU TCN2UB 00000004
EQU AS2 00000005
EQU EXCLK 00000006
EQU PSRASY 00000001
EQU PSR2 00000001
EQU MUX0 00000000
EQU MUX1 00000001
EQU MUX2 00000002
EQU MUX3 00000003
EQU ADLAR 00000005
EQU REFS0 00000006
EQU REFS1 00000007
EQU ADPS0 00000000
EQU ADPS1 00000001
EQU ADPS2 00000002
EQU ADIE 00000003
EQU ADIF 00000004
EQU ADATE 00000005
EQU ADSC 00000006
EQU ADEN 00000007
EQU ADTS0 00000000
EQU ADTS1 00000001
EQU ADTS2 00000002
EQU ACME 00000006
EQU ADCH0 00000000
EQU ADCH1 00000001
EQU ADCH2 00000002
EQU ADCH3 00000003
EQU ADCH4 00000004
EQU ADCH5 00000005
EQU ADCH6 00000006
EQU ADCH7 00000007
EQU ADCL0 00000000
EQU ADCL1 00000001
EQU ADCL2 00000002
EQU ADCL3 00000003
EQU ADCL4 00000004
EQU ADCL5 00000005
EQU ADCL6 00000006
EQU ADCL7 00000007
EQU ADC0D 00000000
EQU ADC1D 00000001
EQU ADC2D 00000002
EQU ADC3D 00000003
EQU ADC4D 00000004
EQU ADC5D 00000005
EQU ACIS0 00000000
EQU ACIS1 00000001
EQU ACIC 00000002
EQU ACIE 00000003
EQU ACI 00000004
EQU ACO 00000005
EQU ACBG 00000006
EQU ACD 00000007
EQU AIN0D 00000000
EQU AIN1D 00000001
EQU PORTB0 00000000
EQU PB0 00000000
EQU PORTB1 00000001
EQU PB1 00000001
EQU PORTB2 00000002
EQU PB2 00000002
EQU PORTB3 00000003
EQU PB3 00000003
EQU PORTB4 00000004
EQU PB4 00000004
EQU PORTB5 00000005
EQU PB5 00000005
EQU PORTB6 00000006
EQU PB6 00000006
EQU PORTB7 00000007
EQU PB7 00000007
EQU DDB0 00000000
EQU DDB1 00000001
EQU DDB2 00000002
EQU DDB3 00000003
EQU DDB4 00000004
EQU DDB5 00000005
EQU DDB6 00000006
EQU DDB7 00000007
EQU PINB0 00000000
EQU PINB1 00000001
EQU PINB2 00000002
EQU PINB3 00000003
EQU PINB4 00000004
EQU PINB5 00000005
EQU PINB6 00000006
EQU PINB7 00000007
EQU PORTC0 00000000
EQU PC0 00000000
EQU PORTC1 00000001
EQU PC1 00000001
EQU PORTC2 00000002
EQU PC2 00000002
EQU PORTC3 00000003
EQU PC3 00000003
EQU PORTC4 00000004
EQU PC4 00000004
EQU PORTC5 00000005
EQU PC5 00000005
EQU PORTC6 00000006
EQU PC6 00000006
EQU DDC0 00000000
EQU DDC1 00000001
EQU DDC2 00000002
EQU DDC3 00000003
EQU DDC4 00000004
EQU DDC5 00000005
EQU DDC6 00000006
EQU PINC0 00000000
EQU PINC1 00000001
EQU PINC2 00000002
EQU PINC3 00000003
EQU PINC4 00000004
EQU PINC5 00000005
EQU PINC6 00000006
EQU PORTD0 00000000
EQU PD0 00000000
EQU PORTD1 00000001
EQU PD1 00000001
EQU PORTD2 00000002
EQU PD2 00000002
EQU PORTD3 00000003
EQU PD3 00000003
EQU PORTD4 00000004
EQU PD4 00000004
EQU PORTD5 00000005
EQU PD5 00000005
EQU PORTD6 00000006
EQU PD6 00000006
EQU PORTD7 00000007
EQU PD7 00000007
EQU DDD0 00000000
EQU DDD1 00000001
EQU DDD2 00000002
EQU DDD3 00000003
EQU DDD4 00000004
EQU DDD5 00000005
EQU DDD6 00000006
EQU DDD7 00000007
EQU PIND0 00000000
EQU PIND1 00000001
EQU PIND2 00000002
EQU PIND3 00000003
EQU PIND4 00000004
EQU PIND5 00000005
EQU PIND6 00000006
EQU PIND7 00000007
EQU TOIE0 00000000
EQU OCIE0A 00000001
EQU OCIE0B 00000002
EQU TOV0 00000000
EQU OCF0A 00000001
EQU OCF0B 00000002
EQU WGM00 00000000
EQU WGM01 00000001
EQU COM0B0 00000004
EQU COM0B1 00000005
EQU COM0A0 00000006
EQU COM0A1 00000007
EQU CS00 00000000
EQU CS01 00000001
EQU CS02 00000002
EQU WGM02 00000003
EQU FOC0B 00000006
EQU FOC0A 00000007
EQU TCNT0_0 00000000
EQU TCNT0_1 00000001
EQU TCNT0_2 00000002
EQU TCNT0_3 00000003
EQU TCNT0_4 00000004
EQU TCNT0_5 00000005
EQU TCNT0_6 00000006
EQU TCNT0_7 00000007
EQU OCR0A_0 00000000
EQU OCR0A_1 00000001
EQU OCR0A_2 00000002
EQU OCR0A_3 00000003
EQU OCR0A_4 00000004
EQU OCR0A_5 00000005
EQU OCR0A_6 00000006
EQU OCR0A_7 00000007
EQU OCR0B_0 00000000
EQU OCR0B_1 00000001
EQU OCR0B_2 00000002
EQU OCR0B_3 00000003
EQU OCR0B_4 00000004
EQU OCR0B_5 00000005
EQU OCR0B_6 00000006
EQU OCR0B_7 00000007
EQU PSR10 00000000
EQU ISC00 00000000
EQU ISC01 00000001
EQU ISC10 00000002
EQU ISC11 00000003
EQU INT0 00000000
EQU INT1 00000001
EQU INTF0 00000000
EQU INTF1 00000001
EQU PCIE0 00000000
EQU PCIE1 00000001
EQU PCIE2 00000002
EQU PCINT16 00000000
EQU PCINT17 00000001
EQU PCINT18 00000002
EQU PCINT19 00000003
EQU PCINT20 00000004
EQU PCINT21 00000005
EQU PCINT22 00000006
EQU PCINT23 00000007
EQU PCINT8 00000000
EQU PCINT9 00000001
EQU PCINT10 00000002
EQU PCINT11 00000003
EQU PCINT12 00000004
EQU PCINT13 00000005
EQU PCINT14 00000006
EQU PCINT0 00000000
EQU PCINT1 00000001
EQU PCINT2 00000002
EQU PCINT3 00000003
EQU PCINT4 00000004
EQU PCINT5 00000005
EQU PCINT6 00000006
EQU PCINT7 00000007
EQU PCIF0 00000000
EQU PCIF1 00000001
EQU PCIF2 00000002
EQU SPDR0 00000000
EQU SPDR1 00000001
EQU SPDR2 00000002
EQU SPDR3 00000003
EQU SPDR4 00000004
EQU SPDR5 00000005
EQU SPDR6 00000006
EQU SPDR7 00000007
EQU SPI2X 00000000
EQU WCOL 00000006
EQU SPIF 00000007
EQU SPR0 00000000
EQU SPR1 00000001
EQU CPHA 00000002
EQU CPOL 00000003
EQU MSTR 00000004
EQU DORD 00000005
EQU SPE 00000006
EQU SPIE 00000007
EQU WDP0 00000000
EQU WDP1 00000001
EQU WDP2 00000002
EQU WDE 00000003
EQU WDCE 00000004
EQU WDP3 00000005
EQU WDIE 00000006
EQU WDIF 00000007
EQU SREG_C 00000000
EQU SREG_Z 00000001
EQU SREG_N 00000002
EQU SREG_V 00000003
EQU SREG_S 00000004
EQU SREG_H 00000005
EQU SREG_T 00000006
EQU SREG_I 00000007
EQU CAL0 00000000
EQU CAL1 00000001
EQU CAL2 00000002
EQU CAL3 00000003
EQU CAL4 00000004
EQU CAL5 00000005
EQU CAL6 00000006
EQU CAL7 00000007
EQU CLKPS0 00000000
EQU CLKPS1 00000001
EQU CLKPS2 00000002
EQU CLKPS3 00000003
EQU CLKPCE 00000007
EQU SELFPRGEN 00000000
EQU SPMEN 00000000
EQU PGERS 00000001
EQU PGWRT 00000002
EQU BLBSET 00000003
EQU RWWSRE 00000004
EQU SIGRD 00000005
EQU RWWSB 00000006
EQU SPMIE 00000007
EQU IVCE 00000000
EQU IVSEL 00000001
EQU PUD 00000004
EQU BODSE 00000005
EQU BODS 00000006
EQU PORF 00000000
EQU EXTRF 00000001
EQU EXTREF 00000001
EQU BORF 00000002
EQU WDRF 00000003
EQU SE 00000000
EQU SM0 00000001
EQU SM1 00000002
EQU SM2 00000003
EQU GPIOR20 00000000
EQU GPIOR21 00000001
EQU GPIOR22 00000002
EQU GPIOR23 00000003
EQU GPIOR24 00000004
EQU GPIOR25 00000005
EQU GPIOR26 00000006
EQU GPIOR27 00000007
EQU GPIOR10 00000000
EQU GPIOR11 00000001
EQU GPIOR12 00000002
EQU GPIOR13 00000003
EQU GPIOR14 00000004
EQU GPIOR15 00000005
EQU GPIOR16 00000006
EQU GPIOR17 00000007
EQU GPIOR00 00000000
EQU GPIOR01 00000001
EQU GPIOR02 00000002
EQU GPIOR03 00000003
EQU GPIOR04 00000004
EQU GPIOR05 00000005
EQU GPIOR06 00000006
EQU GPIOR07 00000007
EQU PRADC 00000000
EQU PRUSART0 00000001
EQU PRSPI 00000002
EQU PRTIM1 00000003
EQU PRTIM0 00000005
EQU PRTIM2 00000006
EQU PRTWI 00000007
EQU EEAR0 00000000
EQU EEAR1 00000001
EQU EEAR2 00000002
EQU EEAR3 00000003
EQU EEAR4 00000004
EQU EEAR5 00000005
EQU EEAR6 00000006
EQU EEAR7 00000007
EQU EEAR8 00000000
EQU EEAR9 00000001
EQU EEDR0 00000000
EQU EEDR1 00000001
EQU EEDR2 00000002
EQU EEDR3 00000003
EQU EEDR4 00000004
EQU EEDR5 00000005
EQU EEDR6 00000006
EQU EEDR7 00000007
EQU EERE 00000000
EQU EEPE 00000001
EQU EEMPE 00000002
EQU EERIE 00000003
EQU EEPM0 00000004
EQU EEPM1 00000005
EQU LB1 00000000
EQU LB2 00000001
EQU BLB01 00000002
EQU BLB02 00000003
EQU BLB11 00000004
EQU BLB12 00000005
EQU CKSEL0 00000000
EQU CKSEL1 00000001
EQU CKSEL2 00000002
EQU CKSEL3 00000003
EQU SUT0 00000004
EQU SUT1 00000005
EQU CKOUT 00000006
EQU CKDIV8 00000007
EQU BOOTRST 00000000
EQU BOOTSZ0 00000001
EQU BOOTSZ1 00000002
EQU EESAVE 00000003
EQU WDTON 00000004
EQU SPIEN 00000005
EQU DWEN 00000006
EQU RSTDISBL 00000007
EQU BODLEVEL0 00000000
EQU BODLEVEL1 00000001
EQU BODLEVEL2 00000002
DEF XH r27
DEF XL r26
DEF YH r29
DEF YL r28
DEF ZH r31
DEF ZL r30
EQU FLASHEND 00003fff
EQU IOEND 000000ff
EQU SRAM_START 00000100
EQU SRAM_SIZE 00000800
EQU RAMEND 000008ff
EQU XRAMEND 00000000
EQU E2END 000003ff
EQU EEPROMEND 000003ff
EQU EEADRBITS 0000000a
EQU NRWW_START_ADDR 00003800
EQU NRWW_STOP_ADDR 00003fff
EQU RWW_START_ADDR 00000000
EQU RWW_STOP_ADDR 000037ff
EQU PAGESIZE 00000040
EQU FIRSTBOOTSTART 00003f00
EQU SECONDBOOTSTART 00003e00
EQU THIRDBOOTSTART 00003c00
EQU FOURTHBOOTSTART 00003800
EQU SMALLBOOTSTART 00003f00
EQU LARGEBOOTSTART 00003800
EQU INT0addr 00000002
EQU INT1addr 00000004
EQU PCI0addr 00000006
EQU PCI1addr 00000008
EQU PCI2addr 0000000a
EQU WDTaddr 0000000c
EQU OC2Aaddr 0000000e
EQU OC2Baddr 00000010
EQU OVF2addr 00000012
EQU ICP1addr 00000014
EQU OC1Aaddr 00000016
EQU OC1Baddr 00000018
EQU OVF1addr 0000001a
EQU OC0Aaddr 0000001c
EQU OC0Baddr 0000001e
EQU OVF0addr 00000020
EQU SPIaddr 00000022
EQU URXCaddr 00000024
EQU UDREaddr 00000026
EQU UTXCaddr 00000028
EQU ADCCaddr 0000002a
EQU ERDYaddr 0000002c
EQU ACIaddr 0000002e
EQU TWIaddr 00000030
EQU SPMRaddr 00000032
EQU INT_VECTORS_SIZE 00000034
EQU b0 00000000
EQU b1 00000001
EQU b2 00000002
EQU b3 00000003
EQU b4 00000004
EQU b5 00000005
EQU b6 00000006
EQU b7 00000007
EQU CHIP_SELECTED 0000001e
DEF OutA0 r0
DEF OutC0 r1
DEF OutA1 r2
DEF CntN r3
DEF OutB r4
DEF BusOut1 r5
DEF NoiseAddon r6
DEF C00 r7
DEF CC0 r8
DEF TabE_AY0 r9
DEF OutC1 r10
DEF EVal_AY1 r11
DEF EVal_AY0 r12
DEF C21 r13
DEF RNGL r14
DEF RNGH r15
DEF TNLevel_AY1 r16
DEF BusOut2 r17
DEF TabP_AY0 r18
DEF TNLevel_AY0 r19
DEF BusData r20
DEF TMP r21
DEF TabE_AY1 r22
DEF TabP_AY1 r23
DEF CntEL_AY0 r24
DEF CntEH_AY0 r25
DEF CntEL_AY1 r26
DEF CntEH_AY1 r27
DEF ADDR r30
EQU CCP 00000034
EQU CLKMSR 00000105
EQU BCR 00000107
EQU BOOTEND 00000108
EQU BODCR 00000104
EQU PMCR 000000f2
EQU PMCE 00000007
EQU CLKFS 00000006
EQU CLKSS 00000005
EQU WCLKS 00000004
EQU WCES 00000004
EQU OSCKEN 00000003
EQU OSCMEN 00000002
EQU RCKEN 00000001
EQU RCMEN 00000000
EQU PMX2 000000f0
EQU IOCR 000000f0
EQU IOCE 00000007
EQU STSC1 00000006
EQU STSC0 00000005
EQU XIEN 00000002
EQU E6EN 00000001
EQU REFIOEN 00000001
EQU C6EN 00000000
EQU RSTIOEN 00000000
EQU C0SR 00000050
EQU C0D 00000007
EQU C0BG 00000006
EQU C0O 00000005
EQU C0I 00000004
EQU C0IE 00000003
EQU C0IC 00000002
EQU C0IS1 00000001
EQU C0IS0 00000000
EQU C0XR 00000051
EQU C0OE 00000006
EQU C0HSYE 00000005
EQU C0PS0 00000004
EQU C0WKE 00000003
EQU C0FEN 00000002
EQU C0FS1 00000001
EQU C0FS0 00000000
EQU C0TR 00000052
EQU C1SR 0000002f
EQU C1D 00000007
EQU C1BG 00000006
EQU C1O 00000005
EQU C1I 00000004
EQU C1IE 00000003
EQU C1IC 00000002
EQU C1IS1 00000001
EQU C1IS0 00000000
EQU C1XR 0000003a
EQU C1OE 00000006
EQU C1HSYE 00000005
EQU C1PS0 00000004
EQU C1WKE 00000003
EQU C1FEN 00000002
EQU C1FS1 00000001
EQU C1FS0 00000000
EQU C1TR 0000005b
EQU DSCR 00000020
EQU DSUEN 00000007
EQU DSMM 00000006
EQU DSD1 00000005
EQU DSD0 00000004
EQU DSZ 00000002
EQU DSN 00000001
EQU DSC 00000000
EQU DSIR 00000021
EQU DSSD 00000022
EQU DSDX 00000030
EQU DSDY 00000031
EQU DSAL 00000058
EQU DSAH 00000059
CSEG _LGT_INIT 00000085
CSEG _INT0_Handler 0000002d
CSEG _INT1_Handler 00000050
CSEG Volumes 00000005
CSEG EVolumes 0000000d
CSEG Envelopes 0000001d
CSEG RegsMask 00000025
CSEG LATCH_REG_ADDR0 00000039
CSEG LOOP_NOT_INACTIVE 00000031
CSEG exit_int0 00000035
CSEG SELECT_CHIP_ADDR0 00000047
CSEG READ_CHIP0 00000043
DSEG AY1_REG00 00000310
CSEG SELECT_CHIP0_ADDR0 0000004c
CSEG SELECT_CHIP1_ADDR0 0000004e
CSEG LATCH_REG_ADDR1 0000006f
CSEG NO_ENVELOPE_CHANGED_P 0000006a
CSEG exit_int1 0000006c
CSEG SELECT_CHIP_ADDR1 0000007c
CSEG READ_CHIP1 00000078
CSEG SELECT_CHIP0_ADDR1 00000081
CSEG SELECT_CHIP1_ADDR1 00000083
CSEG wait 0000009f
CSEG _RESET 000000ab
CSEG LOOP0 000000c6
CSEG _COPY 0000027f
CSEG LOOP1 000000e4
DSEG AY0_CntAL 00000260
CSEG LOOP2 000000ec
CSEG CALIB_WAIT 00000112
CSEG CALIB_DO 0000012b
CSEG CALIB_END 00000149
CSEG CALIB_DIV_LOOP 00000137
CSEG CALIB_DIV_SUB 0000013c
CSEG CALIB_DIV_DONE 00000143
CSEG NO_CALIBRATION 00000153
DSEG ConstL 0000026c
CSEG _MAIN_LOOP 0000017b
CSEG NOISE_GENERATOR_END 00000196
DSEG AY0_REG06 00000116
DSEG AY1_REG06 00000316
CSEG LESS 00000188
CSEG NO_ENVELOPE_CHANGED_AY0 0000019e
DSEG AY0_REG13 0000011d
CSEG E_NEXT_STEP_AY0 000001aa
CSEG ENVELOPE_GENERATOR_END_AY0 000001b3
CSEG E_NEXT_PERIOD_AY0 000001a3
DSEG AY0_REG11 0000011b
DSEG AY0_REG12 0000011c
CSEG NO_ENVELOPE_CHANGED_AY1 000001bb
DSEG AY1_REG13 0000031d
CSEG E_NEXT_STEP_AY1 000001c7
CSEG ENVELOPE_GENERATOR_END_AY1 000001d0
CSEG E_NEXT_PERIOD_AY1 000001c0
DSEG AY1_REG11 0000031b
DSEG AY1_REG12 0000031c
CSEG GENERATORS_AY1 000001fe
CSEG CH_A_NO_CHANGE_AY0 000001de
DSEG AY0_REG00 00000110
DSEG AY0_CntBL 00000262
CSEG CH_B_NO_CHANGE_AY0 000001ec
DSEG AY0_REG02 00000112
DSEG AY0_CntCL 00000264
CSEG CH_C_NO_CHANGE_AY0 000001fa
DSEG AY0_REG04 00000114
CSEG GENERATORS_END 0000022f
DSEG AY1_CntAL 00000266
CSEG CH_A_NO_CHANGE_AY1 0000020c
DSEG AY1_CntBL 00000268
CSEG CH_B_NO_CHANGE_AY1 0000021c
DSEG AY1_REG02 00000312
DSEG AY1_CntCL 0000026a
CSEG CH_C_NO_CHANGE_AY1 0000022c
DSEG AY1_REG04 00000314
DSEG AY0_REG07 00000117
DSEG AY0_REG08 00000118
DSEG AY0_REG09 00000119
DSEG AY0_REG10 0000011a
DSEG AY1_REG07 00000317
DSEG AY1_REG08 00000318
DSEG AY1_REG09 00000319
DSEG AY1_REG10 0000031a
DSEG AY0_REG01 00000111
DSEG AY0_REG03 00000113
DSEG AY0_REG05 00000115
DSEG AY0_REG14 0000011e
DSEG AY0_REG15 0000011f
DSEG AY0_CntAH 00000261
DSEG AY0_CntBH 00000263
DSEG AY0_CntCH 00000265
DSEG AY1_CntAH 00000267
DSEG AY1_CntBH 00000269
DSEG AY1_CntCH 0000026b
DSEG ConstH 0000026d
DSEG AY1_REG01 00000311
DSEG AY1_REG03 00000313
DSEG AY1_REG05 00000315
DSEG AY1_REG14 0000031e
DSEG AY1_REG15 0000031f

BIN
Sources/AY_Emu/AY_Emu/Release/AY_Emu.obj Normal file
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Sources/AY_Emu/AY_Emu/Release/AY_Emu.tmp Normal file
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@ -0,0 +1,125 @@
<ASSEMBLER_INFO>
<VERSION>2.2.7</VERSION>
<DEVICE>"ATmega328P"</DEVICE>
<WORKING_DIR>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\Release</WORKING_DIR>
<INCLUDE_PATH>
<DIR>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.3.300\avrasm\inc</DIR>
<DIR>C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avrassembler\Include</DIR>
<DIR></DIR>
</INCLUDE_PATH>
<SOURCE_FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</SOURCE_FILE>
<INCLUDED_FILES>
<FILE>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.3.300\avrasm\inc\m328pdef.inc</FILE>
</INCLUDED_FILES>
<OBJECT_FILES>
<FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\Release\AY_Emu.obj</FILE>
</OBJECT_FILES>
<HEX_FILES>
<FILE>AY_Emu.hex</FILE>
</HEX_FILES>
<OUTPUT_FILES>
<FILE>AY_Emu.map</FILE>
<FILE>AY_Emu.lss</FILE>
</OUTPUT_FILES>
<LABELS>
<_LGT_INIT><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>334</LINE></_LGT_INIT>
<_INT0_Handler><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>197</LINE></_INT0_Handler>
<_INT1_Handler><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>252</LINE></_INT1_Handler>
<Volumes><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>172</LINE></Volumes>
<EVolumes><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>174</LINE></EVolumes>
<Envelopes><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>189</LINE></Envelopes>
<RegsMask><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>193</LINE></RegsMask>
<LATCH_REG_ADDR0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>216</LINE></LATCH_REG_ADDR0>
<LOOP_NOT_INACTIVE><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>204</LINE></LOOP_NOT_INACTIVE>
<exit_int0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>210</LINE></exit_int0>
<SELECT_CHIP_ADDR0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>236</LINE></SELECT_CHIP_ADDR0>
<READ_CHIP0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>229</LINE></READ_CHIP0>
<AY1_REG00><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1071</LINE></AY1_REG00>
<SELECT_CHIP0_ADDR0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>243</LINE></SELECT_CHIP0_ADDR0>
<SELECT_CHIP1_ADDR0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>247</LINE></SELECT_CHIP1_ADDR0>
<LATCH_REG_ADDR1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>297</LINE></LATCH_REG_ADDR1>
<NO_ENVELOPE_CHANGED_P><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>289</LINE></NO_ENVELOPE_CHANGED_P>
<exit_int1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>292</LINE></exit_int1>
<SELECT_CHIP_ADDR1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>316</LINE></SELECT_CHIP_ADDR1>
<READ_CHIP1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>309</LINE></READ_CHIP1>
<SELECT_CHIP0_ADDR1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>323</LINE></SELECT_CHIP0_ADDR1>
<SELECT_CHIP1_ADDR1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>327</LINE></SELECT_CHIP1_ADDR1>
<wait><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>383</LINE></wait>
<_RESET><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>402</LINE></_RESET>
<LOOP0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>437</LINE></LOOP0>
<_COPY><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1003</LINE></_COPY>
<LOOP1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>478</LINE></LOOP1>
<AY0_CntAL><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1051</LINE></AY0_CntAL>
<LOOP2><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>489</LINE></LOOP2>
<CALIB_WAIT><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>537</LINE></CALIB_WAIT>
<CALIB_DO><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>562</LINE></CALIB_DO>
<CALIB_END><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>610</LINE></CALIB_END>
<CALIB_DIV_LOOP><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>584</LINE></CALIB_DIV_LOOP>
<CALIB_DIV_SUB><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>591</LINE></CALIB_DIV_SUB>
<CALIB_DIV_DONE><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>600</LINE></CALIB_DIV_DONE>
<NO_CALIBRATION><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>632</LINE></NO_CALIBRATION>
<ConstL><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1066</LINE></ConstL>
<_MAIN_LOOP><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>680</LINE></_MAIN_LOOP>
<NOISE_GENERATOR_END><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>709</LINE></NOISE_GENERATOR_END>
<AY0_REG06><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1028</LINE></AY0_REG06>
<AY1_REG06><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1083</LINE></AY1_REG06>
<LESS><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>694</LINE></LESS>
<NO_ENVELOPE_CHANGED_AY0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>724</LINE></NO_ENVELOPE_CHANGED_AY0>
<AY0_REG13><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1042</LINE></AY0_REG13>
<E_NEXT_STEP_AY0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>740</LINE></E_NEXT_STEP_AY0>
<ENVELOPE_GENERATOR_END_AY0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>749</LINE></ENVELOPE_GENERATOR_END_AY0>
<E_NEXT_PERIOD_AY0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>731</LINE></E_NEXT_PERIOD_AY0>
<AY0_REG11><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1038</LINE></AY0_REG11>
<AY0_REG12><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1040</LINE></AY0_REG12>
<NO_ENVELOPE_CHANGED_AY1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>764</LINE></NO_ENVELOPE_CHANGED_AY1>
<AY1_REG13><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1097</LINE></AY1_REG13>
<E_NEXT_STEP_AY1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>780</LINE></E_NEXT_STEP_AY1>
<ENVELOPE_GENERATOR_END_AY1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>789</LINE></ENVELOPE_GENERATOR_END_AY1>
<E_NEXT_PERIOD_AY1><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>771</LINE></E_NEXT_PERIOD_AY1>
<AY1_REG11><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1093</LINE></AY1_REG11>
<AY1_REG12><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1095</LINE></AY1_REG12>
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<CH_A_NO_CHANGE_AY0><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>808</LINE></CH_A_NO_CHANGE_AY0>
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<AY0_CntAH><FILE>D:\ST\AY_Emul_Version26_0\AY_Emu_Prj\AY_Emu\AY_Emu\main.asm</FILE><LINE>1052</LINE></AY0_CntAH>
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</LABELS>
</ASSEMBLER_INFO>

80
Sources/AY_Emu/AY_Emu/Release/AY_Emu_40MHz.hex Normal file
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Sources/AY_Emu/AY_Emu/Release/AY_Emu_INT_37MHz_Auto_Calib.hex Normal file
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9
Sources/AY_Emu/AY_Emu/Release/Flashing.bat Normal file
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@ -0,0 +1,9 @@
@echo off
cd /d "%~dp0"
set Path=%Path%;D:\ST\Spectrum\AVRDUDESS-2.20-portable
avrdude -c arduino_as_isp -P COM20 -b 19200 -p lgt328p -U lfuse:w:0xE2:m -U hfuse:w:0xDF:m -U efuse:w:0xFD:m -U flash:w:AY_Emu.hex:a
pause
REM avrdude.exe -c arduino_as_isp -p lgt328p -P COM20 -b 19200 -U lfuse:w:0xFF:m -U hfuse:w:0xFF:m -U efuse:w:0xFF:m

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; AY-3-8912 IC emulator version 26.0 for LGT8F328P
;
; Sources for Atmel AVRStudio 7
;
; visit our site for more information
; These source codes are distributed under the GPL v3 license
; If you share these sources you should put the link to web site www.avray.ru
;
; ORIGIN: http://www.avray.ru
; CONFIGURATION VALUES ===================================================
#define CHANNELS 2 ; choose 2 or 3 channel version
#define SPEAKER 0 ; use SPEAKER port input on PD1 (0 - no, 1 - yes)
#define VOLUME_TABLE 0 ; 0 - AY, 1 - YM, 2 - ALTERNATE volume table
#define USART_ENABLE 0 ; 0 - OFF, 1 - ON
#define INT_ENABLE 1 ; 0 - OFF, 1 - ON
#define Enable2MHz 0 ; 0 - 1,75 MHz, 1 - 2MHz
#define TS_Chip_0 0 ; 0 - OFF, 1 - On Åñëè âûêëþ÷åíû îáà TS_Chip, òî áóäåò ðàáîòàòü êàê îäèí ñòàíäàðòíûé AY
#define TS_Chip_1 0 ; 0 - OFF, 1 - On Äëÿ TS âåðñèè íåëüçÿ âûáèðàòü ñðàçó 2 ÷èïà!!!!
; ========================================================================
; bit numbers:
.equ b0 = 0x00
.equ b1 = 0x01
.equ b2 = 0x02
.equ b3 = 0x03
.equ b4 = 0x04
.equ b5 = 0x05
.equ b6 = 0x06
.equ b7 = 0x07
.equ CHIP_SELECTED = GPIOR0
; ===== ÐÀÑÏÐÅÄÅËÅÍÈÅ ÐÅÃÈÑÒÐÎÂ =====
; r0 - OutA (âûõîä êàíàëà A)
; r1 - OutC (âûõîä êàíàëà C)
; r2 - C1F (êîíñòàíòà 0x1F äëÿ èíâåðñèè êîíâåðòà)
; r3 - CntN (ñ÷åò÷èê øóìà)
; r4 - OutB (âûõîä êàíàëà B)
; r5 - BusOut1 (ìàñêà ïîðòîâ C/D äëÿ çàïèñè)
; r6 - NoiseAddon (LFSR øóìà)
; r7 - C00 (êîíñòàíòà 0x00)
; r8 - CC0 (êîíñòàíòà 0xC0)
; r9 - TabE (êîä êîíâåðòà)
; r10 - C04 (êîíñòàíòà 0x04)
; r11 - TMP (âðåìåííûé ðåãèñòð)
; r12 - EVal (çíà÷åíèå êîíâåðòà)
; r13 - SREGSave (ñîõðàíåííûé SREG)
; r14 - RNGL (LFSR øóìà LOW)
; r15 - RNGH (LFSR øóìà HIGH)
; r16 - BusData (äàííûå øèíû)
; r17 - BusOut2 (ìàñêà ïîðòîâ äëÿ ÷òåíèÿ)
; r18 - TabP (ñ÷åò÷èê ïåðèîäà êîíâåðòà)
; r19 - TNLevel (óðîâíè òîíîâ è øóìà)
; r20 - CntAL (ñ÷åò÷èê êàíàëà A LOW)
; r21 - CntAH (ñ÷åò÷èê êàíàëà A HIGH)
; r22 - CntBL (ñ÷åò÷èê êàíàëà B LOW)
; r23 - CntBH (ñ÷åò÷èê êàíàëà B HIGH)
; r24 - CntCL (ñ÷åò÷èê êàíàëà C LOW)
; r25 - CntCH (ñ÷åò÷èê êàíàëà C HIGH)
; r26 - CntEL (ñ÷åò÷èê êîíâåðòà LOW)
; r27 - CntEH (ñ÷åò÷èê êîíâåðòà HIGH)
; r30 - ADDR (àäðåñ ðåãèñòðà, èñïîëüçóåòñÿ êàê Z)
.def OutA = r0
.def OutC = r1
.def C1F = r2
.def CntN = r3
.def OutB = r4
.def BusOut1 = r5
.def NoiseAddon = r6
.def C00 = r7
.def CC0 = r8
.def TabE = r9
.def C04 = r10
.def TMP = r11
.def EVal = r12
.def SREGSave = r13
.def RNGL = r14
.def RNGH = r15
.def BusData = r16
.def BusOut2 = r17
.def TabP = r18
.def TNLevel = r19
.def CntAL = r20
.def CntAH = r21
.def CntBL = r22
.def CntBH = r23
.def CntCL = r24
.def CntCH = r25
.def CntEL = r26
.def CntEH = r27
.def ADDR = r30
; ==============================================
; LGT8F328P REGISTER DEFINITIONS
; ==============================================
; Memory-mapped I/O addresses for LGT8F328P
.equ CCP = 0x34 ; Configuration Change Protection
.equ CLKMSR = 0x105 ; Clock Main Settings Register
.equ BCR = 0x107 ; Boot Control Register
.equ BOOTEND = 0x108 ; Boot End Address
.equ BODCR = 0x104 ; BOD Control Register
; AC0 (Analog Comparator 0) Register Definition
.equ C0SR = 0x50
.equ C0D = 7
.equ C0BG = 6
.equ C0O = 5
.equ C0I = 4
.equ C0IE = 3
.equ C0IC = 2
.equ C0IS1 = 1
.equ C0IS0 = 0
.equ C0XR = 0x51
.equ C0OE = 6
.equ C0HSYE = 5
.equ C0PS0 = 4
.equ C0WKE = 3
.equ C0FEN = 2
.equ C0FS1 = 1
.equ C0FS0 = 0
.equ C0TR = 0x52
; AC1 (Analog Comparator 1) Register Definition
.equ C1SR = 0x2F
.equ C1D = 7
.equ C1BG = 6
.equ C1O = 5
.equ C1I = 4
.equ C1IE = 3
.equ C1IC = 2
.equ C1IS1 = 1
.equ C1IS0 = 0
.equ C1XR = 0x3A
.equ C1OE = 6
.equ C1HSYE = 5
.equ C1PS0 = 4
.equ C1WKE = 3
.equ C1FEN = 2
.equ C1FS1 = 1
.equ C1FS0 = 0
.equ C1TR = 0x5B
; LGT8F328P FAST GPIO REGISTERS
.equ FGPIOE = 0x10A ; Fast GPIO Enable Register
.equ FGPIO = 0x10B ; Fast GPIO Control Register
.cseg
;------------------------------------------------------
; INTERRUPT VECTORS TABLE
;------------------------------------------------------
.org 0x0000
rjmp _LGT_INIT
.org INT0addr
rjmp _INT0_Handler
.org INT1addr
rjmp _INT1_Handler
.org URXCaddr
rjmp _USART_RX_COMPLETE
;------------------------------------------------------
#if VOLUME_TABLE == 0
Volumes: ; volume table for amplitude
.db 0,1,1,1,2,2,3,5,6,9,13,17,22,29,36,45 // AY_TABLE
EVolumes: ; volume table for envelopes
.db 0,0,1,1,1,1,1,1,2,2,2,2,3,3,5,5,6,6,7,9,11,13,15,17,19,22,25,29,32,36,40,45 // AY_TABLE
#elif VOLUME_TABLE == 1
Volumes: ; volume table for amplitude
.db 0,1,1,1,2,2,3,4,5,7,10,13,18,24,34,45 // YM_TABLE
EVolumes: ; volume table for envelopes
.db 0,0,1,1,1,1,1,1,2,2,2,2,2,3,3,4,4,5,6,7,8,10,11,13,15,18,21,24,29,34,40,45 // YM_TABLE
#elif VOLUME_TABLE == 2
Volumes: ; volume table for amplitude
.db 0,1,2,3,4,5,6,7,9,11,13,16,22,31,42,58 // ALT_TABLE
EVolumes: ; volume table for envelopes
.db 0,1,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,20,22,24,26,28,30,33,36,40,45,51,58 // ALT_TABLE
#endif
; envelope codes, bit0 - attack, bit1 - invert on next cycle, bit2 - stop generator on next cycle
Envelopes:
.db 7,7,7,7,4,4,4,4,1,7,3,5,0,6,2,4
; mask applied to registers values after receiving
RegsMask:
.db 0xFF,0x0F,0xFF,0x0F,0xFF,0x0F,0x1F,0xFF,0x1F,0x1F,0x1F,0xFF,0xFF,0x0F,0xFF,0xFF
;==========================================================
_INT0_Handler: ; 4 cycles to enter
sbic PinD,b3 ; check BDIR (1)
rjmp LATCH_REG_ADDR0 ; (2) if BDIR=1
#if TS_Chip_0 > 0 || TS_Chip_1 > 0
sbic CHIP_SELECTED,0 ; (1) check chip select
rjmp exit_int0 ; (2) skip if not selected
#endif
; READ MODE - ìèíèìàëüíîå âðåìÿ
out DDRD,BusOut2 ; 1 - set data bus
out DDRC,BusOut1 ; 1
LOOP_NOT_INACTIVE:
sbic PinD,b2 ; 1 - wait for BC1=0
rjmp LOOP_NOT_INACTIVE ; 2
; Áûñòðûé ñáðîñ ïîðòîâ (4 öèêëà âìåñòî 6)
out DDRC, C00 ; 1
out DDRD, C00 ; 1
; Óáðàë âûêëþ÷åíèå ïîäòÿæåê - îíè íå êðèòè÷íû äëÿ ðàáîòû
exit_int0:
out EIFR, YH ; 1 - clear flags
reti ; 4
LATCH_REG_ADDR0:
in ADDR, PinC ; 1
andi ADDR, 0x3F ; 1
#if TS_Chip_0 > 0 || TS_Chip_1 > 0
sbic PinD,b7
rjmp SELECT_CHIP_ADDR0
#endif
ldd BusOut1, Z+0x20 ; 2
ldd BusOut2, Z+0x30 ; 2
rjmp exit_int0 ; 2
SELECT_CHIP_ADDR0:
#if TS_Chip_0 > 0
cpi ADDR, 0x3F ; 1
breq LATCH_SELECT_CHIP0 ; 1/2
cpi ADDR, 0x3E
breq RESET_LATCH0 ; 2
#elif TS_Chip_1 > 0
cpi ADDR, 0x3E ; 1
breq LATCH_SELECT_CHIP0 ; 1/2
cpi ADDR, 0x3F
breq RESET_LATCH0 ; 2
#endif
LATCH_SELECT_CHIP0:
sbi CHIP_SELECTED, b0 ; 2
rjmp exit_int0 ; 2
RESET_LATCH0:
cbi CHIP_SELECTED, b0 ; 2
rjmp exit_int0 ; 2
;==========================================================
_INT1_Handler: ; 4 cycles to enter
in BusData, PinC ; 1
andi BusData, 0x3F ; 1
sbic PinD, b2 ; 1
rjmp LATCH_REG_ADDR1 ; 2
#if TS_Chip_0 > 0 || TS_Chip_1 > 0
sbic CHIP_SELECTED, 0 ; 1
rjmp exit_int1 ; 2
#endif
; WRITE MODE - îïòèìèçèðîâàííàÿ âåðñèÿ
in BusOut1, PinD ; 1
in SREGSave, SREG ; 1
and BusOut1, CC0
or BusData, BusOut1 ; 1
mov BusOut1, BusData ; 1
com BusOut1 ; 1
; Çàãðóæàåì ìàñêó îäíîâðåìåííî ñ äðóãèìè îïåðàöèÿìè
ld BusOut2, Z ; 2 - load mask
std Z+0x20, BusOut1 ; 2 - save inverted
and BusData, BusOut2 ; 1 - apply mask
mov BusOut2, BusOut1 ; 1
andi BusOut2, 0xC0 ; 1 - extract bits 6-7
std Z+0x30, BusOut2 ; 2 - save high bits
std Z+0x10, BusData ; 2 - save value
; Ïðîâåðêà ðåãèñòðà 13 ÷åðåç ïðÿìîå ñðàâíåíèå
cpi ADDR, 0x0D ; 1
brne NO_ENVELOPE_CHANGED_P; 1/2
ori TNLevel, 0x80 ; 1
NO_ENVELOPE_CHANGED_P:
out SREG, SREGSave ; 1
rjmp exit_int1 ; 2
LATCH_REG_ADDR1:
mov ADDR, BusData ; 1
#if TS_Chip_0 > 0 || TS_Chip_1 > 0
sbic PinD,b6
rjmp SELECT_CHIP_ADDR1
#endif
ldd BusOut1, Z+0x20 ; 2
ldd BusOut2, Z+0x30 ; 2
rjmp exit_int1 ; 2
SELECT_CHIP_ADDR1:
#if TS_Chip_0 > 0
cpi ADDR, 0x3F ; 1
breq LATCH_SELECT_CHIP1 ; 1/2
cpi ADDR, 0x3E
breq RESET_LATCH1 ; 2
#elif TS_Chip_1 > 0
cpi ADDR, 0x3E ; 1
breq LATCH_SELECT_CHIP1 ; 1/2
cpi ADDR, 0x3F
breq RESET_LATCH1 ; 2
#endif
LATCH_SELECT_CHIP1:
sbi CHIP_SELECTED, b0 ; 2
exit_int1:
out EIFR, ZH ; 1
reti ;
RESET_LATCH1:
cbi CHIP_SELECTED, b0 ; 2
rjmp exit_int1 ; 2
;==========================================================
_USART_RX_COMPLETE:
lds BusData,UDR0 ; get byte from USART
sbrs ADDR,b4 ; check for address/data mode
rjmp RECV_REG_VALUE
sbrc BusData,b7
rjmp USART_SYNC
mov ADDR,BusData ; ------ receive register number ------------
reti
USART_SYNC: ; ------ synchronization mode ---------------
ldi ADDR,0x10
reti
RECV_REG_VALUE: ; ------ receive register value -------------
in SREGSave,SREG
ld BusOut1,Z ; load register mask
and BusData,BusOut1 ; apply register mask
std Z+0x10,BusData ; put register value to SRAM
cpi ADDR,0x0D ; check for envelope shape register
brne NO_ENVELOPE_CHANGED_S
ori TNLevel,0x80 ; set envelope change flag (bit 7)
NO_ENVELOPE_CHANGED_S:
ldi ADDR,0x10 ; set bit 4 to jump to receive register number on next byte received
out SREG,SREGSave
reti
; ==============================================
; LGT8F328P INITIALIZATION - NO BOOTLOADER
; ==============================================
_LGT_INIT:
; 1. Disable watchdog immediately
ldi r16, 0x00
sts WDTCSR, r16
; 2. Unlock protected registers (LGT specific)
ldi r16, 0xD8
sts CCP, r16 ; Enable configuration changes
; 3. Configure clock: 32MHz internal, divisor = 1
ldi r16, 0x80
sts CLKPR, r16 ; Enable CLKPR changes
ldi r16, 0xD8
sts CCP, r16
ldi r16, 0x00
sts CLKPR, r16 ; Divisor = 1 (32MHz)
; 4. Select internal 32MHz oscillator
ldi r16, 0xD8
sts CCP, r16
ldi r16, 0x04
sts CLKMSR, r16 ; Internal 32MHz oscillator
; 5. ENABLE FAST GPIO FOR PORTS B, C, D
ldi r16, 0xD8
sts CCP, r16
ldi r16, (1<<2) | (1<<1) | (1<<0)
sts FGPIOE, r16
ldi r16, 0xD8
sts CCP, r16
ldi r16, (0<<4) | (0<<2) | (0<<0) ; No delay for all ports
sts FGPIO, r16
; 6. Configure Fast GPIO timing (optional, default is usually OK)
ldi r16, 0xD8
sts CCP, r16
ldi r16, 0x00 ; Default timing (no delay)
sts FGPIO, r16 ; Set Fast GPIO Control register
; 7. DISABLE BOOTLOADER - BOOTRST=0, start from 0x0000
ldi r16, 0x03 ; BOOTSZ=11, BOOTRST=0
sts BCR, r16
; 8. Set BOOTEND (optional, defines flash boundary)
ldi r16, 0x7F ; 0x7F00 for 32KB flash
sts BOOTEND, r16
; 9. Continue to original reset code
rjmp _RESET
;==========================================================
_RESET: // Emulator start
in r16,MCUCR ; 1-> PUD for
sbr r16,PUD
out MCUCR,r16
// init stack pointer at end of RAM
ldi r16,low(RAMEND)
out SPL,r16
ldi r16,high(RAMEND)
out SPH,r16
; ÈÍÈÖÈÀËÈÇÀÖÈß ÏÎÐÒÎÂ C è D Â HI-Z ===================
; Ïîðò C: PC0-PC5 - äàííûå, äîëæíû áûòü â HI-Z
; Ïîðò D: PD6,PD7 - äàííûå, äîëæíû áûòü â HI-Z
ldi r16,0x00
out DDRC,r16 ; âñå ïèíû ïîðòà C êàê âõîäû
out PORTC,r16 ; îòêëþ÷èòü ïîäòÿæêè
out DDRD,r16 ; âñå ïèíû ïîðòà D êàê âõîäû
out PORTD,r16 ; îòêëþ÷èòü ïîäòÿæêè
; =====================================================
; disable Analog Comparator ==============================
ldi r16, (1<<C0D)
sts C0SR, r16
ldi r16, (1<<C1D)
out C1SR, r16
;=========================================================
// init constants
#if TS_Chip_0 > 0
sbi CHIP_SELECTED, b0
#elif TS_Chip_1 > 0
cbi CHIP_SELECTED, b0
#endif
clr C00
ldi r16,0xC0
mov CC0,r16
ldi r16,0x04
mov C04,r16
ldi r16,0x1F
mov C1F,r16
ldi r16,0xFF
mov BusOut1,r16
mov BusOut2,CC0
clr RNGH
ldi YH,0xFF
// clear register values in SRAM 0x110-0x13F
ldi r18,0x10
ldi ZL,0x10
ldi ZH,0x01
LOOP0:
std Z+0x20,CC0
std Z+0x10,r16
st Z+,C00
dec r18
brne LOOP0
; load envelope codes to SRAM 0x210, 16 bytes
ldi xh,0x02
ldi xl,0x10
ldi zl, low(2*Envelopes)
ldi zh, high(2*Envelopes)
ldi r18,0x10
rcall _COPY
; load volume table for amplitude to SRAM 0x220, 16 bytes
ldi xl,0x20
ldi zl, low(2*Volumes)
ldi zh, high(2*Volumes)
ldi r18,0x10
rcall _COPY
; load volume table for envelopes to SRAM 0x230, 32 bytes
ldi xl,0x30
ldi zl, low(2*EVolumes)
ldi zh, high(2*EVolumes)
ldi r18,0x20
rcall _COPY
; load register masks to SRAM 0x100, 16 bytes
clr xl
ldi xh,0x01
ldi zl, low(2*RegsMask)
ldi zh, high(2*RegsMask)
ldi r18,0x10
rcall _COPY
ldi ZH,0x01 ; set high byte of register Z for fast acces to register values
clr ZL
ldi YH,0x02 ; set high byte of register Y for fast acces to volume table
mov NoiseAddon,ZH ; load default value = 1 to high bit of noise generator
#if USART_ENABLE > 0
// init USART
clr r16
sts UBRR0H,r16
ldi r16,0x06
sts UCSR0C,r16
ldi r16,0x02
sts UCSR0A,r16
ldi r16,0x90
sts UCSR0B,r16
ldi r18,0x44
sts UBRR0L,r18
#endif
// init Timer1
sts OCR1AH,C00 ; clear OCR values
sts OCR1AL,C00
sts OCR1BH,C00
sts OCR1BL,C00
sbi DDRB,b1 ; set port B pin 1 to output for PWM (AY channel A)
sbi DDRB,b2 ; set port B pin 2 to output for PWM (AY channel B)
ldi r16,0xA2
sts TCCR1A,r16
ldi r16,0x19
sts TCCR1B,r16
ldi r16,0x19
sts TCCR1B,r16
#if Enable2MHz == 0
ldi r18, 0x91
#else
ldi r18, 0x7F
#endif
sts ICR1H,C00
sts ICR1L,r18 ; set PWM speed
; ICR1L value formula (32000000/109375/2 - 1) where 32000000 = 32MHz - AVR oscillator frequency
; 109375 is for 1.75 MHz version, formula is (PSG frequency / 16) e.g. for 2MHz it is 2000000/16 = 125000
#if CHANNELS == 3
// init Timer2
sbi DDRB,DDB3 ; set port B pin 3 to output for PWM (AY channel C)
ldi r16,0x83
sts TCCR2A,r16
ldi r16,0x01
sts TCCR2B,r16
#endif
#if INT_ENABLE > 0
; set INT0,INT1 ============================================
ldi r16, (1<<ISC01)|(1<<ISC00)|(1<<ISC11)|(1<<ISC10) ; rising edge
sts EICRA, r16
ldi r16, (1<<INTF0)|(1<<INTF1)
out EIFR, r16 ; clear interrupt flags
ldi r16, (1<<INT0)|(1<<INT1)
out EIMSK, r16 ; enable interrupts
; ==========================================================
#endif
// init constants and variables second part
ldi ADDR,0x10
clr TNLevel
clr OutA
clr OutB
clr OutC
mov TabP,CC0 ; set envelope generator disablet by default
clr TabE
clr BusData
clr CntN
clr CntAL
clr CntAH
movw CntBL,CntAL
movw CntCL,CntAL
movw CntEL,CntAL
clr EVal
sei ; enable global interrupts
_MAIN_LOOP:
// MAIN LOOP ========================================================================
in YL,TIFR1 ; check timer1 overflow flag TOV1
sbrs YL,TOV1
rjmp _MAIN_LOOP ; jump if not set
out TIFR1,YL ; clear timer overflow flag
// sound generation code start (using timer1 overflow flag)
// MIN cycles: 69
// MAX cycles: 110
/////////////////////////////////////////////////////////////////////////////////////
/// ENVELOPE GENERATOR
/////////////////////////////////////////////////////////////////////////////////////
sbrs TNLevel,b7
rjmp NO_ENVELOPE_CHANGED
// initialize envelope generator after change envelope shape register, only first 1/32 part of the first period!
lds YL,AY_REG13 ; load envelope shape register value to TabE
ldd TabE,Y+0x10 ; get envelope code from SRAM
ldi TabP,0x1F ; set counter for envelope period
andi TNLevel,0x7F ; clear envelope shape change flag
rjmp E_NEXT_STEP
NO_ENVELOPE_CHANGED:
sbrc TabE,b7 ; alternate: cpi TabE,0x80 ; check if envelope generator is disabled
rjmp ENVELOPE_GENERATOR_END ; alternate: brcc ENVELOPE_GENERATOR_END
sbiw CntEL,0x01
brcs E_NEXT_PERIOD ; jump to init next envelope value if counter overflow (if initial value was 0)
brne ENVELOPE_GENERATOR_END ; go to the next step if zero value is not reached
E_NEXT_PERIOD:
dec TabP
brpl E_NEXT_STEP ; jump to next step if envelope period >= 0
;init new envelope period
ldi TabP,0x1F
sbrc TabE,b1
eor TabE,ZH ; invert envelope ATTACK bit
sbrc TabE,b2
or TabE,CC0 ; disable envelope generator until new envelope shape register recived
E_NEXT_STEP:
lds CntEL,AY_REG11
lds CntEH,AY_REG12
mov YL,TabP
sbrs TabE,b0
eor YL,C1F ; invert envelope value if ATTACK bit is not set
ldd EVal,Y+0x30 ; translate envelope value to volume, read volume value from SRAM 0x230+YL
ENVELOPE_GENERATOR_END:
/////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////
/// NOISE GENERATOR
/////////////////////////////////////////////////////////////////////////////////////
dec CntN ; decrease noise period counter
brpl NOISE_GENERATOR_END ; skip if noise period is not finished (CntN>=0)
//init new cycle
lds CntN,AY_REG06 ; init noise period counter with value in AY register 6
dec CntN
lsr NoiseAddon
mov NoiseAddon,RNGL
ror RNGH
ror RNGL
ori TNLevel,0x38 ; set noise bits
sbrs RNGL,b0
andi TNLevel,0xC7 ; reset noise bits
// make input bit
lsl NoiseAddon
eor NoiseAddon,RNGL
lsr NoiseAddon
NOISE_GENERATOR_END:
/////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////
/// TONE GENERATOR
/////////////////////////////////////////////////////////////////////////////////////
; all counters are Int16 values (signed)
// Channel A -------------
subi CntAL,0x01 ; CntA - 1
sbci CntAH,0x00
brpl CH_A_NO_CHANGE ; CntA >= 0
lds CntAL,AY_REG00 ; update channel A tone period counter
lds CntAH,AY_REG01
subi CntAL,0x01 ; CntA - 1
sbci CntAH,0x00
eor TNLevel,ZH ; TNLevel xor 1 (change logical level of channel A)
CH_A_NO_CHANGE:
// Channel B -------------
subi CntBL,0x01 ; CntB - 1
sbci CntBH,0x00
brpl CH_B_NO_CHANGE ; CntB >= 0
lds CntBL,AY_REG02 ; update channel B tone period counter
lds CntBH,AY_REG03
subi CntBL,0x01 ; CntB - 1
sbci CntBH,0x00
eor TNLevel,YH ; TNLevel xor 2 (change logical level of channel B)
CH_B_NO_CHANGE:
// Channel C -------------
sbiw CntCL,0x01 ; CntC - 1
brpl CH_C_NO_CHANGE ; CntC >= 0
lds CntCL,AY_REG04 ; update channel C tone period counter
lds CntCH,AY_REG05
sbiw CntCL,0x01 ; CntC - 1
eor TNLevel,C04 ; TNLevel xor 4 (change logical level of channel C)
CH_C_NO_CHANGE:
/////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////
/// MIXER
/////////////////////////////////////////////////////////////////////////////////////
lds TMP,AY_REG07 ; Load Mixer AY Register from SRAM
or TMP,TNLevel ; Mixer formula = (Mixer Register Tone | TNLevel Tone) & (Mixer Register Noise | TNLevel Noise)
mov YL,TMP
lsl YL
swap YL
and TMP,YL
/////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////
/// AMPLITUDE CONTROL
/////////////////////////////////////////////////////////////////////////////////////
// Channel A
lds YL,AY_REG08 ; Load Channel A Amplitude register
mov OutA,EVal ; set envelope volume as default value
sbrs YL,b4 ; if bit 4 is not set in amplitude register then translate it to volume
ldd OutA,Y+0x20 ; load volume value from SRAM 0x220 + YL
sbrs TMP,b0 ; if channel is disabled in mixer - set volume to zero
clr OutA
// Channel B
lds YL,AY_REG09 ; Load Channel B Amplitude register
mov OutB,EVal ; set envelope volume as default value
sbrs YL,b4 ; if bit 4 is not set in amplitude register then translate it to volume
ldd OutB,Y+0x20 ; load volume value from SRAM 0x220 + YL
sbrs TMP,b1 ; if channel is disabled in mixer - set volume to zero
clr OutB
// Channel C
lds YL,AY_REG10 ; Load Channel C Amplitude register
mov OutC,EVal ; set envelope volume as default value
sbrs YL,b4 ; if bit 4 is not set in amplitude register then translate it to volume
ldd OutC,Y+0x20 ; load volume value from SRAM 0x220 + YL
sbrs TMP,b2 ; if channel is disabled in mixer - set volume to zero
clr OutC
// Channel B
#if CHANNELS == 2
// two channel version ----------------------------------------
mov YL,OutB
lsr OutB ; TMP = TMP - (TMP/4 + TMP/8);
lsr OutB
sub YL,OutB
lsr OutB
sub YL,OutB
add OutA,YL ; add channel B volume to channels A and C
add OutC,YL
// --------------------------------------------------------------
#elif CHANNELS == 3
// three channel version ----------------------------------------
sts OCR2A,OutB
// --------------------------------------------------------------
#endif
// --------------------------------------------------------------
#if SPEAKER == 1
// speaker port enabled -----------------------------------------
sbic PinD,b1 ; check PD1 (SPEAKER PORT INPUT) skip if bit is not set
add OutA,C1F ; add some volume to channel A
sbic PinD,b1 ; check PD1 (SPEAKER PORT INPUT) skip if bit is not set
add OutC,C1F ; add some volume to channel A
// --------------------------------------------------------------
#endif
sts OCR1AL,OutA ; update PWM counters
sts OCR1BL,OutC
rjmp _MAIN_LOOP
// MAIN LOOP END ====================================================================
// copy routine from flash to SRAM
_COPY:
lpm r16,Z+
st X+,r16
dec r18
brne _COPY
ret
/////////////////////////////////////////////////////////////////
/// AY REGISTERS IN SRAM
/////////////////////////////////////////////////////////////////
.dseg
.org 0x0110
AY_REG00:
.byte 1
AY_REG01:
.byte 1
AY_REG02:
.byte 1
AY_REG03:
.byte 1
AY_REG04:
.byte 1
AY_REG05:
.byte 1
AY_REG06:
.byte 1
AY_REG07:
.byte 1
AY_REG08:
.byte 1
AY_REG09:
.byte 1
AY_REG10:
.byte 1
AY_REG11:
.byte 1
AY_REG12:
.byte 1
AY_REG13:
.byte 1
AY_REG14:
.byte 1
AY_REG15:
.byte 1

774
Sources/AY_Emu/AY_Emu/main_TS_1Chip.asm Normal file
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@ -0,0 +1,774 @@
; AY-3-8912 IC emulator version 26.0 for LGT8F328P
;
; Sources for Atmel AVRStudio 7
;
; visit our site for more information
; These source codes are distributed under the GPL v3 license
; If you share these sources you should put the link to web site www.avray.ru
;
; ORIGIN: http://www.avray.ru
; CONFIGURATION VALUES ===================================================
#define CHANNELS 2 ; choose 2 or 3 channel version
#define VOLUME_TABLE 0 ; 0 - AY, 1 - YM, 2 - ALTERNATE volume table
; ========================================================================
; bit numbers:
.equ b0 = 0x00
.equ b1 = 0x01
.equ b2 = 0x02
.equ b3 = 0x03
.equ b4 = 0x04
.equ b5 = 0x05
.equ b6 = 0x06
.equ b7 = 0x07
.equ CHIP_SELECTED = GPIOR0
.def OutA = r0
.def OutC = r1
.def C1F = r2
.def CntN = r3
.def OutB = r4
.def BusOut1 = r5
.def NoiseAddon = r6
.def C00 = r7
.def CC0 = r8
.def TabE = r9
.def C04 = r10
.def TMP = r11
.def EVal = r12
.def SREGSave = r13
.def RNGL = r14
.def RNGH = r15
.def BusData = r16
.def BusOut2 = r17
.def TabP = r18
.def TNLevel = r19
.def CntAL = r20
.def CntAH = r21
.def CntBL = r22
.def CntBH = r23
.def CntCL = r24
.def CntCH = r25
.def CntEL = r26
.def CntEH = r27
.def ADDR = r30
; ==============================================
; LGT8F328P REGISTER DEFINITIONS
; ==============================================
; Memory-mapped I/O addresses for LGT8F328P
.equ CCP = 0x34 ; Configuration Change Protection
.equ CLKMSR = 0x105 ; Clock Main Settings Register
.equ BCR = 0x107 ; Boot Control Register
.equ BOOTEND = 0x108 ; Boot End Address
.equ BODCR = 0x104 ; BOD Control Register
; AC0 (Analog Comparator 0) Register Definition
.equ C0SR = 0x50
.equ C0D = 7
.equ C0BG = 6
.equ C0O = 5
.equ C0I = 4
.equ C0IE = 3
.equ C0IC = 2
.equ C0IS1 = 1
.equ C0IS0 = 0
.equ C0XR = 0x51
.equ C0OE = 6
.equ C0HSYE = 5
.equ C0PS0 = 4
.equ C0WKE = 3
.equ C0FEN = 2
.equ C0FS1 = 1
.equ C0FS0 = 0
.equ C0TR = 0x52
; AC1 (Analog Comparator 1) Register Definition
.equ C1SR = 0x2F
.equ C1D = 7
.equ C1BG = 6
.equ C1O = 5
.equ C1I = 4
.equ C1IE = 3
.equ C1IC = 2
.equ C1IS1 = 1
.equ C1IS0 = 0
.equ C1XR = 0x3A
.equ C1OE = 6
.equ C1HSYE = 5
.equ C1PS0 = 4
.equ C1WKE = 3
.equ C1FEN = 2
.equ C1FS1 = 1
.equ C1FS0 = 0
.equ C1TR = 0x5B
; LGT8F328P FAST GPIO REGISTERS
.equ FGPIOE = 0x10A ; Fast GPIO Enable Register
.equ FGPIO = 0x10B ; Fast GPIO Control Register
.cseg
;------------------------------------------------------
; INTERRUPT VECTORS TABLE
;------------------------------------------------------
.org 0x0000
rjmp _LGT_INIT
.org INT0addr
rjmp _INT0_Handler
.org INT1addr
rjmp _INT1_Handler
;------------------------------------------------------
#if VOLUME_TABLE == 0
Volumes: ; volume table for amplitude
.db 0,1,1,1,2,2,3,5,6,9,13,17,22,29,36,45 // AY_TABLE
EVolumes: ; volume table for envelopes
.db 0,0,1,1,1,1,1,1,2,2,2,2,3,3,5,5,6,6,7,9,11,13,15,17,19,22,25,29,32,36,40,45 // AY_TABLE
#elif VOLUME_TABLE == 1
Volumes: ; volume table for amplitude
.db 0,1,1,1,2,2,3,4,5,7,10,13,18,24,34,45 // YM_TABLE
EVolumes: ; volume table for envelopes
.db 0,0,1,1,1,1,1,1,2,2,2,2,2,3,3,4,4,5,6,7,8,10,11,13,15,18,21,24,29,34,40,45 // YM_TABLE
#elif VOLUME_TABLE == 2
Volumes: ; volume table for amplitude
.db 0,1,2,3,4,5,6,7,9,11,13,16,22,31,42,58 // ALT_TABLE
EVolumes: ; volume table for envelopes
.db 0,1,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,20,22,24,26,28,30,33,36,40,45,51,58 // ALT_TABLE
#endif
; envelope codes, bit0 - attack, bit1 - invert on next cycle, bit2 - stop generator on next cycle
Envelopes:
.db 7,7,7,7,4,4,4,4,1,7,3,5,0,6,2,4
; mask applied to registers values after receiving
RegsMask:
.db 0xFF,0x0F,0xFF,0x0F,0xFF,0x0F,0x1F,0xFF,0x1F,0x1F,0x1F,0xFF,0xFF,0x0F,0xFF,0xFF
;==========================================================
_INT0_Handler: ; 4 cycles to enter
sbic PinD,b3 ; check BDIR (1)
rjmp LATCH_REG_ADDR0 ; (2) if BDIR=1
out DDRD,BusOut2 ; 1 - set data bus
out DDRC,BusOut1 ; 1
LOOP_NOT_INACTIVE:
sbic PinD,b2 ; 1 - wait for BC1=0
rjmp LOOP_NOT_INACTIVE ; 2
out DDRC, C00 ; 1
out DDRD, C00 ; 1
exit_int0:
out EIFR, YH ; 1 - clear flags
reti ; 4
LATCH_REG_ADDR0:
in ADDR, PinC ; 1
andi ADDR, 0x3F ; 1
sbic PinD,b7
rjmp SELECT_CHIP_ADDR0
sbic CHIP_SELECTED,b0
rjmp READ_CHIP0
; ×èï 0
ldi ZH,0x01
ldd BusOut1, Z+0x20
ldd BusOut2, Z+0x30
rjmp exit_int0
READ_CHIP0:
; ×èï 1
ldi ZH,0x08
ldd BusOut1, Z+0x20
ldd BusOut2, Z+0x30
rjmp exit_int0
SELECT_CHIP_ADDR0:
cpi ADDR, 0x3F ; 1
breq SELECT_CHIP0_ADDR0 ; 1/2
cpi ADDR, 0x3E
breq SELECT_CHIP1_ADDR0 ; 2
rjmp exit_int0
SELECT_CHIP0_ADDR0:
cbi CHIP_SELECTED, b0
rjmp exit_int0
SELECT_CHIP1_ADDR0:
sbi CHIP_SELECTED, b0
rjmp exit_int0
;==========================================================
_INT1_Handler: ; 4 cycles to enter
in BusData, PinC ; 1
andi BusData, 0x3F ; 1
sbic PinD, b2 ; 1
rjmp LATCH_REG_ADDR1 ; 2
in BusOut1, PinD ; 1
in SREGSave, SREG ; 1
and BusOut1, CC0
or BusData, BusOut1 ; 1
mov BusOut1, BusData ; 1
com BusOut1 ; 1
sbic CHIP_SELECTED, b0
rjmp WRITE_TO_CHIP1
; Óñòàíàâëèâàåì Z íà AY0
ldi ZH, 0x01
rjmp WRITE_COMMON
WRITE_TO_CHIP1:
; Óñòàíàâëèâàåì Z íà AY1
ldi ZH, 0x08
WRITE_COMMON:
ld BusOut2, Z ; 2 - load mask
std Z+0x20, BusOut1 ; 2 - save inverted
and BusData, BusOut2 ; 1 - apply mask
mov BusOut2, BusOut1 ; 1
andi BusOut2, 0xC0 ; 1 - extract bits 6-7
std Z+0x30, BusOut2 ; 2 - save high bits
std Z+0x10, BusData ; 2 - save value
; Ïðîâåðêà ðåãèñòðà 13 ÷åðåç ïðÿìîå ñðàâíåíèå
cpi ADDR, 0x0D ; 1
brne NO_ENVELOPE_CHANGED_P; 1/2
ori TNLevel, 0x80 ; 1
NO_ENVELOPE_CHANGED_P:
out SREG, SREGSave ; 1
exit_int1:
ldi ZH, 0x01
out EIFR, ZH ; 1
reti
LATCH_REG_ADDR1:
mov ADDR, BusData ; 1
sbic PinD,b6
rjmp SELECT_CHIP_ADDR1
sbic CHIP_SELECTED,b0
rjmp READ_CHIP1
; ×èï 0
ldi ZH,0x01
ldd BusOut1, Z+0x20 ; 2
ldd BusOut2, Z+0x30 ; 2
rjmp exit_int1
READ_CHIP1:
; ×èï 1
ldi ZH,0x08
ldd BusOut1, Z+0x20
ldd BusOut2, Z+0x30
rjmp exit_int1 ; 2
SELECT_CHIP_ADDR1:
cpi ADDR, 0x3F ; 1
breq SELECT_CHIP0_ADDR1 ; 1/2
cpi ADDR, 0x3E
breq SELECT_CHIP1_ADDR1 ; 2
rjmp exit_int1
SELECT_CHIP0_ADDR1:
cbi CHIP_SELECTED, b0
rjmp exit_int1
SELECT_CHIP1_ADDR1:
sbi CHIP_SELECTED, b0
rjmp exit_int1
; ==============================================
; LGT8F328P INITIALIZATION - NO BOOTLOADER
; ==============================================
_LGT_INIT:
; 1. Disable watchdog immediately
ldi r16, 0x00
sts WDTCSR, r16
; 2. Unlock protected registers (LGT specific)
ldi r16, 0xD8
sts CCP, r16 ; Enable configuration changes
; 3. Configure clock: 32MHz internal, divisor = 1
ldi r16, 0x80
sts CLKPR, r16 ; Enable CLKPR changes
ldi r16, 0xD8
sts CCP, r16
ldi r16, 0x00
sts CLKPR, r16 ; Divisor = 1 (32MHz)
; 4. Select internal 32MHz oscillator
ldi r16, 0xD8
sts CCP, r16
ldi r16, 0x04
sts CLKMSR, r16 ; Internal 32MHz oscillator
; 5. ENABLE FAST GPIO FOR PORTS B, C, D
ldi r16, 0xD8
sts CCP, r16
ldi r16, (1<<2) | (1<<1) | (1<<0)
sts FGPIOE, r16
ldi r16, 0xD8
sts CCP, r16
ldi r16, (0<<4) | (0<<2) | (0<<0) ; No delay for all ports
sts FGPIO, r16
; 6. Configure Fast GPIO timing (optional, default is usually OK)
ldi r16, 0xD8
sts CCP, r16
ldi r16, 0x00 ; Default timing (no delay)
sts FGPIO, r16 ; Set Fast GPIO Control register
; 7. DISABLE BOOTLOADER - BOOTRST=0, start from 0x0000
ldi r16, 0x03 ; BOOTSZ=11, BOOTRST=0
sts BCR, r16
; 8. Set BOOTEND (optional, defines flash boundary)
ldi r16, 0x7F ; 0x7F00 for 32KB flash
sts BOOTEND, r16
; 9. Continue to original reset code
rjmp _RESET
;==========================================================
_RESET: // Emulator start
in r16,MCUCR ; 1-> PUD for
sbr r16,PUD
out MCUCR,r16
// init stack pointer at end of RAM
ldi r16,low(RAMEND)
out SPL,r16
ldi r16,high(RAMEND)
out SPH,r16
; ÈÍÈÖÈÀËÈÇÀÖÈß ÏÎÐÒÎÂ C è D Â HI-Z ===================
; Ïîðò C: PC0-PC5 - äàííûå, äîëæíû áûòü â HI-Z
; Ïîðò D: PD6,PD7 - äàííûå, äîëæíû áûòü â HI-Z
ldi r16,0x00
out DDRC,r16 ; âñå ïèíû ïîðòà C êàê âõîäû
out PORTC,r16 ; îòêëþ÷èòü ïîäòÿæêè
out DDRD,r16 ; âñå ïèíû ïîðòà D êàê âõîäû
out PORTD,r16 ; îòêëþ÷èòü ïîäòÿæêè
; =====================================================
; disable Analog Comparator ==============================
ldi r16, (1<<C0D)
sts C0SR, r16
ldi r16, (1<<C1D)
out C1SR, r16
;=========================================================
// init constants
cbi CHIP_SELECTED, b0 ; Ñíà÷àëà âñåãäà âûáðàí AY 0
cbi CHIP_SELECTED, b1
clr C00
ldi r16,0xC0
mov CC0,r16
ldi r16,0x04
mov C04,r16
ldi r16,0x1F
mov C1F,r16
ldi r16,0xFF
mov BusOut1,r16
mov BusOut2,CC0
clr RNGH
ldi YH,0xFF
// clear register values in SRAM 0x110-0x13F
ldi r18,0x10
ldi ZL,0x10
ldi ZH,0x01
LOOP0:
std Z+0x20,CC0
std Z+0x10,r16
st Z+,C00
dec r18
brne LOOP0
; load envelope codes to SRAM 0x210, 16 bytes
ldi xh,0x02
ldi xl,0x10
ldi zl, low(2*Envelopes)
ldi zh, high(2*Envelopes)
ldi r18,0x10
rcall _COPY
; load volume table for amplitude to SRAM 0x220, 16 bytes
ldi xl,0x20
ldi zl, low(2*Volumes)
ldi zh, high(2*Volumes)
ldi r18,0x10
rcall _COPY
; load volume table for envelopes to SRAM 0x230, 32 bytes
ldi xl,0x30
ldi zl, low(2*EVolumes)
ldi zh, high(2*EVolumes)
ldi r18,0x20
rcall _COPY
; load register masks to SRAM 0x100, 16 bytes
clr xl
ldi xh,0x01
ldi zl, low(2*RegsMask)
ldi zh, high(2*RegsMask)
ldi r18,0x10
rcall _COPY
// clear register values in SRAM 0x300-0x310
ldi r18,0x10
ldi ZL,0x00
ldi ZH,0x08
LOOP1:
std Z+0x20,CC0
std Z+0x10,r16
st Z+,C00
dec r18
brne LOOP1
ldi ZH,0x01 ; set high byte of register Z for fast acces to register values
clr ZL
ldi YH,0x02 ; set high byte of register Y for fast acces to volume table
mov NoiseAddon,ZH ; load default value = 1 to high bit of noise generator
// init Timer1
sts OCR1AH,C00 ; clear OCR values
sts OCR1AL,C00
sts OCR1BH,C00
sts OCR1BL,C00
sbi DDRB,b1 ; set port B pin 1 to output for PWM (AY channel A)
sbi DDRB,b2 ; set port B pin 2 to output for PWM (AY channel B)
ldi r16,0xA2
sts TCCR1A,r16
ldi r16,0x19
sts TCCR1B,r16
ldi r16,0x19
sts TCCR1B,r16
ldi r18, 0x50
sts ICR1H,C00
sts ICR1L,r18 ; set PWM speed
; ICR1L value formula (32000000/109375/2 - 1) where 32000000 = 32MHz - AVR oscillator frequency
; 109375 is for 1.75 MHz version, formula is (PSG frequency / 16) e.g. for 2MHz it is 2000000/16 = 125000
; Íî òàê êàê ó íàñ îáðàáîòêà äâóõ AY èäåò â ÷åòíîì è íå÷åòíîì òèêå, òî ÷àñòîòà òàéìåðà äîëæíà áûòü óâåëè÷èíà.
#if CHANNELS == 3
// init Timer2
sbi DDRB,DDB3 ; set port B pin 3 to output for PWM (AY channel C)
ldi r16,0x83
sts TCCR2A,r16
ldi r16,0x01
sts TCCR2B,r16
#endif
; set INT0,INT1 ============================================
ldi r16, (1<<ISC01)|(1<<ISC00)|(1<<ISC11)|(1<<ISC10) ; rising edge
sts EICRA, r16
ldi r16, (1<<INTF0)|(1<<INTF1)
out EIFR, r16 ; clear interrupt flags
ldi r16, (1<<INT0)|(1<<INT1)
out EIMSK, r16 ; enable interrupts
; ==========================================================
// init constants and variables second part
ldi ADDR,0x10
clr TNLevel
clr OutA
clr OutB
clr OutC
mov TabP,CC0 ; set envelope generator disablet by default
clr TabE
clr BusData
clr CntN
clr CntAL
clr CntAH
movw CntBL,CntAL
movw CntCL,CntAL
movw CntEL,CntAL
clr EVal
sei ; enable global interrupts
_MAIN_LOOP:
// MAIN LOOP ========================================================================
in YL,TIFR1 ; check timer1 overflow flag TOV1
sbrs YL,TOV1
rjmp _MAIN_LOOP ; jump if not set
out TIFR1,YL ; clear timer overflow flag
sbic CHIP_SELECTED, b1
rjmp PROCESS_CHIP1_TICK
sbi CHIP_SELECTED, b1
// sound generation code start (using timer1 overflow flag)
// MIN cycles: 69
// MAX cycles: 110
/////////////////////////////////////////////////////////////////////////////////////
/// ENVELOPE GENERATOR
/////////////////////////////////////////////////////////////////////////////////////
sbrs TNLevel,b7
rjmp NO_ENVELOPE_CHANGED
// initialize envelope generator after change envelope shape register, only first 1/32 part of the first period!
lds YL,AY_REG13 ; load envelope shape register value to TabE
ldd TabE,Y+0x10 ; get envelope code from SRAM
ldi TabP,0x1F ; set counter for envelope period
andi TNLevel,0x7F ; clear envelope shape change flag
rjmp E_NEXT_STEP
NO_ENVELOPE_CHANGED:
sbrc TabE,b7 ; alternate: cpi TabE,0x80 ; check if envelope generator is disabled
rjmp ENVELOPE_GENERATOR_END ; alternate: brcc ENVELOPE_GENERATOR_END
sbiw CntEL,0x01
brcs E_NEXT_PERIOD ; jump to init next envelope value if counter overflow (if initial value was 0)
brne ENVELOPE_GENERATOR_END ; go to the next step if zero value is not reached
E_NEXT_PERIOD:
dec TabP
brpl E_NEXT_STEP ; jump to next step if envelope period >= 0
;init new envelope period
ldi TabP,0x1F
sbrc TabE,b1
eor TabE,ZH ; invert envelope ATTACK bit
sbrc TabE,b2
or TabE,CC0 ; disable envelope generator until new envelope shape register recived
E_NEXT_STEP:
lds CntEL,AY_REG11
lds CntEH,AY_REG12
mov YL,TabP
sbrs TabE,b0
eor YL,C1F ; invert envelope value if ATTACK bit is not set
ldd EVal,Y+0x30 ; translate envelope value to volume, read volume value from SRAM 0x230+YL
ENVELOPE_GENERATOR_END:
/////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////
/// NOISE GENERATOR
/////////////////////////////////////////////////////////////////////////////////////
dec CntN ; decrease noise period counter
brpl NOISE_GENERATOR_END ; skip if noise period is not finished (CntN>=0)
//init new cycle
lds CntN,AY_REG06 ; init noise period counter with value in AY register 6
dec CntN
lsr NoiseAddon
mov NoiseAddon,RNGL
ror RNGH
ror RNGL
ori TNLevel,0x38 ; set noise bits
sbrs RNGL,b0
andi TNLevel,0xC7 ; reset noise bits
// make input bit
lsl NoiseAddon
eor NoiseAddon,RNGL
lsr NoiseAddon
NOISE_GENERATOR_END:
/////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////
/// TONE GENERATOR
/////////////////////////////////////////////////////////////////////////////////////
; all counters are Int16 values (signed)
// Channel A -------------
subi CntAL,0x01 ; CntA - 1
sbci CntAH,0x00
brpl CH_A_NO_CHANGE ; CntA >= 0
lds CntAL,AY_REG00 ; update channel A tone period counter
lds CntAH,AY_REG01
subi CntAL,0x01 ; CntA - 1
sbci CntAH,0x00
eor TNLevel,ZH ; TNLevel xor 1 (change logical level of channel A)
CH_A_NO_CHANGE:
// Channel B -------------
subi CntBL,0x01 ; CntB - 1
sbci CntBH,0x00
brpl CH_B_NO_CHANGE ; CntB >= 0
lds CntBL,AY_REG02 ; update channel B tone period counter
lds CntBH,AY_REG03
subi CntBL,0x01 ; CntB - 1
sbci CntBH,0x00
eor TNLevel,YH ; TNLevel xor 2 (change logical level of channel B)
CH_B_NO_CHANGE:
// Channel C -------------
sbiw CntCL,0x01 ; CntC - 1
brpl CH_C_NO_CHANGE ; CntC >= 0
lds CntCL,AY_REG04 ; update channel C tone period counter
lds CntCH,AY_REG05
sbiw CntCL,0x01 ; CntC - 1
eor TNLevel,C04 ; TNLevel xor 4 (change logical level of channel C)
CH_C_NO_CHANGE:
/////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////
/// MIXER
/////////////////////////////////////////////////////////////////////////////////////
lds TMP,AY_REG07 ; Load Mixer AY Register from SRAM
or TMP,TNLevel ; Mixer formula = (Mixer Register Tone | TNLevel Tone) & (Mixer Register Noise | TNLevel Noise)
mov YL,TMP
lsl YL
swap YL
and TMP,YL
/////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////
/// AMPLITUDE CONTROL
/////////////////////////////////////////////////////////////////////////////////////
// Channel A
lds YL,AY_REG08 ; Load Channel A Amplitude register
mov OutA,EVal ; set envelope volume as default value
sbrs YL,b4 ; if bit 4 is not set in amplitude register then translate it to volume
ldd OutA,Y+0x20 ; load volume value from SRAM 0x220 + YL
sbrs TMP,b0 ; if channel is disabled in mixer - set volume to zero
clr OutA
// Channel B
lds YL,AY_REG09 ; Load Channel B Amplitude register
mov OutB,EVal ; set envelope volume as default value
sbrs YL,b4 ; if bit 4 is not set in amplitude register then translate it to volume
ldd OutB,Y+0x20 ; load volume value from SRAM 0x220 + YL
sbrs TMP,b1 ; if channel is disabled in mixer - set volume to zero
clr OutB
// Channel C
lds YL,AY_REG10 ; Load Channel C Amplitude register
mov OutC,EVal ; set envelope volume as default value
sbrs YL,b4 ; if bit 4 is not set in amplitude register then translate it to volume
ldd OutC,Y+0x20 ; load volume value from SRAM 0x220 + YL
sbrs TMP,b2 ; if channel is disabled in mixer - set volume to zero
clr OutC
rjmp ENDING_MAIN_LOOP
PROCESS_CHIP1_TICK:
cbi CHIP_SELECTED, b1
ENDING_MAIN_LOOP:
// Channel B
#if CHANNELS == 2
// two channel version ----------------------------------------
mov YL,OutB
lsr OutB ; TMP = TMP - (TMP/4 + TMP/8);
lsr OutB
sub YL,OutB
lsr OutB
sub YL,OutB
add OutA,YL ; add channel B volume to channels A and C
add OutC,YL
// --------------------------------------------------------------
#elif CHANNELS == 3
// three channel version ----------------------------------------
sts OCR2A,OutB
// --------------------------------------------------------------
#endif
// --------------------------------------------------------------
sts OCR1AL,OutA ; update PWM counters
sts OCR1BL,OutC
rjmp _MAIN_LOOP
// MAIN LOOP END ====================================================================
// copy routine from flash to SRAM
_COPY:
lpm r16,Z+
st X+,r16
dec r18
brne _COPY
ret
/////////////////////////////////////////////////////////////////
/// AY REGISTERS IN SRAM
/////////////////////////////////////////////////////////////////
.dseg
.org 0x0110
;Ðåãèñòðû äëÿ ïåðâîãî AY ÷èïà
AY_REG00:
.byte 1
AY_REG01:
.byte 1
AY_REG02:
.byte 1
AY_REG03:
.byte 1
AY_REG04:
.byte 1
AY_REG05:
.byte 1
AY_REG06:
.byte 1
AY_REG07:
.byte 1
AY_REG08:
.byte 1
AY_REG09:
.byte 1
AY_REG10:
.byte 1
AY_REG11:
.byte 1
AY_REG12:
.byte 1
AY_REG13:
.byte 1
AY_REG14:
.byte 1
AY_REG15:
.byte 1
;Ðåãèñòðû äëÿ âòîðîãî AY ÷èïà
.org 0x0810
AY1_REG00:
.byte 1
AY1_REG01:
.byte 1
AY1_REG02:
.byte 1
AY1_REG03:
.byte 1
AY1_REG04:
.byte 1
AY1_REG05:
.byte 1
AY1_REG06:
.byte 1
AY1_REG07:
.byte 1
AY1_REG08:
.byte 1
AY1_REG09:
.byte 1
AY1_REG10:
.byte 1
AY1_REG11:
.byte 1
AY1_REG12:
.byte 1
AY1_REG13:
.byte 1
AY1_REG14:
.byte 1
AY1_REG15:
.byte 1

1098
Sources/AY_Emu/AY_Emu/main_v1.asm Normal file
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