
AVRASM ver. 2.1.51  D:\workspace\avr\vg93_lgt\vg93_lgt\vg93_lgt.asm Fri Nov 14 09:42:20 2025

D:\workspace\avr\vg93_lgt\vg93_lgt\vg93_lgt.asm(9): Including file 'D:\workspace\avr\vg93_lgt\vg93_lgt\lgt8f328pdef.inc'
D:\workspace\avr\vg93_lgt\vg93_lgt\vg93_lgt.asm(13): Including file 'D:\workspace\avr\vg93_lgt\vg93_lgt\macro.inc'
D:\workspace\avr\vg93_lgt\vg93_lgt\vg93_lgt.asm(14): Including file 'D:\workspace\avr\vg93_lgt\vg93_lgt\hardware.inc'
D:\workspace\avr\vg93_lgt\vg93_lgt\vg93_lgt.asm(280): Including file 'D:\workspace\avr\vg93_lgt\vg93_lgt\cmd_int.inc'
D:\workspace\avr\vg93_lgt\vg93_lgt\vg93_lgt.asm(361): Including file 'D:\workspace\avr\vg93_lgt\vg93_lgt\CRC.inc'
                 
                 
                  * vg93_lgt.asm
                  *
                  *  Created: 31.05.2023 9:13:34
                  *   Author: ugryumov_ep
                  */ 
                 
                 
                  .include "lgt8f328pdef.inc"
                 
                 ;***** Created: 2023-25-01 ******* Source: m328P.inc, LGT8FX8P_databook_v1.0.4.en.pdf **********
                 ;*************************************************************************
                 ;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
                 ;* 
                 ;* File Name         : "lgt8f328Pdef.inc"
                 ;* Title             : Register/Bit Definitions for the LGT8F328P 
                 ;* Date              : 2023-25-01
                 ;* Author	     : Revich Yury
                 ;* Support E-mail    : revich@lib.ru
                 ;* Target MCU        : LGT8F328P
                 ;* 
                 ;* DESCRIPTION
                 ;* When including this file in the assembly program file, all I/O register 
                 ;* names and I/O register bit names appearing in the data book can be used.
                 ;* In addition, the six registers forming the three data pointers X, Y and 
                 ;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
                 ;* SRAM is also defined 
                 ;* 
                 ;* The Register names are represented by their hexadecimal address.
                 ;* 
                 ;* The Register Bit names are represented by their bit number (0-7).
                 ;* 
                 ;* Please observe the difference in using the bit names with instructions
                 ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
                 ;* (skip if bit in register set/cleared). The following example illustrates
                 ;* this:
                 ;* 
                 ;* in    r16,PORTB             ;read PORTB latch
                 ;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
                 ;* out   PORTB,r16             ;output to PORTB
                 ;* 
                 ;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
                 ;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
                 ;* rjmp  TOV0_is_set           ;jump if set
                 ;* ...                         ;otherwise do something else
                 ;*************************************************************************
                 
                 #ifndef _LGT8F328PDEF_INC_
                 #define _LGT8F328PDEF_INC_
                 
                 
                 #pragma partinc 0
                 
                 ; ***** SPECIFY DEVICE ***************************************************
                 .device LGT8F328P
                 #pragma AVRPART ADMIN PART_NAME LGT8F328P ;same as m328p?
                 .equ	SIGNATURE_000	= 0x1e
                 .equ	SIGNATURE_001	= 0x95
                 .equ	SIGNATURE_002	= 0x0f
                 
                 #pragma AVRPART CORE CORE_VERSION V2E
                 
                 
                 ; ***** I/O REGISTER DEFINITIONS *****************************************
                 ; NOTE:
                 ; Definitions marked "MEMORY MAPPED" are extended I/O ports
                 ; and cannot be used with IN/OUT instructions.
                 ; Write and read to/from "MEMORY MAPPED" registers only with
                 ; instructions ST/STS è LD/LDS. Therefore addresses of this 
                 ; registers is absolute addresses in data memory.
                 
                 ;GUID3-0 is unique 4-byte serial number for each chip LGT8F328P  
                 .equ GUID3 = 0xf6 ; MEMORY MAPPED read only
                 .equ GUID2 = 0xf5 ; MEMORY MAPPED read only
                 .equ GUID1 = 0xf4 ; MEMORY MAPPED read only
                 .equ GUID0 = 0xf3 ; MEMORY MAPPED read only
                 
                 .equ PMCR   = 0xF2 ; MEMORY MAPPED 
                 .equ PMX2   = 0xF0 ; MEMORY MAPPED 
                 .equ PMX0   = 0xEE ; MEMORY MAPPED 
                 .equ PMX1   = 0xED ; MEMORY MAPPED 
                 .equ TCKCSR = 0xEC ; MEMORY MAPPED 
                 .equ PSSR   = 0xE2 ; MEMORY MAPPED 
                 .equ OCPUE  = 0xE1 ; MEMORY MAPPED 
                 .equ HDR    = 0xE0 ; MEMORY MAPPED 
                 .equ DAPTE  = 0xDE ; MEMORY MAPPED 
                 .equ DAPTR  = 0xDD ; MEMORY MAPPED 
                 .equ DAPCR  = 0xDC ; MEMORY MAPPED 
                 .equ LDOCR  = 0xCF ; MEMORY MAPPED 
                 .equ VCAL2  = 0xCE ; MEMORY MAPPED Calibration value for 2.048V internal reference 
                 .equ VCAL1  = 0xCD ; MEMORY MAPPED Calibration value for 1.024V internal reference 
                 .equ VCAL3  = 0xCC ; MEMORY MAPPED Calibration value for 4.096V internal reference 
                 .equ VCAL   = 0xC8 ; MEMORY MAPPED Internal Voltage Reference calibration register 
                 
                 .equ	UDR	= 0xc6	; MEMORY MAPPED
                 .equ	UBRRL	= 0xc4	; MEMORY MAPPED
                 .equ	UBRRH	= 0xc5	; MEMORY MAPPED
                 .equ	UCSRC	= 0xc2	; MEMORY MAPPED
                 .equ	UCSRB	= 0xc1	; MEMORY MAPPED
                 .equ	UCSRA	= 0xc0	; MEMORY MAPPED
                 .equ	TWAMR	= 0xbd	; MEMORY MAPPED
                 .equ	TWCR	= 0xbc	; MEMORY MAPPED
                 .equ	TWDR	= 0xbb	; MEMORY MAPPED
                 .equ	TWAR	= 0xba	; MEMORY MAPPED
                 .equ	TWSR	= 0xb9	; MEMORY MAPPED
                 .equ	TWBR	= 0xb8	; MEMORY MAPPED
                 .equ	ASSR	= 0xb6	; MEMORY MAPPED
                 .equ	OCR2B	= 0xb4	; MEMORY MAPPED
                 .equ	OCR2A	= 0xb3	; MEMORY MAPPED
                 .equ	TCNT2	= 0xb2	; MEMORY MAPPED
                 .equ	TCCR2B	= 0xb1	; MEMORY MAPPED
                 .equ	TCCR2A	= 0xb0	; MEMORY MAPPED
                 
                 .equ DPS2R  = 0xAF ; MEMORY MAPPED
                 .equ IOCWK  = 0xAE ; MEMORY MAPPED
                 .equ ADCSRD = 0xAD ; MEMORY MAPPED
                 .equ ADMSC  = 0xAC ; MEMORY MAPPED 
                 .equ ADT1H  = 0xAB ; MEMORY MAPPED ADC Auto-monitor Overflow threshold high byte
                 .equ ADT1L  = 0xAA ; MEMORY MAPPED ADC Auto-monitor Overflow threshold low byte
                 ;.equ PORTE  = 0xA9 ; MEMORY MAPPED Port Output E (for compatible with LGT8FX8D)
                 ;.equ DDRE   = 0xA8 ; MEMORY MAPPED Data Direction E (for compatible with LGT8FX8D)
                 ;.equ PINE   = 0xA7 ; MEMORY MAPPED Port Input E (for compatible with LGT8FX8D)
                 .equ ADT0H  = 0xA6 ; MEMORY MAPPED ADC Auto-monitor Underflow threshold high byte
                 .equ ADT0L  = 0xA5 ; MEMORY MAPPED ADC Auto-monitor Underflow threshold low byte
                 .equ OFR1   = 0xA4 ; MEMORY MAPPED ADC positive offset trimming
                 .equ OFR0   = 0xA3 ; MEMORY MAPPED ADC negative offset trimming
                 .equ DALR   = 0xA1 ; MEMORY MAPPED DAC data register
                 .equ DACON  = 0xA0 ; MEMORY MAPPED
                 .equ OCR3CH = 0x9F ; MEMORY MAPPED Compare output register high byte of Timer3 C channel
                 .equ OCR3CL = 0x9E ; MEMORY MAPPED Compare output register low byte of Timer3 C channel
                 .equ DTR3H  = 0x9D ; MEMORY MAPPED Dead-band register high byte of Timer3
                 .equ DTR3L  = 0x9C ; MEMORY MAPPED Dead-band register low byte of Timer3
                 .equ OCR3BH = 0x9B ; MEMORY MAPPED Compare output register high byte of Timer3 B channel
                 .equ OCR3BL = 0x9A ; MEMORY MAPPED Compare output register low byte of Timer3 B channel
                 .equ OCR3AH = 0x99 ; MEMORY MAPPED Compare output register high byte of Timer3 A channel
                 .equ OCR3AL = 0x98 ; MEMORY MAPPED Compare output register low byte of Timer3 A channel
                 .equ ICR3H  = 0x97 ; MEMORY MAPPED Input capture register high byte of Timer3
                 .equ ICR3L  = 0x96 ; MEMORY MAPPED Input capture register low byte of Timer3
                 .equ TCNT3H = 0x95 ; MEMORY MAPPED Counter register high byte of Timer3
                 .equ TCNT3L = 0x94 ; MEMORY MAPPED Counter register low byte of Timer3
                 .equ TCCR3D = 0x93 ; MEMORY MAPPED Control register D of Timer3
                 .equ TCCR3C = 0x92 ; MEMORY MAPPED Control register C of Timer3
                 .equ TCCR3B = 0x91 ; MEMORY MAPPED Control register B of Timer3
                 .equ TCCR3A = 0x90 ; MEMORY MAPPED Control register A of Timer3
                 .equ DTR1H  = 0x8D ; MEMORY MAPPED Dead-band register high byte of Timer1
                 .equ DTR1L  = 0x8C ; MEMORY MAPPED Dead-band register low byte of Timer1
                 
                 .equ	OCR1BH	= 0x8b	; MEMORY MAPPED
                 .equ	OCR1BL	= 0x8a	; MEMORY MAPPED
                 .equ	OCR1AH	= 0x89	; MEMORY MAPPED
                 .equ	OCR1AL	= 0x88	; MEMORY MAPPED
                 .equ	ICR1H	= 0x87	; MEMORY MAPPED
                 .equ	ICR1L	= 0x86	; MEMORY MAPPED
                 .equ	TCNT1H	= 0x85	; MEMORY MAPPED
                 .equ	TCNT1L	= 0x84	; MEMORY MAPPED
                 
                 .equ TCCR1D = 0x83 ; MEMORY MAPPED 
                  
                 .equ	TCCR1C	= 0x82	; MEMORY MAPPED
                 .equ	TCCR1B	= 0x81	; MEMORY MAPPED
                 .equ	TCCR1A	= 0x80	; MEMORY MAPPED
                 .equ	DIDR1	= 0x7f	; MEMORY MAPPED
                 .equ	DIDR0	= 0x7e	; MEMORY MAPPED
                 
                 .equ ADCSRC = 0x7D ; MEMORY MAPPED 
                  
                 .equ	ADMUX	= 0x7c	; MEMORY MAPPED
                 .equ	ADCSRB	= 0x7b	; MEMORY MAPPED
                 .equ	ADCSRA	= 0x7a	; MEMORY MAPPED
                 .equ	ADCH	= 0x79	; MEMORY MAPPED
                 .equ	ADCL	= 0x78	; MEMORY MAPPED
                 
                 .equ DIDR2  = 0x76 ; MEMORY MAPPED 
                 .equ IVBASE = 0x75 ; MEMORY MAPPED Interrupt Vector Base Address
                 .equ PCMSK4 = 0x74 ; MEMORY MAPPED 
                 .equ PCMSK3 = 0x73 ; MEMORY MAPPED 
                 .equ TIMSK3 = 0x71 ; MEMORY MAPPED 
                 
                 .equ	TIMSK2	= 0x70	; MEMORY MAPPED
                 .equ	TIMSK1	= 0x6f	; MEMORY MAPPED
                 .equ	TIMSK0	= 0x6e	; MEMORY MAPPED
                 .equ	PCMSK1	= 0x6c	; MEMORY MAPPED
                 .equ	PCMSK2	= 0x6d	; MEMORY MAPPED
                 .equ	PCMSK0	= 0x6b	; MEMORY MAPPED
                 .equ	EICRA	= 0x69	; MEMORY MAPPED
                 .equ	PCICR	= 0x68	; MEMORY MAPPED
                 
                 .equ RCKCAL = 0x67 ; MEMORY MAPPED RC32K Calibration
                 
                 .equ	OSCCAL	= 0x66	; MEMORY MAPPED
                 
                 .equ PRR1   = 0x65 ; MEMORY MAPPED 
                 
                 .equ	PRR	= 0x64	; MEMORY MAPPED
                 
                 .equ VDTCR = 0x62 ; MEMORY MAPPED 
                 
                 .equ	CLKPR	= 0x61	; MEMORY MAPPED
                 .equ	WDTCSR	= 0x60	; MEMORY MAPPED
                 
                 ; Direct registers below be used with IN/OUT instructions.
                 ; Address mean number of register, equal to absolute 
                 ; address (in brackets) minus 0x20.
                 
                 .equ	SREG	= 0x3f 
                 .equ	SPH	= 0x3e 
                 .equ	SPL	= 0x3d 
                 
                 .equ	E2PD3	= 0x3C ;(0x5C) E2PCTL Data register byte 3
                 .equ	C1TR	= 0x3B ;(0x5B) AC1 trimming data
                 .equ	E2PD1	= 0x3A ;(0x5A) E2PCTL Data register byte 1
                 .equ	DSAH	= 0x39 ;(0x59) DSA[31:16] access port of uDSC
                 .equ	DSAL	= 0x38 ;(0x58) DSA[15:0] access port of uDSC
                 .equ	E2PD2	= 0x37 ;(0x57) E2PCTL Data register byte 2
                 ;.equ	SPMCSR	= 0x37 - absent in LGT8F328P
                 .equ	ECCR	= 0x36 ;(0x56) 
                 
                 .equ	MCUCR	= 0x35
                 .equ	MCUSR	= 0x34
                 .equ	SMCR	= 0x33
                 
                 .equ	C0TR	= 0x32 ;(0x52) AC0 Trimming register
                 .equ	C0XR	= 0x31 ;(0x51) 
                  
                 .equ	ACSR	= 0x30
                 
                 .equ	DTR0	= 0x2F ;(0x4F) TC0 Dead-band timing control register
                  
                 .equ	SPDR	= 0x2e
                 .equ	SPSR	= 0x2d
                 .equ	SPCR	= 0x2c
                 .equ	GPIOR2	= 0x2b
                 .equ	GPIOR1	= 0x2a
                 
                 .equ	TCCR0C	= 0x29 ;(0x49) 
                  
                 .equ	OCR0B	= 0x28
                 .equ	OCR0A	= 0x27
                 .equ	TCNT0	= 0x26
                 .equ	TCCR0B	= 0x25
                 .equ	TCCR0A	= 0x24
                 .equ	GTCCR	= 0x23
                 .equ	EEARH	= 0x22
                 .equ	EEARL	= 0x21
                 .equ	EEDR	= 0x20
                 .equ	EECR	= 0x1f
                 .equ	GPIOR0	= 0x1e
                 .equ	EIMSK	= 0x1d
                 .equ	EIFR	= 0x1c
                 .equ	PCIFR	= 0x1b
                 
                 .equ	C1XR	= 0x1A ;(0x3A)
                 .equ	SPFR	= 0x19 ;(0x39)
                 .equ	TIFR3	= 0x18 ;(0x38)
                   
                 .equ	TIFR2	= 0x17
                 .equ	TIFR1	= 0x16
                 .equ	TIFR0	= 0x15
                 
                 .equ	PORTF	= 0x14 ;(0x34) Port Output of Group F
                 .equ	DDRF	= 0x13 ;(0x33) Data Direction of Group F
                 .equ	PINF	= 0x12 ;(0x32) Port Input of Group F
                 .equ	DSDY	= 0x11 ;(0x31) DSDY access port of uDSC
                 .equ	DSDX	= 0x10 ;(0x30) DSDX access port of uDSC
                 .equ	C1SR	= 0x0F ;(0x2F) DSDX access port of uDSC
                 .equ	PORTE	= 0x0E ;(0x2E) Port Output of Group E
                 .equ	DDRE	= 0x0D ;(0x2D) Data Direction of Group F
                 .equ	PINE	= 0x0C ;(0x2C) Port Input of Group E
                  
                 .equ	PORTD	= 0x0b
                 .equ	DDRD	= 0x0a
                 .equ	PIND	= 0x09
                 .equ	PORTC	= 0x08
                 .equ	DDRC	= 0x07
                 .equ	PINC	= 0x06
                 .equ	PORTB	= 0x05
                 .equ	DDRB	= 0x04
                 .equ	PINB	= 0x03
                 
                 .equ	DSSD	= 0x02 ;(0x22) DSSD access port of uDSC
                 .equ	DSIR	= 0x01 ;(0x21) Instruction regiter of uDSC
                 .equ	DSCR	= 0x00 ;(0x20) Instruction regiter of uDSC
                  
                 ; ***** BIT DEFINITIONS **************************************************
                 
                 ; ***** ATmega328 bits **************************************************
                 ; ***** USART0 ***********************
                 ; UDR - USART I/O Data Register
                 .equ	UDR_0	= 0	; USART I/O Data Register bit 0
                 .equ	UDR_1	= 1	; USART I/O Data Register bit 1
                 .equ	UDR_2	= 2	; USART I/O Data Register bit 2
                 .equ	UDR_3	= 3	; USART I/O Data Register bit 3
                 .equ	UDR_4	= 4	; USART I/O Data Register bit 4
                 .equ	UDR_5	= 5	; USART I/O Data Register bit 5
                 .equ	UDR_6	= 6	; USART I/O Data Register bit 6
                 .equ	UDR_7	= 7	; USART I/O Data Register bit 7
                 
                 ; UCSRA - USART Control and Status Register A
                 .equ	MPCM	= 0	; Multi-processor Communication Mode
                 .equ	U2X	= 1	; Double the USART transmission speed
                 .equ	UPE	= 2	; Parity Error
                 .equ	DOR	= 3	; Data overRun
                 .equ	FE	= 4	; Framing Error
                 .equ	UDRE	= 5	; USART Data Register Empty
                 .equ	TXC	= 6	; USART Transmitt Complete
                 .equ	RXC	= 7	; USART Receive Complete
                 
                 ; UCSRB - USART Control and Status Register B
                 .equ	TXB8	= 0	; Transmit Data Bit 8
                 .equ	RXB8	= 1	; Receive Data Bit 8
                 .equ	UCSZ2	= 2	; Character Size
                 .equ	TXEN	= 3	; Transmitter Enable
                 .equ	RXEN	= 4	; Receiver Enable
                 .equ	UDRIE	= 5	; USART Data register Empty Interrupt Enable
                 .equ	TXCIE	= 6	; TX Complete Interrupt Enable
                 .equ	RXCIE	= 7	; RX Complete Interrupt Enable
                 
                 ; UCSRC - USART Control and Status Register C
                 .equ	UCPOL	= 0	; Clock Polarity
                 .equ	UCSZ0	= 1	; Character Size
                 .equ	UCPHA	= UCSZ0	; For compatibility
                 .equ	UCSZ1	= 2	; Character Size
                 .equ	UDORD	= UCSZ1	; For compatibility
                 .equ	USBS	= 3	; Stop Bit Select
                 .equ	UPM0	= 4	; Parity Mode Bit 0
                 .equ	UPM1	= 5	; Parity Mode Bit 1
                 .equ	UMSEL0	= 6	; USART Mode Select
                 .equ	UMSEL1	= 7	; USART Mode Select
                 
                 ; UBRRH - USART Baud Rate Register High Byte
                 .equ	UBRR8	= 0	; USART Baud Rate Register bit 8
                 .equ	UBRR9	= 1	; USART Baud Rate Register bit 9
                 .equ	UBRR10	= 2	; USART Baud Rate Register bit 10
                 .equ	UBRR11	= 3	; USART Baud Rate Register bit 11
                 
                 ; UBRRL - USART Baud Rate Register Low Byte
                 .equ	UBRR0	= 0	; USART Baud Rate Register bit 0
                 .equ	UBRR1	= 1	; USART Baud Rate Register bit 1
                 .equ	UBRR2	= 2	; USART Baud Rate Register bit 2
                 .equ	UBRR3	= 3	; USART Baud Rate Register bit 3
                 .equ	UBRR4	= 4	; USART Baud Rate Register bit 4
                 .equ	UBRR5	= 5	; USART Baud Rate Register bit 5
                 .equ	UBRR6	= 6	; USART Baud Rate Register bit 6
                 .equ	UBRR7	= 7	; USART Baud Rate Register bit 7
                 
                 
                 ; ***** TWI **************************
                 ; TWAMR - TWI (Slave) Address Mask Register
                 .equ	TWAM0	= 1	; 
                 .equ	TWAMR0	= TWAM0	; For compatibility
                 .equ	TWAM1	= 2	; 
                 .equ	TWAMR1	= TWAM1	; For compatibility
                 .equ	TWAM2	= 3	; 
                 .equ	TWAMR2	= TWAM2	; For compatibility
                 .equ	TWAM3	= 4	; 
                 .equ	TWAMR3	= TWAM3	; For compatibility
                 .equ	TWAM4	= 5	; 
                 .equ	TWAMR4	= TWAM4	; For compatibility
                 .equ	TWAM5	= 6	; 
                 .equ	TWAMR5	= TWAM5	; For compatibility
                 .equ	TWAM6	= 7	; 
                 .equ	TWAMR6	= TWAM6	; For compatibility
                 
                 ; TWBR - TWI Bit Rate register
                 .equ	TWBR0	= 0	; 
                 .equ	TWBR1	= 1	; 
                 .equ	TWBR2	= 2	; 
                 .equ	TWBR3	= 3	; 
                 .equ	TWBR4	= 4	; 
                 .equ	TWBR5	= 5	; 
                 .equ	TWBR6	= 6	; 
                 .equ	TWBR7	= 7	; 
                 
                 ; TWCR - TWI Control Register
                 .equ	TWIE	= 0	; TWI Interrupt Enable
                 .equ	TWEN	= 2	; TWI Enable Bit
                 .equ	TWWC	= 3	; TWI Write Collition Flag
                 .equ	TWSTO	= 4	; TWI Stop Condition Bit
                 .equ	TWSTA	= 5	; TWI Start Condition Bit
                 .equ	TWEA	= 6	; TWI Enable Acknowledge Bit
                 .equ	TWINT	= 7	; TWI Interrupt Flag
                 
                 ; TWSR - TWI Status Register
                 .equ	TWPS0	= 0	; TWI Prescaler
                 .equ	TWPS1	= 1	; TWI Prescaler
                 .equ	TWS3	= 3	; TWI Status
                 .equ	TWS4	= 4	; TWI Status
                 .equ	TWS5	= 5	; TWI Status
                 .equ	TWS6	= 6	; TWI Status
                 .equ	TWS7	= 7	; TWI Status
                 
                 ; TWDR - TWI Data register
                 .equ	TWD0	= 0	; TWI Data Register Bit 0
                 .equ	TWD1	= 1	; TWI Data Register Bit 1
                 .equ	TWD2	= 2	; TWI Data Register Bit 2
                 .equ	TWD3	= 3	; TWI Data Register Bit 3
                 .equ	TWD4	= 4	; TWI Data Register Bit 4
                 .equ	TWD5	= 5	; TWI Data Register Bit 5
                 .equ	TWD6	= 6	; TWI Data Register Bit 6
                 .equ	TWD7	= 7	; TWI Data Register Bit 7
                 
                 ; TWAR - TWI (Slave) Address register
                 .equ	TWGCE	= 0	; TWI General Call Recognition Enable Bit
                 .equ	TWA0	= 1	; TWI (Slave) Address register Bit 0
                 .equ	TWA1	= 2	; TWI (Slave) Address register Bit 1
                 .equ	TWA2	= 3	; TWI (Slave) Address register Bit 2
                 .equ	TWA3	= 4	; TWI (Slave) Address register Bit 3
                 .equ	TWA4	= 5	; TWI (Slave) Address register Bit 4
                 .equ	TWA5	= 6	; TWI (Slave) Address register Bit 5
                 .equ	TWA6	= 7	; TWI (Slave) Address register Bit 6
                 
                 
                 ; ***** TIMER_COUNTER_1 **************
                 ; TIMSK1 - Timer/Counter Interrupt Mask Register
                 .equ	TOIE1	= 0	; Timer/Counter1 Overflow Interrupt Enable
                 .equ	OCIE1A	= 1	; Timer/Counter1 Output CompareA Match Interrupt Enable
                 .equ	OCIE1B	= 2	; Timer/Counter1 Output CompareB Match Interrupt Enable
                 .equ	ICIE1	= 5	; Timer/Counter1 Input Capture Interrupt Enable
                 
                 ; TIFR1 - Timer/Counter Interrupt Flag register
                 .equ	TOV1	= 0	; Timer/Counter1 Overflow Flag
                 .equ	OCF1A	= 1	; Output Compare Flag 1A
                 .equ	OCF1B	= 2	; Output Compare Flag 1B
                 .equ	ICF1	= 5	; Input Capture Flag 1
                 
                 ; TCCR1A - Timer/Counter1 Control Register A
                 .equ	WGM10	= 0	; Waveform Generation Mode
                 .equ	WGM11	= 1	; Waveform Generation Mode
                 .equ	COM1B0	= 4	; Compare Output Mode 1B, bit 0
                 .equ	COM1B1	= 5	; Compare Output Mode 1B, bit 1
                 .equ	COM1A0	= 6	; Comparet Ouput Mode 1A, bit 0
                 .equ	COM1A1	= 7	; Compare Output Mode 1A, bit 1
                 
                 ; TCCR1B - Timer/Counter1 Control Register B
                 .equ	CS10	= 0	; Prescaler source of Timer/Counter 1
                 .equ	CS11	= 1	; Prescaler source of Timer/Counter 1
                 .equ	CS12	= 2	; Prescaler source of Timer/Counter 1
                 .equ	WGM12	= 3	; Waveform Generation Mode
                 .equ	WGM13	= 4	; Waveform Generation Mode
                 .equ	ICES1	= 6	; Input Capture 1 Edge Select
                 .equ	ICNC1	= 7	; Input Capture 1 Noise Canceler
                 
                 ; TCCR1C - Timer/Counter1 Control Register C
                 .equ	FOC1B	= 6	; 
                 .equ	FOC1A	= 7	; 
                 
                 ; GTCCR - General Timer/Counter Control Register
                 .equ	PSRSYNC	= 0	; Prescaler Reset Timer/Counter1 and Timer/Counter0
                 .equ	TSM	= 7	; Timer/Counter Synchronization Mode
                 
                 
                 ; ***** TIMER_COUNTER_2 **************
                 ; TIMSK2 - Timer/Counter Interrupt Mask register
                 .equ	TOIE2	= 0	; Timer/Counter2 Overflow Interrupt Enable
                 .equ	TOIE2A	= TOIE2	; For compatibility
                 .equ	OCIE2A	= 1	; Timer/Counter2 Output Compare Match A Interrupt Enable
                 .equ	OCIE2B	= 2	; Timer/Counter2 Output Compare Match B Interrupt Enable
                 
                 ; TIFR2 - Timer/Counter Interrupt Flag Register
                 .equ	TOV2	= 0	; Timer/Counter2 Overflow Flag
                 .equ	OCF2A	= 1	; Output Compare Flag 2A
                 .equ	OCF2B	= 2	; Output Compare Flag 2B
                 
                 ; TCCR2A - Timer/Counter2 Control Register A
                 .equ	WGM20	= 0	; Waveform Genration Mode
                 .equ	WGM21	= 1	; Waveform Genration Mode
                 .equ	COM2B0	= 4	; Compare Output Mode bit 0
                 .equ	COM2B1	= 5	; Compare Output Mode bit 1
                 .equ	COM2A0	= 6	; Compare Output Mode bit 1
                 .equ	COM2A1	= 7	; Compare Output Mode bit 1
                 
                 ; TCCR2B - Timer/Counter2 Control Register B
                 .equ	CS20	= 0	; Clock Select bit 0
                 .equ	CS21	= 1	; Clock Select bit 1
                 .equ	CS22	= 2	; Clock Select bit 2
                 .equ	WGM22	= 3	; Waveform Generation Mode
                 .equ	FOC2B	= 6	; Force Output Compare B
                 .equ	FOC2A	= 7	; Force Output Compare A
                 
                 ; TCNT2 - Timer/Counter2
                 .equ	TCNT2_0	= 0	; Timer/Counter 2 bit 0
                 .equ	TCNT2_1	= 1	; Timer/Counter 2 bit 1
                 .equ	TCNT2_2	= 2	; Timer/Counter 2 bit 2
                 .equ	TCNT2_3	= 3	; Timer/Counter 2 bit 3
                 .equ	TCNT2_4	= 4	; Timer/Counter 2 bit 4
                 .equ	TCNT2_5	= 5	; Timer/Counter 2 bit 5
                 .equ	TCNT2_6	= 6	; Timer/Counter 2 bit 6
                 .equ	TCNT2_7	= 7	; Timer/Counter 2 bit 7
                 
                 ; OCR2A - Timer/Counter2 Output Compare Register A
                 .equ	OCR2A_0	= 0	; Timer/Counter2 Output Compare Register Bit 0
                 .equ	OCR2A_1	= 1	; Timer/Counter2 Output Compare Register Bit 1
                 .equ	OCR2A_2	= 2	; Timer/Counter2 Output Compare Register Bit 2
                 .equ	OCR2A_3	= 3	; Timer/Counter2 Output Compare Register Bit 3
                 .equ	OCR2A_4	= 4	; Timer/Counter2 Output Compare Register Bit 4
                 .equ	OCR2A_5	= 5	; Timer/Counter2 Output Compare Register Bit 5
                 .equ	OCR2A_6	= 6	; Timer/Counter2 Output Compare Register Bit 6
                 .equ	OCR2A_7	= 7	; Timer/Counter2 Output Compare Register Bit 7
                 
                 ; OCR2B - Timer/Counter2 Output Compare Register B
                 .equ	OCR2B_0	= 0	; Timer/Counter2 Output Compare Register Bit 0
                 .equ	OCR2B_1	= 1	; Timer/Counter2 Output Compare Register Bit 1
                 .equ	OCR2B_2	= 2	; Timer/Counter2 Output Compare Register Bit 2
                 .equ	OCR2B_3	= 3	; Timer/Counter2 Output Compare Register Bit 3
                 .equ	OCR2B_4	= 4	; Timer/Counter2 Output Compare Register Bit 4
                 .equ	OCR2B_5	= 5	; Timer/Counter2 Output Compare Register Bit 5
                 .equ	OCR2B_6	= 6	; Timer/Counter2 Output Compare Register Bit 6
                 .equ	OCR2B_7	= 7	; Timer/Counter2 Output Compare Register Bit 7
                 
                 ; ASSR - Asynchronous Status Register
                 .equ	TCR2BUB	= 0	; Timer/Counter Control Register2 Update Busy
                 .equ	TCR2AUB	= 1	; Timer/Counter Control Register2 Update Busy
                 .equ	OCR2BUB	= 2	; Output Compare Register 2 Update Busy
                 .equ	OCR2AUB	= 3	; Output Compare Register2 Update Busy
                 .equ	TCN2UB	= 4	; Timer/Counter2 Update Busy
                 .equ	AS2	= 5	; Asynchronous Timer/Counter2
                 .equ	EXCLK	= 6	; Enable External Clock Input
                 
                 ; GTCCR - General Timer Counter Control register
                 .equ	PSRASY	= 1	; Prescaler Reset Timer/Counter2
                 .equ	PSR2	= PSRASY	; For compatibility
                 ;.equ	TSM	= 7	; Timer/Counter Synchronization Mode
                 
                 
                 ; ***** AD_CONVERTER *****************
                 ; ADMUX - The ADC multiplexer Selection Register
                 .equ	MUX0	= 0	; Analog Channel and Gain Selection Bits
                 .equ	MUX1	= 1	; Analog Channel and Gain Selection Bits
                 .equ	MUX2	= 2	; Analog Channel and Gain Selection Bits
                 .equ	MUX3	= 3	; Analog Channel and Gain Selection Bits
                 .equ	ADLAR	= 5	; Left Adjust Result
                 .equ	REFS0	= 6	; Reference Selection Bit 0
                 .equ	REFS1	= 7	; Reference Selection Bit 1
                 
                 ; ADCSRA - The ADC Control and Status register A
                 .equ	ADPS0	= 0	; ADC  Prescaler Select Bits
                 .equ	ADPS1	= 1	; ADC  Prescaler Select Bits
                 .equ	ADPS2	= 2	; ADC  Prescaler Select Bits
                 .equ	ADIE	= 3	; ADC Interrupt Enable
                 .equ	ADIF	= 4	; ADC Interrupt Flag
                 .equ	ADATE	= 5	; ADC  Auto Trigger Enable
                 .equ	ADSC	= 6	; ADC Start Conversion
                 .equ	ADEN	= 7	; ADC Enable
                 
                 ; ADCSRB - The ADC Control and Status register B
                 .equ	ADTS0	= 0	; ADC Auto Trigger Source bit 0
                 .equ	ADTS1	= 1	; ADC Auto Trigger Source bit 1
                 .equ	ADTS2	= 2	; ADC Auto Trigger Source bit 2
                 .equ	ACME	= 6	; 
                 
                 ; ADCH - ADC Data Register High Byte
                 .equ	ADCH0	= 0	; ADC Data Register High Byte Bit 0
                 .equ	ADCH1	= 1	; ADC Data Register High Byte Bit 1
                 .equ	ADCH2	= 2	; ADC Data Register High Byte Bit 2
                 .equ	ADCH3	= 3	; ADC Data Register High Byte Bit 3
                 .equ	ADCH4	= 4	; ADC Data Register High Byte Bit 4
                 .equ	ADCH5	= 5	; ADC Data Register High Byte Bit 5
                 .equ	ADCH6	= 6	; ADC Data Register High Byte Bit 6
                 .equ	ADCH7	= 7	; ADC Data Register High Byte Bit 7
                 
                 ; ADCL - ADC Data Register Low Byte
                 .equ	ADCL0	= 0	; ADC Data Register Low Byte Bit 0
                 .equ	ADCL1	= 1	; ADC Data Register Low Byte Bit 1
                 .equ	ADCL2	= 2	; ADC Data Register Low Byte Bit 2
                 .equ	ADCL3	= 3	; ADC Data Register Low Byte Bit 3
                 .equ	ADCL4	= 4	; ADC Data Register Low Byte Bit 4
                 .equ	ADCL5	= 5	; ADC Data Register Low Byte Bit 5
                 .equ	ADCL6	= 6	; ADC Data Register Low Byte Bit 6
                 .equ	ADCL7	= 7	; ADC Data Register Low Byte Bit 7
                 
                 ; DIDR0 - Digital Input Disable Register
                 .equ	ADC0D	= 0	; 
                 .equ	ADC1D	= 1	; 
                 .equ	ADC2D	= 2	; 
                 .equ	ADC3D	= 3	; 
                 .equ	ADC4D	= 4	; 
                 .equ	ADC5D	= 5	; 
                 
                 
                 ; ***** ANALOG_COMPARATOR ************
                 ; ACSR - Analog Comparator Control And Status Register
                 .equ	ACIS0	= 0	; Analog Comparator Interrupt Mode Select bit 0
                 .equ	ACIS1	= 1	; Analog Comparator Interrupt Mode Select bit 1
                 .equ	ACIC	= 2	; Analog Comparator Input Capture Enable
                 .equ	ACIE	= 3	; Analog Comparator Interrupt Enable
                 .equ	ACI	= 4	; Analog Comparator Interrupt Flag
                 .equ	ACO	= 5	; Analog Compare Output
                 .equ	ACBG	= 6	; Analog Comparator Bandgap Select
                 .equ	ACD	= 7	; Analog Comparator Disable
                 
                 ; DIDR1 - Digital Input Disable Register 1
                 .equ	AIN0D	= 0	; AIN0 Digital Input Disable
                 .equ	AIN1D	= 1	; AIN1 Digital Input Disable
                 
                 
                 ; ***** PORTB ************************
                 ; PORTB - Port B Data Register
                 .equ	PORTB0	= 0	; Port B Data Register bit 0
                 .equ	PB0	= 0	; For compatibility
                 .equ	PORTB1	= 1	; Port B Data Register bit 1
                 .equ	PB1	= 1	; For compatibility
                 .equ	PORTB2	= 2	; Port B Data Register bit 2
                 .equ	PB2	= 2	; For compatibility
                 .equ	PORTB3	= 3	; Port B Data Register bit 3
                 .equ	PB3	= 3	; For compatibility
                 .equ	PORTB4	= 4	; Port B Data Register bit 4
                 .equ	PB4	= 4	; For compatibility
                 .equ	PORTB5	= 5	; Port B Data Register bit 5
                 .equ	PB5	= 5	; For compatibility
                 .equ	PORTB6	= 6	; Port B Data Register bit 6
                 .equ	PB6	= 6	; For compatibility
                 .equ	PORTB7	= 7	; Port B Data Register bit 7
                 .equ	PB7	= 7	; For compatibility
                 
                 ; DDRB - Port B Data Direction Register
                 .equ	DDB0	= 0	; Port B Data Direction Register bit 0
                 .equ	DDB1	= 1	; Port B Data Direction Register bit 1
                 .equ	DDB2	= 2	; Port B Data Direction Register bit 2
                 .equ	DDB3	= 3	; Port B Data Direction Register bit 3
                 .equ	DDB4	= 4	; Port B Data Direction Register bit 4
                 .equ	DDB5	= 5	; Port B Data Direction Register bit 5
                 .equ	DDB6	= 6	; Port B Data Direction Register bit 6
                 .equ	DDB7	= 7	; Port B Data Direction Register bit 7
                 
                 ; PINB - Port B Input Pins
                 .equ	PINB0	= 0	; Port B Input Pins bit 0
                 .equ	PINB1	= 1	; Port B Input Pins bit 1
                 .equ	PINB2	= 2	; Port B Input Pins bit 2
                 .equ	PINB3	= 3	; Port B Input Pins bit 3
                 .equ	PINB4	= 4	; Port B Input Pins bit 4
                 .equ	PINB5	= 5	; Port B Input Pins bit 5
                 .equ	PINB6	= 6	; Port B Input Pins bit 6
                 .equ	PINB7	= 7	; Port B Input Pins bit 7
                 
                 
                 ; ***** PORTC ************************
                 ; PORTC - Port C Data Register
                 .equ	PORTC0	= 0	; Port C Data Register bit 0
                 .equ	PC0	= 0	; For compatibility
                 .equ	PORTC1	= 1	; Port C Data Register bit 1
                 .equ	PC1	= 1	; For compatibility
                 .equ	PORTC2	= 2	; Port C Data Register bit 2
                 .equ	PC2	= 2	; For compatibility
                 .equ	PORTC3	= 3	; Port C Data Register bit 3
                 .equ	PC3	= 3	; For compatibility
                 .equ	PORTC4	= 4	; Port C Data Register bit 4
                 .equ	PC4	= 4	; For compatibility
                 .equ	PORTC5	= 5	; Port C Data Register bit 5
                 .equ	PC5	= 5	; For compatibility
                 .equ	PORTC6	= 6	; Port C Data Register bit 6
                 .equ	PC6	= 6	; For compatibility
                 
                 ; DDRC - Port C Data Direction Register
                 .equ	DDC0	= 0	; Port C Data Direction Register bit 0
                 .equ	DDC1	= 1	; Port C Data Direction Register bit 1
                 .equ	DDC2	= 2	; Port C Data Direction Register bit 2
                 .equ	DDC3	= 3	; Port C Data Direction Register bit 3
                 .equ	DDC4	= 4	; Port C Data Direction Register bit 4
                 .equ	DDC5	= 5	; Port C Data Direction Register bit 5
                 .equ	DDC6	= 6	; Port C Data Direction Register bit 6
                 
                 ; PINC - Port C Input Pins
                 .equ	PINC0	= 0	; Port C Input Pins bit 0
                 .equ	PINC1	= 1	; Port C Input Pins bit 1
                 .equ	PINC2	= 2	; Port C Input Pins bit 2
                 .equ	PINC3	= 3	; Port C Input Pins bit 3
                 .equ	PINC4	= 4	; Port C Input Pins bit 4
                 .equ	PINC5	= 5	; Port C Input Pins bit 5
                 .equ	PINC6	= 6	; Port C Input Pins bit 6
                 
                 
                 ; ***** PORTD ************************
                 ; PORTD - Port D Data Register
                 .equ	PORTD0	= 0	; Port D Data Register bit 0
                 .equ	PD0	= 0	; For compatibility
                 .equ	PORTD1	= 1	; Port D Data Register bit 1
                 .equ	PD1	= 1	; For compatibility
                 .equ	PORTD2	= 2	; Port D Data Register bit 2
                 .equ	PD2	= 2	; For compatibility
                 .equ	PORTD3	= 3	; Port D Data Register bit 3
                 .equ	PD3	= 3	; For compatibility
                 .equ	PORTD4	= 4	; Port D Data Register bit 4
                 .equ	PD4	= 4	; For compatibility
                 .equ	PORTD5	= 5	; Port D Data Register bit 5
                 .equ	PD5	= 5	; For compatibility
                 .equ	PORTD6	= 6	; Port D Data Register bit 6
                 .equ	PD6	= 6	; For compatibility
                 .equ	PORTD7	= 7	; Port D Data Register bit 7
                 .equ	PD7	= 7	; For compatibility
                 
                 ; DDRD - Port D Data Direction Register
                 .equ	DDD0	= 0	; Port D Data Direction Register bit 0
                 .equ	DDD1	= 1	; Port D Data Direction Register bit 1
                 .equ	DDD2	= 2	; Port D Data Direction Register bit 2
                 .equ	DDD3	= 3	; Port D Data Direction Register bit 3
                 .equ	DDD4	= 4	; Port D Data Direction Register bit 4
                 .equ	DDD5	= 5	; Port D Data Direction Register bit 5
                 .equ	DDD6	= 6	; Port D Data Direction Register bit 6
                 .equ	DDD7	= 7	; Port D Data Direction Register bit 7
                 
                 ; PIND - Port D Input Pins
                 .equ	PIND0	= 0	; Port D Input Pins bit 0
                 .equ	PIND1	= 1	; Port D Input Pins bit 1
                 .equ	PIND2	= 2	; Port D Input Pins bit 2
                 .equ	PIND3	= 3	; Port D Input Pins bit 3
                 .equ	PIND4	= 4	; Port D Input Pins bit 4
                 .equ	PIND5	= 5	; Port D Input Pins bit 5
                 .equ	PIND6	= 6	; Port D Input Pins bit 6
                 .equ	PIND7	= 7	; Port D Input Pins bit 7
                 
                 
                 ; ***** TIMER_COUNTER_0 **************
                 ; TIMSK0 - Timer/Counter0 Interrupt Mask Register
                 .equ	TOIE0	= 0	; Timer/Counter0 Overflow Interrupt Enable
                 .equ	OCIE0A	= 1	; Timer/Counter0 Output Compare Match A Interrupt Enable
                 .equ	OCIE0B	= 2	; Timer/Counter0 Output Compare Match B Interrupt Enable
                 
                 ; TIFR0 - Timer/Counter0 Interrupt Flag register
                 .equ	TOV0	= 0	; Timer/Counter0 Overflow Flag
                 .equ	OCF0A	= 1	; Timer/Counter0 Output Compare Flag 0A
                 .equ	OCF0B	= 2	; Timer/Counter0 Output Compare Flag 0B
                 
                 ; TCCR0A - Timer/Counter  Control Register A
                 .equ	WGM00	= 0	; Waveform Generation Mode
                 .equ	WGM01	= 1	; Waveform Generation Mode
                 .equ	COM0B0	= 4	; Compare Output Mode, Fast PWm
                 .equ	COM0B1	= 5	; Compare Output Mode, Fast PWm
                 .equ	COM0A0	= 6	; Compare Output Mode, Phase Correct PWM Mode
                 .equ	COM0A1	= 7	; Compare Output Mode, Phase Correct PWM Mode
                 
                 ; TCCR0B - Timer/Counter Control Register B
                 .equ	CS00	= 0	; Clock Select
                 .equ	CS01	= 1	; Clock Select
                 .equ	CS02	= 2	; Clock Select
                 .equ	WGM02	= 3	; 
                 .equ	FOC0B	= 6	; Force Output Compare B
                 .equ	FOC0A	= 7	; Force Output Compare A
                 
                 ; TCNT0 - Timer/Counter0
                 .equ	TCNT0_0	= 0	; 
                 .equ	TCNT0_1	= 1	; 
                 .equ	TCNT0_2	= 2	; 
                 .equ	TCNT0_3	= 3	; 
                 .equ	TCNT0_4	= 4	; 
                 .equ	TCNT0_5	= 5	; 
                 .equ	TCNT0_6	= 6	; 
                 .equ	TCNT0_7	= 7	; 
                 
                 ; OCR0A - Timer/Counter0 Output Compare Register
                 .equ	OCR0A_0	= 0	; 
                 .equ	OCR0A_1	= 1	; 
                 .equ	OCR0A_2	= 2	; 
                 .equ	OCR0A_3	= 3	; 
                 .equ	OCR0A_4	= 4	; 
                 .equ	OCR0A_5	= 5	; 
                 .equ	OCR0A_6	= 6	; 
                 .equ	OCR0A_7	= 7	; 
                 
                 ; OCR0B - Timer/Counter0 Output Compare Register
                 .equ	OCR0B_0	= 0	; 
                 .equ	OCR0B_1	= 1	; 
                 .equ	OCR0B_2	= 2	; 
                 .equ	OCR0B_3	= 3	; 
                 .equ	OCR0B_4	= 4	; 
                 .equ	OCR0B_5	= 5	; 
                 .equ	OCR0B_6	= 6	; 
                 .equ	OCR0B_7	= 7	; 
                 
                 ; GTCCR - General Timer/Counter Control Register
                 ;.equ	PSRSYNC	= 0	; Prescaler Reset Timer/Counter1 and Timer/Counter0
                 .equ	PSR10	= PSRSYNC	; For compatibility
                 ;.equ	TSM	= 7	; Timer/Counter Synchronization Mode
                 
                 
                 ; ***** EXTERNAL_INTERRUPT ***********
                 ; EICRA - External Interrupt Control Register
                 .equ	ISC00	= 0	; External Interrupt Sense Control 0 Bit 0
                 .equ	ISC01	= 1	; External Interrupt Sense Control 0 Bit 1
                 .equ	ISC10	= 2	; External Interrupt Sense Control 1 Bit 0
                 .equ	ISC11	= 3	; External Interrupt Sense Control 1 Bit 1
                 
                 ; EIMSK - External Interrupt Mask Register
                 .equ	INT0	= 0	; External Interrupt Request 0 Enable
                 .equ	INT1	= 1	; External Interrupt Request 1 Enable
                 
                 ; EIFR - External Interrupt Flag Register
                 .equ	INTF0	= 0	; External Interrupt Flag 0
                 .equ	INTF1	= 1	; External Interrupt Flag 1
                 
                 ; PCICR - Pin Change Interrupt Control Register
                 .equ	PCIE0	= 0	; Pin Change Interrupt Enable 0
                 .equ	PCIE1	= 1	; Pin Change Interrupt Enable 1
                 .equ	PCIE2	= 2	; Pin Change Interrupt Enable 2
                 
                 ; PCMSK2 - Pin Change Mask Register 2
                 .equ	PCINT16	= 0	; Pin Change Enable Mask 16
                 .equ	PCINT17	= 1	; Pin Change Enable Mask 17
                 .equ	PCINT18	= 2	; Pin Change Enable Mask 18
                 .equ	PCINT19	= 3	; Pin Change Enable Mask 19
                 .equ	PCINT20	= 4	; Pin Change Enable Mask 20
                 .equ	PCINT21	= 5	; Pin Change Enable Mask 21
                 .equ	PCINT22	= 6	; Pin Change Enable Mask 22
                 .equ	PCINT23	= 7	; Pin Change Enable Mask 23
                 
                 ; PCMSK1 - Pin Change Mask Register 1
                 .equ	PCINT8	= 0	; Pin Change Enable Mask 8
                 .equ	PCINT9	= 1	; Pin Change Enable Mask 9
                 .equ	PCINT10	= 2	; Pin Change Enable Mask 10
                 .equ	PCINT11	= 3	; Pin Change Enable Mask 11
                 .equ	PCINT12	= 4	; Pin Change Enable Mask 12
                 .equ	PCINT13	= 5	; Pin Change Enable Mask 13
                 .equ	PCINT14	= 6	; Pin Change Enable Mask 14
                 
                 ; PCMSK0 - Pin Change Mask Register 0
                 .equ	PCINT0	= 0	; Pin Change Enable Mask 0
                 .equ	PCINT1	= 1	; Pin Change Enable Mask 1
                 .equ	PCINT2	= 2	; Pin Change Enable Mask 2
                 .equ	PCINT3	= 3	; Pin Change Enable Mask 3
                 .equ	PCINT4	= 4	; Pin Change Enable Mask 4
                 .equ	PCINT5	= 5	; Pin Change Enable Mask 5
                 .equ	PCINT6	= 6	; Pin Change Enable Mask 6
                 .equ	PCINT7	= 7	; Pin Change Enable Mask 7
                 
                 ; PCIFR - Pin Change Interrupt Flag Register
                 .equ	PCIF0	= 0	; Pin Change Interrupt Flag 0
                 .equ	PCIF1	= 1	; Pin Change Interrupt Flag 1
                 .equ	PCIF2	= 2	; Pin Change Interrupt Flag 2
                 
                 
                 ; ***** SPI **************************
                 ; SPDR - SPI Data Register
                 .equ	SPDR0	= 0	; SPI Data Register bit 0
                 .equ	SPDR1	= 1	; SPI Data Register bit 1
                 .equ	SPDR2	= 2	; SPI Data Register bit 2
                 .equ	SPDR3	= 3	; SPI Data Register bit 3
                 .equ	SPDR4	= 4	; SPI Data Register bit 4
                 .equ	SPDR5	= 5	; SPI Data Register bit 5
                 .equ	SPDR6	= 6	; SPI Data Register bit 6
                 .equ	SPDR7	= 7	; SPI Data Register bit 7
                 
                 ; SPSR - SPI Status Register
                 .equ	SPI2X	= 0	; Double SPI Speed Bit
                 .equ	WCOL	= 6	; Write Collision Flag
                 .equ	SPIF	= 7	; SPI Interrupt Flag
                 
                 ; SPCR - SPI Control Register
                 .equ	SPR0	= 0	; SPI Clock Rate Select 0
                 .equ	SPR1	= 1	; SPI Clock Rate Select 1
                 .equ	CPHA	= 2	; Clock Phase
                 .equ	CPOL	= 3	; Clock polarity
                 .equ	MSTR	= 4	; Master/Slave Select
                 .equ	DORD	= 5	; Data Order
                 .equ	SPE	= 6	; SPI Enable
                 .equ	SPIE	= 7	; SPI Interrupt Enable
                 
                 
                 ; ***** WATCHDOG *********************
                 ; WDTCSR - Watchdog Timer Control Register
                 .equ	WDP0	= 0	; Watch Dog Timer Prescaler bit 0
                 .equ	WDP1	= 1	; Watch Dog Timer Prescaler bit 1
                 .equ	WDP2	= 2	; Watch Dog Timer Prescaler bit 2
                 .equ	WDE	= 3	; Watch Dog Enable
                 .equ	WDCE	= 4	; Watchdog Change Enable
                 .equ	WDP3	= 5	; Watchdog Timer Prescaler Bit 3
                 .equ	WDIE	= 6	; Watchdog Timeout Interrupt Enable
                 .equ	WDIF	= 7	; Watchdog Timeout Interrupt Flag
                 
                 
                 ; ***** CPU **************************
                 ; SREG - Status Register
                 .equ	SREG_C	= 0	; Carry Flag
                 .equ	SREG_Z	= 1	; Zero Flag
                 .equ	SREG_N	= 2	; Negative Flag
                 .equ	SREG_V	= 3	; Two's Complement Overflow Flag
                 .equ	SREG_S	= 4	; Sign Bit
                 .equ	SREG_H	= 5	; Half Carry Flag
                 .equ	SREG_T	= 6	; Bit Copy Storage
                 .equ	SREG_I	= 7	; Global Interrupt Enable
                 
                 ; OSCCAL - Oscillator Calibration Value
                 .equ	CAL0	= 0	; Oscillator Calibration Value Bit0
                 .equ	CAL1	= 1	; Oscillator Calibration Value Bit1
                 .equ	CAL2	= 2	; Oscillator Calibration Value Bit2
                 .equ	CAL3	= 3	; Oscillator Calibration Value Bit3
                 .equ	CAL4	= 4	; Oscillator Calibration Value Bit4
                 .equ	CAL5	= 5	; Oscillator Calibration Value Bit5
                 .equ	CAL6	= 6	; Oscillator Calibration Value Bit6
                 .equ	CAL7	= 7	; Oscillator Calibration Value Bit7
                 
                 ; CLKPR - Clock Prescale Register
                 .equ	CLKPS0	= 0	; Clock Prescaler Select Bit 0
                 .equ	CLKPS1	= 1	; Clock Prescaler Select Bit 1
                 .equ	CLKPS2	= 2	; Clock Prescaler Select Bit 2
                 .equ	CLKPS3	= 3	; Clock Prescaler Select Bit 3  
                 .equ	CKOEN0	= 5	; Clock Prescaler Select Bit 3 
                 .equ	CKOEN1	= 6	; Clock Prescaler Select Bit 3 
                 .equ	CLKPCE	= 7	; Clock Prescaler Change Enable
                 
                 ; SPMCSR - Store Program Memory Control and Status Register
                 .equ	SELFPRGEN	= 0	; Self Programming Enable
                 .equ	PGERS	= 1	; Page Erase
                 .equ	PGWRT	= 2	; Page Write
                 .equ	BLBSET	= 3	; Boot Lock Bit Set
                 .equ	RWWSRE	= 4	; Read-While-Write section read enable
                 .equ	RWWSB	= 6	; Read-While-Write Section Busy
                 .equ	SPMIE	= 7	; SPM Interrupt Enable
                 
                 ; MCUCR - MCU Control Register
                 .equ	IVCE	= 0	; 
                 .equ	IVSEL	= 1	; 
                 .equ	PUD	= 4	; 
                 .equ	BODSE	= 5	; BOD Sleep Enable
                 .equ	BODS	= 6	; BOD Sleep
                 
                 ; MCUSR - MCU Status Register
                 .equ	PORF	= 0	; Power-on reset flag
                 .equ	EXTRF	= 1	; External Reset Flag
                 .equ	EXTREF	= EXTRF	; For compatibility
                 .equ	BORF	= 2	; Brown-out Reset Flag
                 .equ	WDRF	= 3	; Watchdog Reset Flag
                 
                 ; SMCR - Sleep Mode Control Register
                 .equ	SE	= 0	; Sleep Enable
                 .equ	SM0	= 1	; Sleep Mode Select Bit 0
                 .equ	SM1	= 2	; Sleep Mode Select Bit 1
                 .equ	SM2	= 3	; Sleep Mode Select Bit 2
                 
                 ; GPIOR2 - General Purpose I/O Register 2
                 .equ	GPIOR20	= 0	; 
                 .equ	GPIOR21	= 1	; 
                 .equ	GPIOR22	= 2	; 
                 .equ	GPIOR23	= 3	; 
                 .equ	GPIOR24	= 4	; 
                 .equ	GPIOR25	= 5	; 
                 .equ	GPIOR26	= 6	; 
                 .equ	GPIOR27	= 7	; 
                 
                 ; GPIOR1 - General Purpose I/O Register 1
                 .equ	GPIOR10	= 0	; 
                 .equ	GPIOR11	= 1	; 
                 .equ	GPIOR12	= 2	; 
                 .equ	GPIOR13	= 3	; 
                 .equ	GPIOR14	= 4	; 
                 .equ	GPIOR15	= 5	; 
                 .equ	GPIOR16	= 6	; 
                 .equ	GPIOR17	= 7	; 
                 
                 ; GPIOR0 - General Purpose I/O Register 0
                 .equ	GPIOR00	= 0	; 
                 .equ	GPIOR01	= 1	; 
                 .equ	GPIOR02	= 2	; 
                 .equ	GPIOR03	= 3	; 
                 .equ	GPIOR04	= 4	; 
                 .equ	GPIOR05	= 5	; 
                 .equ	GPIOR06	= 6	; 
                 .equ	GPIOR07	= 7	; 
                 
                 ; PRR - Power Reduction Register
                 .equ	PRADC	= 0	; Power Reduction ADC
                 .equ	PRUSART0	= 1	; Power Reduction USART
                 .equ	PRSPI	= 2	; Power Reduction Serial Peripheral Interface
                 .equ	PRTIM1	= 3	; Power Reduction Timer/Counter1
                 .equ	PRTIM0	= 5	; Power Reduction Timer/Counter0
                 .equ	PRTIM2	= 6	; Power Reduction Timer/Counter2
                 .equ	PRTWI	= 7	; Power Reduction TWI
                 
                 
                 ; ***** EEPROM ***********************
                 ; EEARL - EEPROM Address Register Low Byte
                 .equ	EEAR0	= 0	; EEPROM Read/Write Access Bit 0
                 .equ	EEAR1	= 1	; EEPROM Read/Write Access Bit 1
                 .equ	EEAR2	= 2	; EEPROM Read/Write Access Bit 2
                 .equ	EEAR3	= 3	; EEPROM Read/Write Access Bit 3
                 .equ	EEAR4	= 4	; EEPROM Read/Write Access Bit 4
                 .equ	EEAR5	= 5	; EEPROM Read/Write Access Bit 5
                 .equ	EEAR6	= 6	; EEPROM Read/Write Access Bit 6
                 .equ	EEAR7	= 7	; EEPROM Read/Write Access Bit 7
                 
                 ; EEARH - EEPROM Address Register High Byte
                 .equ	EEAR8	= 0	; EEPROM Read/Write Access Bit 8
                 .equ	EEAR9	= 1	; EEPROM Read/Write Access Bit 9
                 
                 ; EEDR - EEPROM Data Register
                 .equ	EEDR0	= 0	; EEPROM Data Register bit 0
                 .equ	EEDR1	= 1	; EEPROM Data Register bit 1
                 .equ	EEDR2	= 2	; EEPROM Data Register bit 2
                 .equ	EEDR3	= 3	; EEPROM Data Register bit 3
                 .equ	EEDR4	= 4	; EEPROM Data Register bit 4
                 .equ	EEDR5	= 5	; EEPROM Data Register bit 5
                 .equ	EEDR6	= 6	; EEPROM Data Register bit 6
                 .equ	EEDR7	= 7	; EEPROM Data Register bit 7
                 
                 ; EECR - EEPROM Control Register
                 .equ	EERE	= 0	; EEPROM Read Enable
                 .equ	EEPE	= 1	; EEPROM Write Enable
                 .equ	EEMPE	= 2	; EEPROM Master Write Enable
                 .equ	EERIE	= 3	; EEPROM Ready Interrupt Enable
                 .equ	EEPM0	= 4	; EEPROM Programming Mode Bit 0
                 .equ	EEPM1	= 5	; EEPROM Programming Mode Bit 1
                 
                 ;****** LGT8F328P bits ***********************************
                 ; PMCR - Clock Source register
                 .equ	RCMEN	= 0	
                 .equ	RCKEN	= 1	
                 .equ	OSCMEN	= 2	
                 .equ	OSCKEN	= 3	
                 .equ	WCLKS	= 4	
                 .equ	CLKSS	= 5	
                 .equ	CLKFS	= 6	
                 .equ	PMCE	= 7	
                        
                 ; PMX2 - Port multiplexing control register 2
                 .equ	C6EN	= 0	
                 .equ	E6EN	= 1	
                 .equ	XIEN	= 2	
                 .equ	STOSC0	= 5	
                 .equ	STOSC1	= 6	
                 .equ	WCE	= 7	
                 
                 ; PMX0 - Port multiplexing control register 0
                 .equ	RXD5	= 0	
                 .equ	TXD6	= 1	
                 .equ	SSB1	= 2	
                 .equ	C0AC0	= 3	
                 .equ	C0BF3	= 4	
                 .equ	C1AF5	= 5	
                 .equ	C1BF4	= 6	
                 .equ	PMXCE	= 7	
                        
                 ; PMX1 - Port multiplexing control register 1
                 .equ	C2AF6	= 0	
                 .equ	C2BF7	= 1	
                 .equ	C3AC	= 2	
                   
                 ; TCKCSR - TC Clock control and status register
                 .equ	TC2XS0	= 0	
                 .equ	TC2XS1	= 1	
                 .equ	AFCKS	= 2	
                 .equ	TC2XF0	= 4	
                 .equ	TC2XF1	= 5	
                 .equ	F2XEN	= 6	
                 
                 ;PSSR - TMR0/1/3 Prescaler selection register
                 .equ	PSR1	= 0	
                 .equ	PSR3	= 1	
                 .equ	PSS3	= 6	
                 .equ	PSS1	= 7	
                 
                 ;OCPUE ?????? 
                 .equ	PUE0	= 0	
                 .equ	PUE1	= 1	
                 .equ	PUE2	= 2	
                 .equ	PUE3	= 3	
                 .equ	PUE4	= 4	
                 .equ	PUE5	= 5	
                 .equ	PUE6	= 6	
                 .equ	PUE7	= 7	
                 
                 ;HDR - High-current Dirve port control Register 
                 .equ	HDR0	= 0	
                 .equ	HDR1	= 1	
                 .equ	HDR2	= 2	
                 .equ	HDR3	= 3	
                 .equ	HDR4	= 4	
                 .equ	HDR5	= 5	
                 
                 ;DAPCR - Differential amplifier control register 
                 .equ	DPS0	= 0	
                 .equ	DPS1	= 1	
                 .equ	DNS0	= 2	
                 .equ	DNS1	= 3	
                 .equ	DNS2	= 4	
                 .equ	GA0	= 5	
                 .equ	GA1	= 6	
                 .equ	DAPEN	= 7	
                 
                 ;LDOCR ?????
                 .equ	VSEL0	= 0	
                 .equ	VSEL1	= 1	
                 .equ	VSEL2	= 2	
                 .equ	PDEN	= 3	
                 ;.equ	WCE	= 7	
                 
                 ;DPS2R - DPS2 Mode Control Register 
                 .equ	TOS0	= 0	
                 .equ	TOS1	= 1	
                 .equ	LPRCE	= 2	
                 .equ	DPS2E	= 3	
                 
                 ;IOCWK - PD Group level change wakeup control register 
                 .equ	IOCD0	= 0	
                 .equ	IOCD1	= 1	
                 .equ	IOCD2	= 2	
                 .equ	IOCD3	= 3	
                 .equ	IOCD4	= 4	
                 .equ	IOCD5	= 5	
                 .equ	IOCD6	= 6	
                 .equ	IOCD7	= 7	
                 
                 ;ADCSRD - ADC Control and status registers D 
                 .equ	VDS0	= 0	
                 .equ	VDS1	= 1	
                 .equ	VDS2	= 2	
                 .equ	IVSEL0	= 3	
                 .equ	IVSEL1	= 5	
                 .equ	REFS2	= 6	
                 .equ	BGEN	= 7	
                 
                 ;ADMSC - ADC Monitoring channel status and control register 
                 .equ	AMFC0	= 0	
                 .equ	AMFC1	= 1	
                 .equ	AMFC2	= 2	
                 .equ	AMFC3	= 3	
                 .equ	AMOF	= 7	
                 
                 ;DACON - DAC Control register 
                 .equ	DAVS0	= 0	
                 .equ	DAVS1	= 1	
                 .equ	DAOE	= 2	
                 .equ	DACEN	= 3	
                    
                 ;TCCR1D - TC1 Control register D 
                 .equ	DSX10	= 0	
                 .equ	DSX11	= 1	
                 .equ	DAX14	= 4	
                 .equ	DSX15	= 5	
                 .equ	DSX16	= 6	
                 .equ	DSX17	= 7	
                 
                 ;ADCSRC - ADC Control and status registers C 
                 .equ	ADTM	= 0	
                 .equ	DIFS	= 1	
                 .equ	SPD	= 2	
                 .equ	AMEN	= 4	
                 .equ	SPN	= 5	
                 .equ	OFEN	= 7	
                 
                 ;TIMSK3 - TC3 Interrupt mask register 
                 .equ	TOIE3	= 0	
                 .equ	OCIE3A	= 1	
                 .equ	OCIE3B	= 2	
                 .equ	OCIE3C	= 3	
                 .equ	ICIE3	= 5	
                 
                 ;PRR1 - Power control register 1
                 .equ	PRPCI	= 1	
                 .equ	PREFL	= 2	
                 .equ	PRTIM3	= 3	
                 .equ	PRWDT	= 5	
                 
                 ;VDTCR - Low voltage detection (LVD) Control Register 
                 .equ	VDTEN	= 0	
                 .equ	VDREN	= 1	
                 .equ	VDTS0	= 2	
                 .equ	VDTS1	= 3	
                 .equ	VDTS2	= 4	
                 .equ	SWR	= 6	
                 ;.equ	WCE	= 7	
                 
                 ; ECCR - FLASH Mode Control Register 
                 .equ	ECS0	= 0	
                 .equ	ECS1	= 1	
                 .equ	CP0	= 2	
                 .equ	CP1	= 3	
                 .equ	SWM	= 4	
                 .equ	ERN	= 5	
                 .equ	EEN	= 6	
                 .equ	WEN	= 7	
                 
                 ; C0XR - AC0 Auxiliary Control Register
                 .equ	C0FS0	= 0	
                 .equ	C0FS1	= 1	
                 .equ	C0FEN	= 2	
                 .equ	C0WKE	= 3	
                 .equ	C0PS0	= 4	
                 .equ	C0HYSE	= 5	
                 .equ	C0OE	= 6	
                 
                 ; TCCR0C - TC0 Control register C
                 .equ	DSX00	= 0	
                 .equ	DSX01	= 1	
                 .equ	DSX04	= 4	
                 .equ	DSX05	= 5	
                 .equ	DSX06	= 6	
                 .equ	DSX07	= 7	
                 
                 ; C1XR - AC1 Auxiliary Control Register
                 .equ	C1FS0	= 0	
                 .equ	C1FS1	= 1	
                 .equ	C1FEN	= 2	
                 .equ	C1WKE	= 3	
                 .equ	C1PS0	= 4	
                 .equ	C1HYSE	= 5	
                 .equ	C1OE	= 6	
                 
                 ; SPFR - SPI Buffer 
                 .equ	WRPTR0	= 0	
                 .equ	WRPTR1	= 1	
                 .equ	WREMPT	= 2	
                 .equ	WRFULL	= 3	
                 .equ	RDPTR0	= 4	
                 .equ	RDPTR1	= 5	
                 .equ	RDEMPT	= 6	
                 .equ	RDFULL	= 7	
                 
                 ; TIFR3 - - TC3 Interrupt Flag Register
                 .equ	TOV3	= 0	
                 .equ	OCF3A	= 1	
                 .equ	OCF3B	= 2	
                 .equ	OCF3C	= 3	
                 .equ	ICF3	= 5	
                 
                 ; C1SR - AC1 Control and status registers 
                 .equ	C1IS0	= 0	
                 .equ	C1IS1	= 1	
                 .equ	C1IC	= 2	
                 .equ	C1IE	= 3	
                 .equ	C1I	= 4	
                 .equ	C1O	= 5	
                 .equ	C1BG	= 6	
                 .equ	C1D	= 7	
                 
                 ; DSCR - Arithmetic accelerator (uDSC) Control Status Register 
                 .equ	DSC	= 0	
                 .equ	DSZ	= 1	
                 .equ	DSN	= 2	
                 ;.equ	D0	= 4	
                 ;.equ	D1	= 5	
                 .equ	MM	= 6	
                 .equ	DSUEN	= 7	
                 
                 
                 ; ***** CPU REGISTER DEFINITIONS *****************************************
                 .def	XH	= r27
                 .def	XL	= r26
                 .def	YH	= r29
                 .def	YL	= r28
                 .def	ZH	= r31
                 .def	ZL	= r30
                 
                 
                 ; ***** DATA MEMORY DECLARATIONS *****************************************
                 .equ	FLASHEND	= 0x3fff	; Note: Word address
                 .equ	IOEND	= 0x00ff
                 .equ	SRAM_START	= 0x0100
                 .equ	SRAM_SIZE	= 2048
                 .equ	RAMEND	= 0x08ff
                 .equ	XRAMEND	= 0x0000
                 .equ	E2END	= 0x03ff
                 .equ	EEPROMEND	= 0x03ff
                 .equ	EEADRBITS	= 10
                 #pragma AVRPART MEMORY PROG_FLASH 32768
                 #pragma AVRPART MEMORY INT_SRAM SIZE 2048
                 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
                 
                 
                 
                 ; ***** BOOTLOADER DECLARATIONS ******************************************
                 .equ	NRWW_START_ADDR	= 0x3800
                 .equ	NRWW_STOP_ADDR	= 0x3fff
                 .equ	RWW_START_ADDR	= 0x0
                 .equ	RWW_STOP_ADDR	= 0x37ff
                 .equ	PAGESIZE	= 64
                 .equ	FIRSTBOOTSTART	= 0x3f00
                 .equ	SECONDBOOTSTART	= 0x3e00
                 .equ	THIRDBOOTSTART	= 0x3c00
                 .equ	FOURTHBOOTSTART	= 0x3800
                 .equ	SMALLBOOTSTART	= FIRSTBOOTSTART
                 .equ	LARGEBOOTSTART	= FOURTHBOOTSTART
                 
                 
                 
                 ; ***** INTERRUPT VECTORS ************************************************
                 .equ	INT0addr	= 0x0002	; External Interrupt Request 0
                 .equ	INT1addr	= 0x0004	; External Interrupt Request 1
                 .equ	PCI0addr	= 0x0006	; Pin Change Interrupt Request 0
                 .equ	PCI1addr	= 0x0008	; Pin Change Interrupt Request 1
                 .equ	PCI2addr	= 0x000a	; Pin Change Interrupt Request 2
                 .equ	WDTaddr		= 0x000c	; Watchdog Time-out Interrupt
                 .equ	OC2Aaddr	= 0x000e	; Timer/Counter2 Compare Match A
                 .equ	OC2Baddr	= 0x0010	; Timer/Counter2 Compare Match A
                 .equ	OVF2addr	= 0x0012	; Timer/Counter2 Overflow
                 .equ	ICP1addr	= 0x0014	; Timer/Counter1 Capture Event
                 .equ	OC1Aaddr	= 0x0016	; Timer/Counter1 Compare Match A
                 .equ	OC1Baddr	= 0x0018	; Timer/Counter1 Compare Match B
                 .equ	OVF1addr	= 0x001a	; Timer/Counter1 Overflow
                 .equ	OC0Aaddr	= 0x001c	; TimerCounter0 Compare Match A
                 .equ	OC0Baddr	= 0x001e	; TimerCounter0 Compare Match B
                 .equ	OVF0addr	= 0x0020	; Timer/Couner0 Overflow
                 .equ	SPIaddr		= 0x0022	; SPI Serial Transfer Complete
                 .equ	URXCaddr	= 0x0024	; USART Rx Complete
                 .equ	UDREaddr	= 0x0026	; USART, Data Register Empty
                 .equ	UTXCaddr	= 0x0028	; USART Tx Complete
                 .equ	ADCCaddr	= 0x002a	; ADC Conversion Complete
                 .equ	ERDYaddr	= 0x002c	; EEPROM Ready
                 .equ	ACIaddr		= 0x002e	; Analog Comparator
                 .equ	TWIaddr		= 0x0030	; Two-wire Serial Interface
                 
                 ;below changes for LGT8F328P:
                 .equ	ANA_COMP1addr	= 0x0032	; Analog comparator 1 Interrupt
                 ;0x0034	reserved
                 .equ	PCI3addr	= 0x0036	; Pin Change Interrupt Request 3
                 .equ	PCI4addr	= 0x0038	; Pin Change Interrupt Request 4
                 .equ	TC3INTaddr	= 0x003a	; Timer 3 Interrupt
                 
                 .equ	INT_VECTORS_SIZE	= 60	; size in words
                 
                 #endif  /* _M328PDEF_INC_ */
                 
                 ; ***** END OF FILE ******************************************************
                  
                  .equ OLD_WRITE = 0
                  .equ DEBUG_ = 0
                  .include "macro.inc"
                 
                 .def CONSTFF	=r1
                 .def SREG_TEMP	=r2
                 ; .def COUNT_IP   =r3
                 
                 ;.def CMD_REG	=r4
                 .def TR_REG		=r5
                 .def SECT_REG	=r6
                 .def DAT_REG	=r7
                 
                 .def CRC_L		=r8
                 .def CRC_H		=r9	
                 
                 .def SECT_LEN	 = r10
                 .def SECT_LEN_H	 = r11
                 
                 .def OLD_CAPT   =r12
                 .def TEMP1      =r13
                 
                 .def TEMP_CMD   =r15
                 
                 .def TEMP		=r16 
                 .def CURR_CAPT  =r17 
                 
                 .def SHIFT_REG	=r18 
                 .def S_REG		=r19
                 
                 .def TEMP_D_REG =r20
                 
                 .def FLAGS		 = r21
                 .def SHIFT_COUNT = r22
                 .def SHIFT_REG_S = r23
                 
                 ;.def TIME       = r24
                 ;.def TEMP_ZH    =r25
                 
                 .equ  DATA_BUS	= PORTB
                 .equ  DIR_BUS	= DDRB
                 .equ  PIN_BUS	= PINB
                 .equ  PEREHOD	= PINC
                 
                 .equ	S_REG_BUSY		 = 0
                 .equ	S_REG_IP		 = 1
                 .equ    S_REG_DRQ		 = 1
                 
                 .equ	S_REG_TR00		 = 2
                 .equ    S_REG_DATA_LOST	 = 2 
                 
                 .equ	S_REG_CRC_ERR	 = 3
                 .equ	S_REG_SEEK_ERR	 = 4
                 
                 .equ	S_REG_HLD		 = 5
                 .equ    S_REG_TYPE_REC	 = 5
                 .equ    S_REG_WRITE_ERR	 = 5
                 
                 .equ	S_REG_WR_PR		 = 6
                 .equ	S_REG_READY		 = 7
                 
                 ;.equ    PMCR     = 0xF2
                 
                 .equ NEW_CMD	 = 0
                 .equ S_D_R		 = 1
                 .equ BREAK_IP	 = 2
                 .equ CMD_1_TYPE	 = 3
                 .equ READ_TR	 = 4
                 ;.equ PHASE		 = 5
                 .equ SYNC		 = 6
                 
                 .macro    align
                     .org    @0+PC-PC%@0
                 .endm
                 .macro STATE_M
                 	ldi XL, low(@0  )
                 	ldi XH, high(@0 ) 
                 .endm
                 .macro STATE_E
                 	ldi XL, low(@0  )
                 	ldi XH, high(@0 ) 
                 	rjmp _end_state
                 .endm
                 
                 .macro CLR_S_REG
                 		ser S_REG
                 .endm
                 .macro SET_S_REG_BIT
                 		andi S_REG , ~( 1 << @0 ) 
                 .endm
                 
                 .macro RES_S_REG_BIT
                 		ori S_REG , ( 1 << @0 )
                 .endm
                 .macro CHECK_S_REG_BIT
                 		sbrs S_REG , @0
                 .endm
                 
                 .macro INC_SECT_LEN
                 		inc SECT_LEN
                 		brne $inc_end
                 		inc SECT_LEN_H
                 $inc_end:
                 .endm
                 
                 
                 .macro INI_DELAY_4
                 		sts TCCR2A , CONST00
                 		sts TCCR2B , CONST00
                 		sts TIMSK2 , CONST00 
                 .endm
                 .macro START_DELAY_4
                 		ldi TEMP , 127
                 		sts OCR2A , TEMP
                 		ldi TEMP , 2 
                 		sts TCCR2A , TEMP
                 		sts TCNT2 , CONST00
                 		out TIFR2 , CONSTFF
                 		ldi TEMP , 1
                 		sts TCCR2B , TEMP
                 
                 .endm
                 .macro CHECK_DELAY_4
                 		sbis TIFR2 ,  OCF2A
                 .endm
                 
                 .macro STOP_DELAY_4
                 		sts TCCR2B , CONST00
                 .endm
                 
                 .macro INI_DELAY_32
                 		sts TCCR2A , CONST00
                 		sts TCCR2B , CONST00
                 		sts TIMSK2 , CONST00 
                 .endm
                 .macro START_DELAY_32
                 		sts TCCR2B , CONST00
                 		sts OCR2A , TEMP
                 		ldi TEMP , 2 
                 		sts TCCR2A , TEMP
                 		sts TCNT2 , CONST00
                 		out TIFR2 , CONSTFF
                 		ldi TEMP , 6
                 		sts TCCR2B , TEMP
                 
                 .endm
                 .macro CHECK_DELAY_32
                 		sbis TIFR2 ,  OCF2A
                 .endm
                 .macro STOP_DELAY_32
                 		sts TCCR2B , CONST00
                 .endm
                 
                 .macro INI_DELAY
                 	sts TCCR3A , CONST00
                 	sts TCCR3B , CONST00
                 	sts TCCR3C , CONST00
                 	sts TIMSK3 , CONST00
                 .endm
                 
                 .macro START_DELAY 
                 	out TIFR3 , CONSTFF
                 	sts TCNT3H , CONST00
                 	sts TCNT3L , CONST00
                 	cpi TEMP , 0
                 	brne $ma1 
                 	ldi TEMP , 6*KOEFF
                 	rjmp $mae	
                 $ma1:
                 	cpi TEMP , 1
                 	brne $ma2 
                 	ldi TEMP , 12*KOEFF
                 	rjmp $mae	
                 $ma2:
                    	cpi TEMP , 2
                 	brne $ma3 
                 	ldi TEMP , 20*KOEFF
                 	rjmp $mae	
                 $ma3:
                 	ldi TEMP , 30*KOEFF
                 $mae:	
                 	sts OCR3AH , TEMP
                 	sts OCR3AL , CONST00
                 	ldi TEMP , ( 1 << WGM12 ) | ( 1 << CS11 ) | ( 1 << CS10 )  
                 	sts TCCR3B , TEMP
                 .endm
                 .macro CHECK_DELAY
                 	sbis TIFR3 , OCF3A
                 .endm
                 .macro STOP_DELAY
                 	sts TCCR3B , CONST00
                 .endm
                 
                 .macro INI_CAPTURE
                 		ldi TEMP , 0x80
                 		out ACSR , TEMP
                 		out C1SR , TEMP
                 		sts  TCCR3A , CONST00
                 		sts  TCCR3B , CONST00
                 		sts  TCCR3C , CONST00
                 		sts  TIMSK3 , CONST00 
                 .endm
                 
                 .macro START_CAPTURE
                 		ldi TEMP , 0x02
                 		sts TCCR3B , TEMP
                 .endm
                 
                 .macro STOP_CAPTURE
                 		sts TCCR3B , CONST00
                 .endm
                 
                 .macro START_IP
                 	sts TCCR1B , CONST00
                 	sts TCCR1A , CONST00
                 	sts TCNT1H , CONSTFF
                 	sts TCNT1L , TEMP
                 	out TIFR1 , CONSTFF
                 	ldi TEMP , ( 1 << CS12 ) | ( 1 << CS11 ) 
                 	sts TCCR1B , TEMP
                 
                 .endm
                 .macro CHECK_IP
                 		sbis TIFR1 , TOV1
                 .endm
                 .macro STOP_IP
                 	sts TCCR1B , CONST00
                 .endm
                 
                 .equ PULSE =  8
                 .equ MED_PULSE = PULSE * 5 / 2
                 .equ LONG_PULSE = PULSE * 7 / 2 
                 .equ KOEFF = 1
                 
                 .listmac
                 
                 ;.macro READPULSE 
                 ;$m1:  
                 ;	   sbis   TIFR3, ICF3     // (1/2) skip next instruction if timer input capture seen
                 ;      rjmp   $m1           // (2)   wait more 
                 ; 	   lds     TEMP , ICR3L     // (2)   get time of input capture (ICR1L, lower 8 bits only)
                 ; 	   sbi     TIFR3, ICF3    // (2)   clear input capture flag
                 ;  	   mov     CURR_CAPT, TEMP     // (1)   calculate time since previous capture...
                 ;       sub     CURR_CAPT, OLD_CAPT      // (1)   ...into r22
                 ;       mov     OLD_CAPT, TEMP      // (1)   set r18 to time of current capture
                 ;.endm
                 
                 
                 
                 .macro WAIT_SHIFT_R
                 				ldi XL, low(@0  )
                 				ldi XH, high(@0 ) 
                 				sbrs FLAGS , S_D_R
                 				rjmp _start_state	
                 				andi  FLAGS , ~( 1 << S_D_R )
                 .endm
                 
                 .macro WAIT_SYNC_A1
                 				ldi XL, low(@0  )
                 				ldi XH, high(@0 )
                 				sbrs FLAGS , SYNC
                 				rjmp _start_state	
                 				andi  FLAGS , ~(( 1 << SYNC ) | (1 << S_D_R ))
                 ;				ldi TEMP , 0xA1
                 ;				cpse TEMP_D_REG ,  TEMP 
                 ;				rjmp _start_state
                 
                 .endm
                 
                 
                 .macro STORE  ;   
                 		lsl     @1          // (1)   shift received data
                 .if @0 != 0
                 		ori     @1 , 1        // (1)   store "1" bit
                 
                  		cpi @1 ,  0xA1
                 		brne $sm5
                 		cpi @2 ,  0x0A 
                 		brne $sm6
                 		ori FLAGS , ( 1 << SYNC )
                 		rjmp $sm7
                 $sm5:	  
                 .else
                 ;		sbrs FLAGS , READ_TR
                 ;			rjmp $sm6
                 ;		cpi @1 ,  0xC2
                 ;		brne $sm6
                 ;		cpi @2 ,  0x14 
                 ;		brne $sm6
                 ;		ori FLAGS , ( 1 << SYNC )
                 ;		rjmp $sm7
                 .endif
                 $sm6:	  
                 		dec    SHIFT_COUNT    // (1)   decrement bit counter
                 		brne    $sm8          // (1/2) skip if bit counter >0
                 $sm7:      
                 		ldi SHIFT_COUNT , 16
                 		mov TEMP_D_REG  , @1  // (2)   store received data byte
                 		ori FLAGS , (1 << S_D_R )
                 		CALC_CRC TEMP_D_REG
                 $sm8:
                 	
                 .endm
                 
                 .macro  READ_BYTE 
                 		sbis   TIFR3, ICF3     // (1/2) skip next instruction if timer input capture seen
                 			rjmp   $rdend           // (2)   wait more 
                 		lds     TEMP , ICR3L     // (2)   get time of input capture (ICR1L, lower 8 bits only)
                  		sbi     TIFR3, ICF3    // (2)   clear input capture flag
                  		mov     CURR_CAPT, TEMP     // (1)   calculate time since previous capture...
                 		sub     CURR_CAPT, OLD_CAPT      // (1)   ...into r22
                 		mov     OLD_CAPT, TEMP      // (1)   set r18 to time of current capture
                 	
                   	    cpi     CURR_CAPT, LONG_PULSE		
                         brsh    $rdl				
                         cpi     CURR_CAPT, MED_PULSE	
                         brlo    $rds				
                 		mov		TEMP , SHIFT_REG
                 		mov		SHIFT_REG , SHIFT_REG_S
                 		mov		SHIFT_REG_S , TEMP
                 		rjmp    $rdm
                 $rdl:		
                 		STORE 0 , SHIFT_REG , SHIFT_REG_S
                 $rdm:	    
                 		STORE 0 , SHIFT_REG_S , SHIFT_REG	
                 $rds:
                         STORE 0 , SHIFT_REG , SHIFT_REG_S
                 		STORE 1	, SHIFT_REG_S , SHIFT_REG			
                 $rdend:
                 .endm   
                 
                 
                  .macro INI_CRC
                 	ldi TEMP , low(0xCDB4)
                 	mov CRC_L , TEMP
                 	ldi TEMP , high(0xCDB4)
                 	mov CRC_H , TEMP 
                 .endm 
                 .macro CALC_CRC
                 	mov YL , @0
                 	eor YL , CRC_H
                 	ldi YH , high( 2 * crchi ) + 0x40
                     ld CRC_H , Y
                 	eor CRC_H , CRC_L
                 	dec YH
                     ld CRC_L , Y
                 .endm
                 
                 
                 .if OLD_WRITE == 1
                 .else
                 .equ BIT_COUNT = 4
                 .endif
                 
                 
                 ;.macro OUT_BIT
                 ;$ms0:	
                 ;		lds TEMP1 , UCSRA 
                 ;		sbrs TEMP1 ,  UDRE
                 ;			rjmp $ms0 
                 ;		sts UDR , @0
                 ;.endm
                 
                 .macro OUT_BIT_
                 $ms0:	
                 		lds TEMP1 , UCSRA 
                 		sbrs TEMP1 ,  UDRE
                 			rjmp _end_state 
                 		sts UDR , @0
                 		dec SHIFT_COUNT 
                 		brne @1		 
                 .endm
                 
                 
                 ;.macro PREV_WRITE_DATA
                 ;.if OLD_WRITE == 1
                 ;		ldi SHIFT_COUNT , 8
                 ;.else
                 ;		ldi SHIFT_COUNT , 4
                 ;.endif
                 ;.endm
                 
                 .macro WRITE_DATA
                 .if OLD_WRITE == 1
                 mw0:	
                 		lsl TEMP_D_REG
                 		brcc mw1
                 		
                 		ori SHIFT_REG_S ,  1 
                 		ldi SHIFT_REG , ( 1 )
                 		rjmp mw2
                 mw1:
                 		ldi SHIFT_REG , 0x0
                 		sbrs SHIFT_REG_S , 0
                 		ldi SHIFT_REG , (1 << 4 )
                 		andi SHIFT_REG_S , ~( 1 )       
                 mw2:
                 .else
                 mw0:		
                 		lsl TEMP_D_REG
                 		rol SHIFT_REG_S
                 		lsl TEMP_D_REG
                 		rol SHIFT_REG_S
                 		andi SHIFT_REG_S , 0b00000111
                 		ldi YH , high( MFM_table * 2 ) + 0x40
                 		ldi YL , low( MFM_table  * 2 )
                 		add YL , SHIFT_REG_S
                 		adc YH , CONST00
                 		ld  SHIFT_REG , Y
                 .endif
                 .endm
                 
                 
                 ;.macro WRITE_SYNC
                 ;		ld  SHIFT_REG , Y+
                 ;.endm
                  .include "hardware.inc"
                 
                 .equ	TR00 = 0
                 .macro INI_TR00
                 	cbi DDRD , TR00
                 	cbi PORTD , TR00
                 .endm
                 .macro CHECK_TR00
                 	sbic PIND , TR00
                 .endm
                 
                 
                 .equ CPRDY = 1
                 .macro INI_CPRDY
                         cbi DDRD , CPRDY
                 		cbi PORTD , CPRDY
                 .endm 
                 .macro CHECK_CPRDY
                 		sbic PIND , CPRDY	
                 .endm
                 
                 
                 .equ	HLD = 3
                 .macro INI_HLD
                 	sbi DDRD , HLD
                 	cbi PORTD , HLD
                 .endm
                 .macro SET_HLD
                 	sbi PORTD , HLD
                 .endm
                 .macro RES_HLD
                 	cbi PORTD , HLD
                 .endm
                 
                 .equ	IP = 5
                 .macro INI_IP
                 	cbi DDRD , IP
                 	cbi PORTD , IP 
                 .endm
                 .macro CHECK_IP_
                 	sbic PIND , IP
                 .endm
                 
                 
                 .equ	DRQ = 7
                 .macro INI_DRQ
                 	sbi DDRD , DRQ
                 	cbi PORTD , DRQ
                 .endm
                 .macro SET_DRQ
                 ;	sbi PORTD , DRQ
                 	cbi DDRD , DRQ
                 .endm
                 .macro RES_DRQ
                 ;	cbi PORTD , DRQ
                 	sbi DDRD , DRQ
                 .endm
                 .macro CHECK_DRQ
                     in TEMP , PIND
                     sbrs TEMP , DRQ
                 .endm
                 
                 
                 .equ	STEP = 0
                 .macro INI_STEP
                 	sbi DDRC , STEP
                 	cbi PORTC , STEP
                 .endm
                 .macro SET_STEP
                 	sbi PORTC , STEP
                 .endm
                 .macro RES_STEP
                 	cbi PORTC , STEP
                 .endm
                 
                 .equ	DIR = 1
                 .macro INI_DIR
                 	sbi DDRC , DIR
                 	cbi PORTC , DIR
                 .endm
                 .macro SET_DIR
                 	sbi PORTC , DIR
                 .endm
                 .macro RES_DIR
                 	cbi PORTC , DIR
                 .endm
                 .macro CHECK_DIR
                 	sbic PINC , DIR
                 .endm
                 
                 
                 .equ	 WG = 0
                 .macro INI_WG
                 	sbi DDRE , WG
                 	cbi PORTE , WG
                 .endm
                 .macro SET_WG
                 	sbi PORTE , WG
                 .endm
                 .macro RES_WG
                 	cbi PORTE , WG
                 .endm
                 
                 .equ    INTRQ = 1
                 .macro INI_INTRQ
                 	sbi DDRE , INTRQ
                 	cbi PORTE , INTRQ
                 .endm
                 .macro SET_INTRQ
                 ;	sbi PORTE , INTRQ
                     cbi DDRE , INTRQ
                 .endm
                 .macro RES_INTRQ
                 ;	cbi PORTE , INTRQ
                 	sbi DDRE , INTRQ
                 .endm
                 
                 
                 .equ WRPT = 2
                 .macro INI_WRPT
                 		cbi DDRE , WRPT
                 		cbi PORTE , WRPT
                 .endm
                 .macro CHECK_WRPT
                 		sbic PINE , WRPT
                 .endm
                 
                 .equ CLEAR = 3
                 .macro INI_CLR
                 	cbi DDRE , CLEAR
                 	cbi PORTE , CLEAR
                 .endm
                 .macro CHECK_CLR
                 	sbis PINE , CLEAR
                 .endm
                 
                 .equ    HRDY = 5
                 .macro INI_HRDY
                 	cbi DDRE , HRDY
                 	cbi PORTE , HRDY 
                 .endm
                 .macro CHECK_HRDY
                 	sbis PINE , HRDY
                 .endm
                 
                 .equ    WF_DE = 6
                 .macro INI_WF_DE
                 	cbi DDRE , WF_DE
                 	sbi PORTE , WF_DE 
                 .endm
                 
                 .macro SET_WF_DE
                     cbi DDRE , WF_DE
                 	sbi PORTE , WF_DE
                 .endm
                 .macro RES_WF_DE
                 	sbi DDRE , WF_DE
                 	cbi PORTE , WF_DE
                 .endm
                 
                 .macro CHECK_WF_DE
                 	sbic PINE , WF_DE
                 .endm
                 
                 
                 
                 .equ TR43 = 1
                 .macro INI_TR43
                 ;		sbi DDRE , TR43
                 ;		cbi PORTE , TR43
                 .endm
                 .macro SET_TR43
                 ;		cbi PORTE , TR43
                 .endm
                 .macro RES_TR43
                 ;		cbi PORTE , TR43
                 .endm
                 
                 
                 .macro INI_WRITE
                 .if OLD_WRITE == 1
                 		ldi TEMP , ( 1 << UMSEL1 ) | ( 1 << UMSEL0 )
                 		sts UCSRC , TEMP
                 		ldi TEMP , 7
                 		sts UBRRH , CONST00
                 		sts UBRRL , TEMP
                 		
                 .else
                 		ldi TEMP , ( 1 << UMSEL1 ) ;| ( 1 << UCPOL )
                 		sts UCSRC , TEMP
                 .endif
                 		sts UCSRA , CONST00
                 		lds TEMP , PMX0
                 		ori TEMP , (1 << WCE )
                 		sts PMX0  , TEMP
                 		ori TEMP , ( 1 << TXD6 )
                 		sts PMX0 , TEMP 
                 
                 .endm
                 
                 .macro START_WRITE
                 		ldi TEMP , ( 1 << TXEN )
                 		sts UCSRB , TEMP
                 .endm
                 
                 .macro STOP_WRITE
                 $msw0:	
                 		lds TEMP1 , UCSRA 
                 		sbrs TEMP1 ,  UDRE
                 			rjmp $msw0
                 		sts UCSRB , CONST00
                 .endm
                 .macro STOP_WRITER
                 		sts UCSRB , CONST00
                 .endm
                 
                 
                 
                  
                    
                  .org 0x0000
000000 c03b      	rjmp _reset
                  .org INT0addr
                 ;	movw TEMP_ZL , ZL
000002 b62f      	in SREG_TEMP ,SREG
                 ;	ldi ZH , 0x01
000003 b1e6      	in ZL , PEREHOD
000004 73ec      	andi ZL , 0b00111100
                 ;	nop						;
                 ;	nop	`					;	
                 ;	nop						;	
                 ;	nop						;  ðàáîòàåò â íîðì ðåæèìå 16 òàêòîâ 
                 ;	nop						;
000005 9409      	ijmp
                 ;.org WDTaddr
                 ;	rjmp _reset
                  .org INT_VECTORS_SIZE
                 
                 
                  _reset:
                 		
00003c 94f8      	cli
00003d 2400      	clr CONST00
00003e e108      	ldi TEMP ,( 1 << WDCE ) |  ( 1 << WDE )
00003f 9300 0060 	sts WDTCSR , TEMP
000041 e000      	ldi TEMP , ( 0 << WDE )
000042 9200 0060 	sts WDTCSR , CONST00
                 
000044 ef0f      	ser TEMP
000045 2e10      	mov CONSTFF , TEMP
                 	
000046 e800      	ldi TEMP , 0x80
000047 9300 00f2 	sts PMCR , TEMP
000049 e001      	ldi TEMP , 1
00004a 9300 00f2 	sts PMCR , TEMP
                 	
                 	
00004c e800      	ldi TEMP , 0x80 
00004d 9300 0061 	sts CLKPR , TEMP
00004f 9200 0061 	sts CLKPR , CONST00
000051 0000      	nop
000052 0000      	nop
000053 0000      	nop
                 
                 
000054 b804      	out DDRB , CONST00
000055 b805      	out PORTB , CONST00
                 	
000056 e003      	ldi TEMP , ( 1<<STEP) | ( 1 << DIR )
000057 b907      	out DDRC ,TEMP
000058 b808      	out PORTC , CONST00 
                 	
000059 e400      	ldi TEMP ,  ( 1 << 6 )
                 
00005a b90a      	out DDRD , TEMP
                 	;out PORTD , CONST00
                 
00005b 989c      	cbi DDRF , 4
00005c 9aa4      	sbi PORTF , 4
                 	
00005d 9200 007e   	sts DIDR0 , CONST00		
                 	;=========================================================
                 	// init stack pointer 0x45F
00005f ef0f      	ldi	TEMP,low(RAMEND)
000060 bf0d      	out	SPL,TEMP
000061 e008      	ldi	TEMP,high(RAMEND)
000062 bf0e      	out	SPH,TEMP
                 	
000063 e0f1      	ldi ZH , 0x01
                 
000064 e002      	ldi TEMP , ( 1 << ISC01 )
000065 9300 0069 	sts EICRA , TEMP
000067 e001      	ldi TEMP , ( 1 << INT0 )
000068 bb0d      	out EIMSK , TEMP 
                 
000069 b704      	in TEMP , MCUSR
00006a 6800      	ori TEMP , ( 1 << 7 )
00006b bf04      	out MCUSR , TEMP
00006c bf04      	out MCUSR , TEMP
                 
00006d 9100 00ee 	lds TEMP , PMX0
00006f 6800      	ori TEMP , (1 << WCE )
000070 9300 00ee 	sts PMX0  , TEMP
000072 6002      	ori TEMP , ( 1 << TXD6 )
000073 9300 00ee 	sts PMX0 , TEMP 
                 
000075 9100 00f0 	lds TEMP , PMX2
000077 6800      	ori TEMP , (1 << WCE )
000078 9300 00f0 	sts PMX2  , TEMP
00007a 6002      	ori TEMP , ( 1 << E6EN )
00007b 9300 00f0 	sts PMX2 , TEMP 
                 
                 
                 
                 .if DEBUG_ == 1
                 .endif
                 
                 _warm_start:
                 		
                +
00007d 9200 0090+sts TCCR3A , CONST00
00007f 9200 0091+sts TCCR3B , CONST00
000081 9200 0092+sts TCCR3C , CONST00
000083 9200 0071+sts TIMSK3 , CONST00
                 	INI_DELAY
                +
000085 9200 00b0+sts TCCR2A , CONST00
000087 9200 00b1+sts TCCR2B , CONST00
000089 9200 0070+sts TIMSK2 , CONST00
                 	INI_DELAY_32
                +
00008b 9a69     +sbi DDRE , INTRQ
00008c 9871     +cbi PORTE , INTRQ
                 	INI_INTRQ
                +
00008d 9a57     +sbi DDRD , DRQ
00008e 985f     +cbi PORTD , DRQ
                 	INI_DRQ
                +
00008f 9850     +cbi DDRD , TR00
000090 9858     +cbi PORTD , TR00
                 	INI_TR00
                +
000091 9855     +cbi DDRD , IP
000092 985d     +cbi PORTD , IP
                 	INI_IP
                +
000093 9a53     +sbi DDRD , HLD
000094 985b     +cbi PORTD , HLD
                 	INI_HLD
                +
000095 9a68     +sbi DDRE , WG
000096 9870     +cbi PORTE , WG
                 	INI_WG
                +
000097 9a39     +sbi DDRC , DIR
000098 9841     +cbi PORTC , DIR
                 	INI_DIR
                +
000099 9a38     +sbi DDRC , STEP
00009a 9840     +cbi PORTC , STEP
                 	INI_STEP
                +
00009b 986b     +cbi DDRE , CLEAR
00009c 9873     +cbi PORTE , CLEAR
                 	INI_CLR
                +
00009d 986d     +cbi DDRE , HRDY
00009e 9875     +cbi PORTE , HRDY
                 	INI_HRDY
                +
00009f 9851     +cbi DDRD , CPRDY
0000a0 9859     +cbi PORTD , CPRDY
                 	INI_CPRDY
                +
                +
                +
                 	INI_TR43
                +
0000a1 986a     +cbi DDRE , WRPT
0000a2 9872     +cbi PORTE , WRPT
                 	INI_WRPT
                +
0000a3 e800     +ldi TEMP , 0x80
0000a4 bf00     +out ACSR , TEMP
0000a5 b90f     +out C1SR , TEMP
0000a6 9200 0090+sts TCCR3A , CONST00
0000a8 9200 0091+sts TCCR3B , CONST00
0000aa 9200 0092+sts TCCR3C , CONST00
0000ac 9200 0071+sts TIMSK3 , CONST00
                 	INI_CAPTURE
                 
                +
                +.if OLD_WRITE == 1
                +ldi TEMP , ( 1 << UMSEL1 ) | ( 1 << UMSEL0 )
0000ae e800     +sts UCSRC , TEMP
0000af 9300 00c2+ldi TEMP , 7
                +sts UBRRH , CONST00
0000b1 9200 00c0+sts UBRRL , TEMP
0000b3 9100 00ee+
0000b5 6800     +.else 
0000b6 9300 00ee+ldi TEMP , ( 1 << UMSEL1 )
0000b8 6002     +sts UCSRC , TEMP
0000b9 9300 00ee+.endif 
                +sts UCSRA , CONST00
                 	INI_WRITE
                 	
0000bb e001      	ldi TEMP , ( 1 << INTF0 )
0000bc bb0c      	out EIFR , TEMP
0000bd 9478      	sei
                 
0000be c000      	rjmp _start
                 
                 
                 	_start:	
                 		
                +
0000bf 9870     +cbi PORTE , WG
                 		RES_WG
0000c0 2755      		clr FLAGS
0000c1 e003      		ldi TEMP , 0x03
0000c2 2ef0      		mov TEMP_CMD , TEMP
0000c3 6051      		ori FLAGS , ( 1  << NEW_CMD )
0000c4 2c51      		mov TR_REG  , CONSTFF
0000c5 ef0e      		ldi TEMP , 0xFE
0000c6 2e60      		mov SECT_REG , TEMP
0000c7 2477      		clr DAT_REG 
                +
0000c8 ef3f     +ser S_REG
                 		CLR_S_REG
                +
0000c9 9200 0081+sts TCCR1B , CONST00
                 		STOP_IP
                +
0000cb e6a0     +ldi XL , low ( _t0 )
0000cc e0b1     +ldi XH , high ( _t0 )
                 		STATE_M _t0
                 _start_1:
                +
0000cd 9b63     +sbis PINE , CLEAR
                 		CHECK_CLR
0000ce cffe      			rjmp _start_1
0000cf c4dd              rjmp _end_state
                 
                 
                 .org 0x100
                 	
                 ; rw = 00 a10=00
000100 0000      	nop
000101 0000      	nop
000102 0000      	nop
000103 c03d      	rjmp end_INT0
                 ; rw = 00 a10=01
000104 0000      	nop
000105 0000      	nop
000106 0000      	nop
000107 c039      	rjmp end_INT0
                 ; rw = 00 a10=10
000108 0000      	nop
000109 0000      	nop
00010a 0000      	nop
00010b c035      	rjmp end_INT0
                 ; rw = 00 a10=11
00010c 0000      	nop
00010d 0000      	nop
00010e 0000      	nop
00010f c031      	rjmp end_INT0
                 
                 ; rw = 01 a10 = 00
                 ;	out DIR_BUS , CONSTFF
000110 b934      	out DIR_BUS , S_REG
000111 0000      	nop
                 ;	out DATA_BUS , S_REG
                +
                +
000112 9a69     +sbi DDRE , INTRQ
                 	RES_INTRQ
000113 c02d      	rjmp end_INT0
                 ; rw = 01 a10 = 01
                 ;	out DIR_BUS , CONSTFF
000114 b854      	out DIR_BUS , TR_REG
000115 0000      	nop
                 ;	out DATA_BUS , TR_REG
000116 0000      	nop
000117 c029      	rjmp end_INT0
                 ; rw = 01 a10 = 10
                 ;	out DIR_BUS , CONSTFF
000118 b864      	out DIR_BUS , SECT_REG
000119 0000      	nop
                 ;	out DATA_BUS , SECT_REG
00011a 0000      	nop
00011b c025      	rjmp end_INT0
                 ; rw = 01 a10 = 11
                 ;	out DIR_BUS , CONSTFF
00011c b874      	out DIR_BUS , DAT_REG
00011d 0000      	nop
                 ;	out DATA_BUS , D_REG
                +
                +
00011e 9a57     +sbi DDRD , DRQ
                 	RES_DRQ
00011f c021      	rjmp end_INT0
                 
                 ; rw = 10 a10 = 00
000120 b0f3      	in TEMP_CMD , PIN_BUS
000121 6051      	ori FLAGS , ( 1 << NEW_CMD )
000122 0000      	nop	
000123 c01d      	rjmp end_INT0
                 ; rw = 10 a10 = 01
000124 b053      	in  TR_REG ,  PIN_BUS
000125 9450      	com TR_REG
                 ;	nop
000126 0000      	nop
000127 c019      	rjmp end_INT0
                 ; rw = 10 a10 = 10
000128 b063      	in   SECT_REG , PIN_BUS 
000129 9460      	com SECT_REG
                 ;	nop
00012a 0000      	nop
00012b c015      	rjmp end_INT0
                 ; rw = 10 a10 = 11
00012c b073      	in   DAT_REG ,  PIN_BUS
00012d 9470      	com DAT_REG
00012e 0000      	nop
                +
                +
00012f 9a57     +sbi DDRD , DRQ
                 	RES_DRQ
000130 c010       	rjmp end_INT0
                 
                 ; rw = 11 a10 = 00
000131 0000      	nop
000132 0000      	nop
000133 0000      	nop
000134 c00c      	rjmp end_INT0
                 ; rw = 11 a10 = 01
000135 0000      	nop
000136 0000      	nop
000137 0000      	nop
000138 c008      	rjmp end_INT0
                 ; rw = 11 a10 = 10
000139 0000      	nop
00013a 0000      	nop
00013b 0000      	nop
00013c c004      	rjmp end_INT0
                 ; rw = 11 a10 = 11
00013d 0000      	nop
00013e 0000      	nop
00013f 0000      	nop
000140 c000      	rjmp end_INT0
                 
                 end_INT0 :
000141 9b4a      		sbis PIND , 2
000142 cffe      		rjmp end_INT0
000143 b804      		out DDRB , CONST00
000144 b805      		out PORTB , CONST00
                 ;		movw ZL , TEMP_ZL
000145 be2f      		out SREG , SREG_TEMP
                 		
000146 9518      		reti
                  
                  
                 
                 .include "cmd_int.inc"	
                 
000147 6058      			ori FLAGS , ( 1 << CMD_1_TYPE )
                +
000148 e70f     +ldi TEMP , 127
000149 9300 00b3+sts OCR2A , TEMP
00014b e002     +ldi TEMP , 2
00014c 9300 00b0+sts TCCR2A , TEMP
00014e 9200 00b2+sts TCNT2 , CONST00
000150 ba17     +out TIFR2 , CONSTFF
000151 e001     +ldi TEMP , 1
000152 9300 00b1+sts TCCR2B , TEMP
                +
                 			START_DELAY_4
                 _break:
                +
000154 9200 00c1+sts UCSRB , CONST00
                 			STOP_WRITER
                +
000156 9200 0091+sts TCCR3B , CONST00
                 			STOP_CAPTURE
                +
000158 9200 0091+sts TCCR3B , CONST00
                 			STOP_DELAY
00015a 7e5a      			andi FLAGS , ~( (1 << NEW_CMD)  | (1 << READ_TR) | (1 << BREAK_IP ))
                +
00015b 6031     +ori S_REG , ( 1 << S_REG_BUSY )
                 			RES_S_REG_BIT  S_REG_BUSY
00015c e00f      			ldi TEMP , 0b00001111
                 
00015d 210f      			and TEMP , TEMP_CMD
00015e f009      			breq _t0
                +
                +
00015f 9869     +cbi DDRE , INTRQ
                 			SET_INTRQ
                 _t0:	
000160 ef01      			ldi TEMP , (-15)  
                +
000161 9200 0081+sts TCCR1B , CONST00
000163 9200 0080+sts TCCR1A , CONST00
000165 9210 0085+sts TCNT1H , CONSTFF
000167 9300 0084+sts TCNT1L , TEMP
000169 ba16     +out TIFR1 , CONSTFF
00016a e006     +ldi TEMP , ( 1 << CS12 ) | ( 1 << CS11 )
00016b 9300 0081+sts TCCR1B , TEMP
                +
                 			START_IP 
                +
00016d e7a0     +ldi XL , low ( _t0_0 )
00016e e0b1     +ldi XH , high ( _t0_0 )
00016f c43d     +rjmp _end_state
                 			STATE_E _t0_0
                 _t0_0:		
000170 9b5b      			sbis PORTD , HLD
000171 c005      				rjmp _t0_1
                +
000172 9bb0     +sbis TIFR1 , TOV1
                 			CHECK_IP
000173 c003      				rjmp _t0_1
                +
000174 985b     +cbi PORTD , HLD
                 			RES_HLD
                +
000175 986e     +cbi DDRE , WF_DE
000176 9a76     +sbi PORTE , WF_DE
                 			SET_WF_DE
                 			
                 _t0_1:		
                +
000177 e7a0     +ldi XL , low ( _t0_0 )
000178 e0b1     +ldi XH , high ( _t0_0 )
                 		STATE_M _t0_0
                 		
                +
000179 9b63     +sbis PINE , CLEAR
                 		CHECK_CLR
00017a cf02      			rjmp _warm_start
00017b ff50      		sbrs  FLAGS , NEW_CMD
00017c c439      			rjmp calc_ip
                 
00017d 2d0f      	    mov TEMP , TEMP_CMD
00017e 7f00      		andi TEMP , 0xF0
00017f 3d00      	    cpi TEMP , 0xD0
000180 f231      	    breq _break_
000181 7f5e      		andi FLAGS , ~( 1 << NEW_CMD )
000182 fef7      		sbrs TEMP_CMD , 7 
000183 c009      			rjmp _cmd_type_1
000184 7f57      	   	andi FLAGS , ~(1 << CMD_1_TYPE)
000185 fef6      		sbrs TEMP_CMD , 6
000186 c14d      			rjmp _cmd_type_2
                 	
000187 fef4      		sbrs TEMP_CMD , 4
000188 c451      			rjmp _cmd_type_3
                 	    
000189 fef3      		sbrs TEMP_CMD , 3
00018a c56e      			rjmp _cmd_type_4
                +
                +
00018b 9869     +cbi DDRE , INTRQ
                 		SET_INTRQ
00018c cfe3      		rjmp _t0_0
                 
                 _cmd_type_1:
00018d 6058      				ori FLAGS , (1 << CMD_1_TYPE)
                +
00018e e70f     +ldi TEMP , 127
00018f 9300 00b3+sts OCR2A , TEMP
000191 e002     +ldi TEMP , 2
000192 9300 00b0+sts TCCR2A , TEMP
000194 9200 00b2+sts TCNT2 , CONST00
000196 ba17     +out TIFR2 , CONSTFF
000197 e001     +ldi TEMP , 1
000198 9300 00b1+sts TCCR2B , TEMP
                +
                 				START_DELAY_4
                +
00019a ef3f     +ser S_REG
                 				CLR_S_REG
                 	_t1_s02:
                +
00019b 7f3e     +andi S_REG , ~ ( 1 << S_REG_BUSY )
                 				SET_S_REG_BIT  S_REG_BUSY 
                +
                +
00019c 9a57     +sbi DDRD , DRQ
                 				RES_DRQ
                +
                +
00019d 9a69     +sbi DDRE , INTRQ
                 				RES_INTRQ
                +
00019e eaa1     +ldi XL , low ( _t1_s03 )
00019f e0b1     +ldi XH , high ( _t1_s03 )
0001a0 c40c     +rjmp _end_state
                 				STATE_E _t1_s03
                 	_t1_s03:
                +
0001a1 eaa9     +ldi XL , low ( _t1_s04 )
0001a2 e0b1     +ldi XH , high ( _t1_s04 )
                 				STATE_M _t1_s04
0001a3 fef3      				sbrs TEMP_CMD , 3
0001a4 c408      				rjmp _end_state
                +
0001a5 9a5b     +sbi PORTD , HLD
                 				SET_HLD
                 ;				SET_S_REG_BIT   S_REG_HLD
                +
0001a6 eaad     +ldi XL , low ( _t1_s04_00 )
0001a7 e0b1     +ldi XH , high ( _t1_s04_00 )
0001a8 c404     +rjmp _end_state
                 				STATE_E _t1_s04_00
                 	_t1_s04:					
                +
0001a9 985b     +cbi PORTD , HLD
                 				RES_HLD
                 ;				RES_S_REG_BIT  S_REG_HLD
                +
0001aa eaad     +ldi XL , low ( _t1_s04_00 )
0001ab e0b1     +ldi XH , high ( _t1_s04_00 )
0001ac c400     +rjmp _end_state
                 				STATE_E _t1_s04_00
                 
                 	_t1_s04_00:
                 ;				INI_DELAY_1
                 ;				ldi TEMP , 16
                 ;				START_DELAY_1
                 ;				STATE_M _t1_s04_01
                 ;	_t1_s04_01:
                 ;				CHECK_DELAY_1
                 ;					rjmp _end_state
                 ;				STOP_DELAY_1
                 	_t1_s05:
                +
0001ad ebad     +ldi XL , low ( _t1_s07 )
0001ae e0b1     +ldi XH , high ( _t1_s07 )
                 				STATE_M _t1_s07
0001af fef6      				sbrs TEMP_CMD , 6
0001b0 c3fc      				rjmp _end_state
                 				
                +
0001b1 eba9     +ldi XL , low ( _t1_s06 )
0001b2 e0b1     +ldi XH , high ( _t1_s06 )
                 				STATE_M _t1_s06
0001b3 fef5      				sbrs TEMP_CMD , 5
0001b4 c3f8      				rjmp _end_state			
                +
0001b5 9841     +cbi PORTC , DIR
                 				RES_DIR
                +
0001b6 eca1     +ldi XL , low ( _t1_C )
0001b7 e0b1     +ldi XH , high ( _t1_C )
0001b8 c3f4     +rjmp _end_state
                 				STATE_E _t1_C
                 	_t1_s06:	
                +
0001b9 9a41     +sbi PORTC , DIR
                 				SET_DIR
                +
0001ba eca1     +ldi XL , low ( _t1_C )
0001bb e0b1     +ldi XH , high ( _t1_C )
0001bc c3f0     +rjmp _end_state
                 				STATE_E _t1_C
                 	_t1_s07:	
                +
0001bd eca8     +ldi XL , low ( _t1_s08 )
0001be e0b1     +ldi XH , high ( _t1_s08 )
                 				STATE_M _t1_s08
0001bf fef5      				sbrs TEMP_CMD , 5
0001c0 c3ec      				rjmp _end_state
                 	_t1_C:		
                +
0001c1 efa6     +ldi XL , low ( _t1_s17 )
0001c2 e0b1     +ldi XH , high ( _t1_s17 )
                 				STATE_M _t1_s17
0001c3 fef4      				sbrs TEMP_CMD , 4
0001c4 c3e8      				rjmp _end_state 
                +
0001c5 eeaa     +ldi XL , low ( _t1_s15 )
0001c6 e0b1     +ldi XH , high ( _t1_s15 )
0001c7 c3e5     +rjmp _end_state
                 				STATE_E _t1_s15
                 	_t1_s08:
                +
0001c8 eda7     +ldi XL , low ( _t1_s11 )
0001c9 e0b1     +ldi XH , high ( _t1_s11 )
                 				STATE_M _t1_s11
0001ca fcf4      				sbrc TEMP_CMD , 4
0001cb c3e1      		        rjmp _end_state
                +
0001cc ecaf     +ldi XL , low ( _t1_s09 )
0001cd e0b1     +ldi XH , high ( _t1_s09 )
0001ce c3de     +rjmp _end_state
                 				STATE_E _t1_s09
                 	_t1_s09:
0001cf 2c50      				mov TR_REG , CONST00
                +
0001d0 eda3     +ldi XL , low ( _t1_s10 )
0001d1 e0b1     +ldi XH , high ( _t1_s10 )
0001d2 c3da     +rjmp _end_state
                 				STATE_E _t1_s10
                 	_t1_s10:
0001d3 2c71      				mov DAT_REG , CONSTFF
                +
0001d4 eda7     +ldi XL , low ( _t1_s11 )
0001d5 e0b1     +ldi XH , high ( _t1_s11 )
0001d6 c3d6     +rjmp _end_state
                 				STATE_E _t1_s11
                 	_t1_s11:
0001d7 2d47      				mov TEMP_D_REG , DAT_REG
                +
0001d8 edab     +ldi XL , low ( _t1_s12 )
0001d9 e0b1     +ldi XH , high ( _t1_s12 )
0001da c3d2     +rjmp _end_state
                 				STATE_E _t1_s12
                 	_t1_s12:
0001db 1545      				cp TEMP_D_REG , TR_REG
0001dc f419      				brne _t1_s13
                +
0001dd e3a8     +ldi XL , low ( _t1_s21 )
0001de e0b2     +ldi XH , high ( _t1_s21 )
0001df c3cd     +rjmp _end_state
                 				STATE_E _t1_s21
                 	_t1_s13:
0001e0 1545      				cp TEMP_D_REG , TR_REG
0001e1 f420      				brsh _t1_s14
                +
0001e2 9a41     +sbi PORTC , DIR
                 				SET_DIR
                +
0001e3 eeaa     +ldi XL , low ( _t1_s15 )
0001e4 e0b1     +ldi XH , high ( _t1_s15 )
0001e5 c3c7     +rjmp _end_state
                 				STATE_E _t1_s15
                 	_t1_s14:
                +
0001e6 9841     +cbi PORTC , DIR
                 				RES_DIR
                +
0001e7 eeaa     +ldi XL , low ( _t1_s15 )
0001e8 e0b1     +ldi XH , high ( _t1_s15 )
0001e9 c3c3     +rjmp _end_state
                 				STATE_E _t1_s15
                 	_t1_s15:
                +
0001ea efa2     +ldi XL , low ( _t1_s16 )
0001eb e0b1     +ldi XH , high ( _t1_s16 )
                 				STATE_M _t1_s16
                +
0001ec 9931     +sbic PINC , DIR
                 				CHECK_DIR
0001ed c3bf      					rjmp _end_state
0001ee 9453      				inc TR_REG
                +
0001ef efa6     +ldi XL , low ( _t1_s17 )
0001f0 e0b1     +ldi XH , high ( _t1_s17 )
0001f1 c3bb     +rjmp _end_state
                 				STATE_E _t1_s17
                 	_t1_s16:
0001f2 945a      				dec TR_REG
                +
0001f3 efa6     +ldi XL , low ( _t1_s17 )
0001f4 e0b1     +ldi XH , high ( _t1_s17 )
0001f5 c3b7     +rjmp _end_state
                 				STATE_E _t1_s17
                 	_t1_s17:
                +
0001f6 e0a0     +ldi XL , low ( _t1_s18 )
0001f7 e0b2     +ldi XH , high ( _t1_s18 )
                 				STATE_M _t1_s18
                +
0001f8 9948     +sbic PIND , TR00
                 				CHECK_TR00
0001f9 c3b3      					rjmp _end_state
                +
0001fa 9931     +sbic PINC , DIR
                 				CHECK_DIR
0001fb c3b1      					rjmp _end_state
0001fc 2c51      				mov TR_REG , CONSTFF
                +
0001fd e3a8     +ldi XL , low ( _t1_s21 )
0001fe e0b2     +ldi XH , high ( _t1_s21 )
0001ff c3ad     +rjmp _end_state
                 				STATE_E _t1_s21
                 	_t1_s18:
                +
000200 e0a3     +ldi XL , low ( _t1_s18_0 )
000201 e0b2     +ldi XH , high ( _t1_s18_0 )
000202 c3aa     +rjmp _end_state
                 	           	STATE_E _t1_s18_0		
                 	_t1_s18_0: 
                +
000203 9a40     +sbi PORTC , STEP
                 				SET_STEP
                +
000204 e0a7     +ldi XL , low ( _t1_s18_1 )
000205 e0b2     +ldi XH , high ( _t1_s18_1 )
000206 c3a6     +rjmp _end_state
                 				STATE_E _t1_s18_1
                 	_t1_s18_1:			
                 ;				STATE_E _t1_s18_2
                 ;	_t1_s18_2:			
                 ;				STATE_E _t1_s18_3
                 ;	_t1_s18_3:			
                 ;				STATE_E _t1_s18_4
                 ;	_t1_s18_4:			
                +
000207 9840     +cbi PORTC , STEP
                 				RES_STEP			
                 		
000208 2d0f      				mov TEMP , TEMP_CMD
000209 7003      				andi TEMP , 0x3
                +
00020a ba18     +out TIFR3 , CONSTFF
00020b 9200 0095+sts TCNT3H , CONST00
00020d 9200 0094+sts TCNT3L , CONST00
00020f 3000     +cpi TEMP , 0
000210 f411     +brne $ ma1
000211 e006     +ldi TEMP , 6 * KOEFF
000212 c009     +rjmp $ mae
                +$ ma1 :
000213 3001     +cpi TEMP , 1
000214 f411     +brne $ ma2
000215 e00c     +ldi TEMP , 12 * KOEFF
000216 c005     +rjmp $ mae
                +$ ma2 :
000217 3002     +cpi TEMP , 2
000218 f411     +brne $ ma3
000219 e104     +ldi TEMP , 20 * KOEFF
00021a c001     +rjmp $ mae
                +$ ma3 :
00021b e10e     +ldi TEMP , 30 * KOEFF
                +$ mae :
00021c 9300 0099+sts OCR3AH , TEMP
00021e 9200 0098+sts OCR3AL , CONST00
000220 e00b     +ldi TEMP , ( 1 << WGM12 ) | ( 1 << CS11 ) | ( 1 << CS10 )
000221 9300 0091+sts TCCR3B , TEMP
                 				START_DELAY 
                +
000223 e2a6     +ldi XL , low ( _t1_s19 )
000224 e0b2     +ldi XH , high ( _t1_s19 )
000225 c387     +rjmp _end_state
                 				STATE_E _t1_s19
                 	_t1_s19:
                +
000226 e2a6     +ldi XL , low ( _t1_s19 )
000227 e0b2     +ldi XH , high ( _t1_s19 )
                 				STATE_M _t1_s19
                +
000228 9bc1     +sbis TIFR3 , OCF3A
                 				CHECK_DELAY
000229 c383      					rjmp _end_state
                +
00022a 9200 0091+sts TCCR3B , CONST00
                 				STOP_DELAY
                +
00022c e2af     +ldi XL , low ( _t1_s20 )
00022d e0b2     +ldi XH , high ( _t1_s20 )
00022e c37e     +rjmp _end_state
                 				STATE_E _t1_s20
                 	_t1_s20:
                +
00022f e3a8     +ldi XL , low ( _t1_s21 )
000230 e0b2     +ldi XH , high ( _t1_s21 )
                 				STATE_M _t1_s21
000231 fcf6      				sbrc TEMP_CMD , 6
000232 c37a      					rjmp _end_state
000233 fcf5      				sbrc TEMP_CMD , 5
000234 c378      					rjmp _end_state
                +
000235 eda7     +ldi XL , low ( _t1_s11 )
000236 e0b1     +ldi XH , high ( _t1_s11 )
000237 c375     +rjmp _end_state
                 				STATE_E _t1_s11
                 
                 	_t1_s21:
                +
000238 ecaa     +ldi XL , low ( _t1_s30 )
000239 e0b2     +ldi XH , high ( _t1_s30 )
                 				STATE_M _t1_s30
00023a fef2      				sbrs TEMP_CMD , 2
00023b c371      					rjmp _end_state
                +
00023c e3af     +ldi XL , low ( _t1_s22 )
00023d e0b2     +ldi XH , high ( _t1_s22 )
00023e c36e     +rjmp _end_state
                 				STATE_E _t1_s22
                 	_t1_s22:
                +
00023f 9a5b     +sbi PORTD , HLD
                 				SET_HLD
                 ;				SET_S_REG_BIT  S_REG_HLD
000240 e001      				ldi TEMP,0x01
                +
000241 ba18     +out TIFR3 , CONSTFF
000242 9200 0095+sts TCNT3H , CONST00
000244 9200 0094+sts TCNT3L , CONST00
000246 3000     +cpi TEMP , 0
000247 f411     +brne $ ma1
000248 e006     +ldi TEMP , 6 * KOEFF
000249 c009     +rjmp $ mae
                +$ ma1 :
00024a 3001     +cpi TEMP , 1
00024b f411     +brne $ ma2
00024c e00c     +ldi TEMP , 12 * KOEFF
00024d c005     +rjmp $ mae
                +$ ma2 :
00024e 3002     +cpi TEMP , 2
00024f f411     +brne $ ma3
000250 e104     +ldi TEMP , 20 * KOEFF
000251 c001     +rjmp $ mae
                +$ ma3 :
000252 e10e     +ldi TEMP , 30 * KOEFF
                +$ mae :
000253 9300 0099+sts OCR3AH , TEMP
000255 9200 0098+sts OCR3AL , CONST00
000257 e00b     +ldi TEMP , ( 1 << WGM12 ) | ( 1 << CS11 ) | ( 1 << CS10 )
000258 9300 0091+sts TCCR3B , TEMP
                 				START_DELAY 
                +
00025a e5ad     +ldi XL , low ( _t1_s23 )
00025b e0b2     +ldi XH , high ( _t1_s23 )
00025c c350     +rjmp _end_state
                 				STATE_E _t1_s23
                 	_t1_s23:
                +
00025d e5ad     +ldi XL , low ( _t1_s23 )
00025e e0b2     +ldi XH , high ( _t1_s23 )
                 				STATE_M _t1_s23
                +
00025f 9bc1     +sbis TIFR3 , OCF3A
                 				CHECK_DELAY
000260 c34c      					rjmp _end_state
                +
000261 9200 0091+sts TCCR3B , CONST00
                 				STOP_DELAY
                +
000263 e6a6     +ldi XL , low ( _t1_s24 )
000264 e0b2     +ldi XH , high ( _t1_s24 )
000265 c347     +rjmp _end_state
                 				STATE_E _t1_s24
                 	_t1_s24:
                +
000266 e6a6     +ldi XL , low ( _t1_s24 )
000267 e0b2     +ldi XH , high ( _t1_s24 )
                 				STATE_M _t1_s24
                +
000268 9b65     +sbis PINE , HRDY
                 				CHECK_HRDY
000269 c343      					rjmp _end_state
00026a ef07      				ldi TEMP , (-9 )
                +
00026b 9a6e     +sbi DDRE , WF_DE
00026c 9876     +cbi PORTE , WF_DE
                 				RES_WF_DE
                +
00026d 9200 0081+sts TCCR1B , CONST00
00026f 9200 0080+sts TCCR1A , CONST00
000271 9210 0085+sts TCNT1H , CONSTFF
000273 9300 0084+sts TCNT1L , TEMP
000275 ba16     +out TIFR1 , CONSTFF
000276 e006     +ldi TEMP , ( 1 << CS12 ) | ( 1 << CS11 )
000277 9300 0081+sts TCCR1B , TEMP
                +
                 				START_IP 
                +
000279 e002     +ldi TEMP , 0x02
00027a 9300 0091+sts TCCR3B , TEMP
                 				START_CAPTURE
                +
00027c e7af     +ldi XL , low ( _t1_s25 )
00027d e0b2     +ldi XH , high ( _t1_s25 )
00027e c32e     +rjmp _end_state
                 				STATE_E _t1_s25
                 	
                 	_t1_s25:
                 				
                +
00027f e8a7     +ldi XL , low ( _t1_s26 )
000280 e0b2     +ldi XH , high ( _t1_s26 )
                 				STATE_M _t1_s26
                +
000281 9bb0     +sbis TIFR1 , TOV1
                 				CHECK_IP 
000282 c32a      					rjmp _end_state
                +
000283 7e3f     +andi S_REG , ~ ( 1 << S_REG_SEEK_ERR )
                 				SET_S_REG_BIT  S_REG_SEEK_ERR
                +
000284 ecaa     +ldi XL , low ( _t1_s30 )
000285 e0b2     +ldi XH , high ( _t1_s30 )
000286 c326     +rjmp _end_state
                 				STATE_E _t1_s30
                 
                 	_t1_s26:    
                +
000287 e7af     +ldi XL , low ( _t1_s25 )
000288 e0b2     +ldi XH , high ( _t1_s25 )
                 	            STATE_M _t1_s25
                +
000289 e7af     +ldi XL , low ( _t1_s25 )
00028a e0b2     +ldi XH , high ( _t1_s25 )
00028b ff56     +sbrs FLAGS , SYNC
00028c c2d5     +rjmp _start_state
00028d 7b5d     +andi FLAGS , ~ ( ( 1 << SYNC ) | ( 1 << S_D_R ) )
                +
                +
                +
                +
                 				WAIT_SYNC_A1  _t1_s25
                +
00028e eb04     +ldi TEMP , low ( 0xCDB4 )
00028f 2e80     +mov CRC_L , TEMP
000290 ec0d     +ldi TEMP , high ( 0xCDB4 )
000291 2e90     +mov CRC_H , TEMP
                 				INI_CRC
                 	_t1_s26_1:
                +
000292 e9a2     +ldi XL , low ( _t1_s26_1 )
000293 e0b2     +ldi XH , high ( _t1_s26_1 )
000294 ff51     +sbrs FLAGS , S_D_R
000295 c2cc     +rjmp _start_state
000296 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R 	_t1_s26_1
000297 3f4e      				cpi TEMP_D_REG  , 0xFE
000298 f019      				breq _t1_s27
                +
000299 e7af     +ldi XL , low ( _t1_s25 )
00029a e0b2     +ldi XH , high ( _t1_s25 )
00029b c311     +rjmp _end_state
                 				STATE_E _t1_s25
                 	_t1_s27:
                +
00029c e9ac     +ldi XL , low ( _t1_s27 )
00029d e0b2     +ldi XH , high ( _t1_s27 )
00029e ff51     +sbrs FLAGS , S_D_R
00029f c2c2     +rjmp _start_state
0002a0 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R 	_t1_s27
0002a1 9540      				com TEMP_D_REG
0002a2 1654      				cp TR_REG , TEMP_D_REG
0002a3 f019      				breq	_t1_s28
                +
0002a4 e7af     +ldi XL , low ( _t1_s25 )
0002a5 e0b2     +ldi XH , high ( _t1_s25 )
0002a6 c306     +rjmp _end_state
                 				STATE_E _t1_s25
                 	_t1_s28:
                +
0002a7 eaa7     +ldi XL , low ( _t1_s28 )
0002a8 e0b2     +ldi XH , high ( _t1_s28 )
0002a9 ff51     +sbrs FLAGS , S_D_R
0002aa c2b7     +rjmp _start_state
0002ab 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R  _t1_s28
                 	_t1_s28_1:			
                +
0002ac eaac     +ldi XL , low ( _t1_s28_1 )
0002ad e0b2     +ldi XH , high ( _t1_s28_1 )
0002ae ff51     +sbrs FLAGS , S_D_R
0002af c2b2     +rjmp _start_state
0002b0 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R  _t1_s28_1
                 	_t1_s28_2:			
                +
0002b1 eba1     +ldi XL , low ( _t1_s28_2 )
0002b2 e0b2     +ldi XH , high ( _t1_s28_2 )
0002b3 ff51     +sbrs FLAGS , S_D_R
0002b4 c2ad     +rjmp _start_state
0002b5 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R  _t1_s28_2
                 	_t1_s28_3:			
                +
0002b6 eba6     +ldi XL , low ( _t1_s28_3 )
0002b7 e0b2     +ldi XH , high ( _t1_s28_3 )
0002b8 ff51     +sbrs FLAGS , S_D_R
0002b9 c2a8     +rjmp _start_state
0002ba 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R _t1_s28_3
                 	_t1_s28_4:			
                +
0002bb ebab     +ldi XL , low ( _t1_s28_4 )
0002bc e0b2     +ldi XH , high ( _t1_s28_4 )
0002bd ff51     +sbrs FLAGS , S_D_R
0002be c2a3     +rjmp _start_state
0002bf 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R _t1_s28_4
0002c0 2898      				or CRC_H , CRC_L
0002c1 f021      				breq _t1_s29
                 ;				STATE_E _t1_s28_5
                     _t1_s28_5:
                +
0002c2 7f37     +andi S_REG , ~ ( 1 << S_REG_CRC_ERR )
                 	            SET_S_REG_BIT   S_REG_CRC_ERR 
                +
0002c3 e7af     +ldi XL , low ( _t1_s25 )
0002c4 e0b2     +ldi XH , high ( _t1_s25 )
0002c5 c2e7     +rjmp _end_state
                 				STATE_E _t1_s25
                 	_t1_s29:
                +
0002c6 6038     +ori S_REG , ( 1 << S_REG_CRC_ERR )
                 				RES_S_REG_BIT  S_REG_CRC_ERR
                +
0002c7 ecaa     +ldi XL , low ( _t1_s30 )
0002c8 e0b2     +ldi XH , high ( _t1_s30 )
0002c9 c2e3     +rjmp _end_state
                 				STATE_E _t1_s30
                 	_t1_s30:
                +
0002ca 986e     +cbi DDRE , WF_DE
0002cb 9a76     +sbi PORTE , WF_DE
                 				SET_WF_DE
                +
0002cc 9200 0091+sts TCCR3B , CONST00
                 				STOP_CAPTURE
                +
0002ce 6031     +ori S_REG , ( 1 << S_REG_BUSY )
                 				RES_S_REG_BIT  S_REG_BUSY 
                +
                +
0002cf 9869     +cbi DDRE , INTRQ
                 				SET_INTRQ
0002d0 7f5e      				andi FLAGS , ~( 1 << NEW_CMD )
                +
0002d1 e6a0     +ldi XL , low ( _t0 )
0002d2 e0b1     +ldi XH , high ( _t0 )
0002d3 c2d9     +rjmp _end_state
                 				STATE_E _t0
                 
                 _cmd_type_2:
                 	_t2_s01:
                +
0002d4 ef3f     +ser S_REG
                 	_t2_s02:	CLR_S_REG 
                +
0002d5 7f3e     +andi S_REG , ~ ( 1 << S_REG_BUSY )
                 				SET_S_REG_BIT  S_REG_BUSY 
                +
                +
0002d6 9a57     +sbi DDRD , DRQ
                 				RES_DRQ
                +
                +
0002d7 9a69     +sbi DDRE , INTRQ
                 				RES_INTRQ
                +
0002d8 edab     +ldi XL , low ( _t2_s03 )
0002d9 e0b2     +ldi XH , high ( _t2_s03 )
0002da c2d2     +rjmp _end_state
                 				STATE_E _t2_s03   
                 	_t2_s03:    
                +
0002db eea2     +ldi XL , low ( _t2_s04 )
0002dc e0b2     +ldi XH , high ( _t2_s04 )
                 				STATE_M _t2_s04
                +
0002dd 9949     +sbic PIND , CPRDY
                 				CHECK_CPRDY
0002de c2ce      					rjmp _end_state
                +
0002df e5aa     +ldi XL , low ( _t2_s47 )
0002e0 e0b5     +ldi XH , high ( _t2_s47 )
0002e1 c2cb     +rjmp _end_state
                 				STATE_E _t2_s47
                 	_t2_s04:
                +
0002e2 9a5b     +sbi PORTD , HLD
                 				SET_HLD
                 	_t2_s05:
                +
0002e3 e0ad     +ldi XL , low ( _t2_s07 )
0002e4 e0b3     +ldi XH , high ( _t2_s07 )
                 				STATE_M _t2_s07
0002e5 fef2      				sbrs TEMP_CMD , 2
0002e6 c2c6      					rjmp _end_state
0002e7 e002      				ldi TEMP,0x02
                +
0002e8 ba18     +out TIFR3 , CONSTFF
0002e9 9200 0095+sts TCNT3H , CONST00
0002eb 9200 0094+sts TCNT3L , CONST00
0002ed 3000     +cpi TEMP , 0
0002ee f411     +brne $ ma1
0002ef e006     +ldi TEMP , 6 * KOEFF
0002f0 c009     +rjmp $ mae
                +$ ma1 :
0002f1 3001     +cpi TEMP , 1
0002f2 f411     +brne $ ma2
0002f3 e00c     +ldi TEMP , 12 * KOEFF
0002f4 c005     +rjmp $ mae
                +$ ma2 :
0002f5 3002     +cpi TEMP , 2
0002f6 f411     +brne $ ma3
0002f7 e104     +ldi TEMP , 20 * KOEFF
0002f8 c001     +rjmp $ mae
                +$ ma3 :
0002f9 e10e     +ldi TEMP , 30 * KOEFF
                +$ mae :
0002fa 9300 0099+sts OCR3AH , TEMP
0002fc 9200 0098+sts OCR3AL , CONST00
0002fe e00b     +ldi TEMP , ( 1 << WGM12 ) | ( 1 << CS11 ) | ( 1 << CS10 )
0002ff 9300 0091+sts TCCR3B , TEMP
                 				START_DELAY 
                +
000301 e0a4     +ldi XL , low ( _t2_s06 )
000302 e0b3     +ldi XH , high ( _t2_s06 )
000303 c2a9     +rjmp _end_state
                 				STATE_E _t2_s06
                 	_t2_s06:	
                +
000304 e0a4     +ldi XL , low ( _t2_s06 )
000305 e0b3     +ldi XH , high ( _t2_s06 )
                 				STATE_M _t2_s06
                +
000306 9bc1     +sbis TIFR3 , OCF3A
                 				CHECK_DELAY
000307 c2a5      					rjmp _end_state
                +
000308 9200 0091+sts TCCR3B , CONST00
                 				STOP_DELAY
                +
00030a e0ad     +ldi XL , low ( _t2_s07 )
00030b e0b3     +ldi XH , high ( _t2_s07 )
00030c c2a0     +rjmp _end_state
                 				STATE_E _t2_s07
                 	_t2_s07:	
                +
00030d e0ad     +ldi XL , low ( _t2_s07 )
00030e e0b3     +ldi XH , high ( _t2_s07 )
                 				STATE_M _t2_s07
                +
00030f 9b65     +sbis PINE , HRDY
                 				CHECK_HRDY
000310 c29c      					rjmp _end_state
                +
000311 e1a4     +ldi XL , low ( _t2_s08 )
000312 e0b3     +ldi XH , high ( _t2_s08 )
000313 c299     +rjmp _end_state
                 				STATE_E _t2_s08
                 	_t2_s08:				
000314 2d05      				mov TEMP , TR_REG
000315 9500      				com TEMP
000316 320b      				cpi TEMP , 43
000317 f41a      				brpl _t2_s09
                +
                +
                                 RES_TR43
                +
000318 e1ae     +ldi XL , low ( _t2_s10 )
000319 e0b3     +ldi XH , high ( _t2_s10 )
00031a c292     +rjmp _end_state
                 				STATE_E  _t2_s10
                 	_t2_s09:
                +
                +
                 				SET_TR43
                +
00031b e1ae     +ldi XL , low ( _t2_s10 )
00031c e0b3     +ldi XH , high ( _t2_s10 )
00031d c28f     +rjmp _end_state
                 				STATE_E _t2_s10	
                 	_t2_s10:
                +
00031e e2a5     +ldi XL , low ( _t2_s11 )
00031f e0b3     +ldi XH , high ( _t2_s11 )
                 				STATE_M _t2_s11
000320 fcf5      				sbrc TEMP_CMD , 5
000321 c28b      					rjmp _end_state
                +
000322 e2ad     +ldi XL , low ( _t2_s12_0 )
000323 e0b3     +ldi XH , high ( _t2_s12_0 )
000324 c288     +rjmp _end_state
                 				STATE_E _t2_s12_0
                 	_t2_s11:	
                +
000325 e2ad     +ldi XL , low ( _t2_s12_0 )
000326 e0b3     +ldi XH , high ( _t2_s12_0 )
                 				STATE_M _t2_s12_0
                +
000327 9962     +sbic PINE , WRPT
                 				CHECK_WRPT
000328 c284      					rjmp _end_state
                +
000329 7b3f     +andi S_REG , ~ ( 1 << S_REG_WR_PR )
                 				SET_S_REG_BIT   S_REG_WR_PR
                +
00032a e5aa     +ldi XL , low ( _t2_s47 )
00032b e0b5     +ldi XH , high ( _t2_s47 )
00032c c280     +rjmp _end_state
                 				STATE_E _t2_s47				
                 	_t2_s12_0:
                +
00032d 9a6e     +sbi DDRE , WF_DE
00032e 9876     +cbi PORTE , WF_DE
                 				RES_WF_DE
00032f ef0b      				ldi TEMP , (-5)
                +
000330 9200 0081+sts TCCR1B , CONST00
000332 9200 0080+sts TCCR1A , CONST00
000334 9210 0085+sts TCNT1H , CONSTFF
000336 9300 0084+sts TCNT1L , TEMP
000338 ba16     +out TIFR1 , CONSTFF
000339 e006     +ldi TEMP , ( 1 << CS12 ) | ( 1 << CS11 )
00033a 9300 0081+sts TCCR1B , TEMP
                +
                 				START_IP  
                +
00033c e002     +ldi TEMP , 0x02
00033d 9300 0091+sts TCCR3B , TEMP
                 				START_CAPTURE
                +
00033f e4a2     +ldi XL , low ( _t2_s12 )
000340 e0b3     +ldi XH , high ( _t2_s12 )
000341 c26b     +rjmp _end_state
                 				STATE_E _t2_s12
                 	_t2_s12:
                +
000342 e4aa     +ldi XL , low ( _t2_s13 )
000343 e0b3     +ldi XH , high ( _t2_s13 )
                                 STATE_M _t2_s13
                +
000344 9bb0     +sbis TIFR1 , TOV1
                 				CHECK_IP
000345 c267      					rjmp _end_state
                +
000346 7e3f     +andi S_REG , ~ ( 1 << S_REG_SEEK_ERR )
                 				SET_S_REG_BIT  S_REG_SEEK_ERR 
                +
000347 e5aa     +ldi XL , low ( _t2_s47 )
000348 e0b5     +ldi XH , high ( _t2_s47 )
000349 c263     +rjmp _end_state
                 				STATE_E _t2_s47
                 	_t2_s13:    
                +
00034a e4a2     +ldi XL , low ( _t2_s12 )
00034b e0b3     +ldi XH , high ( _t2_s12 )
                 	            STATE_M _t2_s12
                +
00034c e4a2     +ldi XL , low ( _t2_s12 )
00034d e0b3     +ldi XH , high ( _t2_s12 )
00034e ff56     +sbrs FLAGS , SYNC
00034f c212     +rjmp _start_state
000350 7b5d     +andi FLAGS , ~ ( ( 1 << SYNC ) | ( 1 << S_D_R ) )
                +
                +
                +
                +
                 				WAIT_SYNC_A1  _t2_s12
                +
000351 eb04     +ldi TEMP , low ( 0xCDB4 )
000352 2e80     +mov CRC_L , TEMP
000353 ec0d     +ldi TEMP , high ( 0xCDB4 )
000354 2e90     +mov CRC_H , TEMP
                 				INI_CRC
                 	_t2_s13_1:
                +
000355 e5a5     +ldi XL , low ( _t2_s13_1 )
000356 e0b3     +ldi XH , high ( _t2_s13_1 )
000357 ff51     +sbrs FLAGS , S_D_R
000358 c209     +rjmp _start_state
000359 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R 	_t2_s13_1
00035a 3f4e      				cpi TEMP_D_REG  , 0xFE
00035b f019      				breq _t2_s14
                +
00035c e4a2     +ldi XL , low ( _t2_s12 )
00035d e0b3     +ldi XH , high ( _t2_s12 )
00035e c24e     +rjmp _end_state
                 				STATE_E _t2_s12
                 	_t2_s14:
                +
00035f e5af     +ldi XL , low ( _t2_s14 )
000360 e0b3     +ldi XH , high ( _t2_s14 )
000361 ff51     +sbrs FLAGS , S_D_R
000362 c1ff     +rjmp _start_state
000363 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R 	_t2_s14
000364 9540      				com TEMP_D_REG
000365 1654      				cp TR_REG , TEMP_D_REG
000366 f019      				breq _t2_s15
                +
000367 e4a2     +ldi XL , low ( _t2_s12 )
000368 e0b3     +ldi XH , high ( _t2_s12 )
000369 c243     +rjmp _end_state
                 				STATE_E _t2_s12
                 	_t2_s15:	
                +
00036a e6aa     +ldi XL , low ( _t2_s15 )
00036b e0b3     +ldi XH , high ( _t2_s15 )
00036c ff51     +sbrs FLAGS , S_D_R
00036d c1f4     +rjmp _start_state
00036e 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R  _t2_s15
                +
00036f e8a6     +ldi XL , low ( _t2_s16 )
000370 e0b3     +ldi XH , high ( _t2_s16 )
                 				STATE_M _t2_s16
000371 fef1      				sbrs TEMP_CMD , 1
000372 c1ef      					rjmp _start_state
000373 7041      				andi TEMP_D_REG , 0b00000001
                +
000374 e7af     +ldi XL , low ( _t2_s15_1 )
000375 e0b3     +ldi XH , high ( _t2_s15_1 )
                 				STATE_M _t2_s15_1
000376 fef3      				sbrs TEMP_CMD , 3
000377 c1ea      					rjmp _start_state
                +
000378 e8a6     +ldi XL , low ( _t2_s16 )
000379 e0b3     +ldi XH , high ( _t2_s16 )
                 					STATE_M _t2_s16
00037a fd40      				sbrc TEMP_D_REG  , 0
00037b c231      					rjmp _end_state
                +
00037c e4a2     +ldi XL , low ( _t2_s12 )
00037d e0b3     +ldi XH , high ( _t2_s12 )
00037e c22e     +rjmp _end_state
                 				STATE_E _t2_s12
                 
                 	_t2_s15_1:				  
                +
00037f e8a6     +ldi XL , low ( _t2_s16 )
000380 e0b3     +ldi XH , high ( _t2_s16 )
                   				STATE_M _t2_s16
000381 ff40      				sbrs TEMP_D_REG  , 0
000382 c22a      					rjmp _end_state
                +
000383 e4a2     +ldi XL , low ( _t2_s12 )
000384 e0b3     +ldi XH , high ( _t2_s12 )
000385 c227     +rjmp _end_state
                 				STATE_E _t2_s12  
                 	_t2_s16:
                +
000386 e8a6     +ldi XL , low ( _t2_s16 )
000387 e0b3     +ldi XH , high ( _t2_s16 )
000388 ff51     +sbrs FLAGS , S_D_R
000389 c1d8     +rjmp _start_state
00038a 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R  _t2_s16
00038b 9540      			    com TEMP_D_REG
00038c 1664      				cp SECT_REG , TEMP_D_REG
00038d f019      				breq _t2_s17
                 				
                +
00038e e4a2     +ldi XL , low ( _t2_s12 )
00038f e0b3     +ldi XH , high ( _t2_s12 )
                 				STATE_M _t2_s12
000390 c1d1      					rjmp _start_state
                 	_t2_s17:			
                +
000391 e9a1     +ldi XL , low ( _t2_s17 )
000392 e0b3     +ldi XH , high ( _t2_s17 )
000393 ff51     +sbrs FLAGS , S_D_R
000394 c1cd     +rjmp _start_state
000395 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R  _t2_s17
                +
000396 eaa1     +ldi XL , low ( _t2_s18 )
000397 e0b3     +ldi XH , high ( _t2_s18 )
                                	STATE_M _t2_s18
                 				
000398 e800      				ldi TEMP , 0x80
000399 2ea0      				mov SECT_LEN , TEMP
00039a 2cb1      				mov SECT_LEN_H , CONSTFF
                 
00039b 1540      	            cp TEMP_D_REG , CONST00
00039c f021      				breq _t2_s18_0
                 _t2_s17_1:
00039d 0caa      				lsl SECT_LEN
00039e 1cbb      				rol SECT_LEN_H
00039f 954a      				dec TEMP_D_REG
0003a0 f7e1      				brne _t2_s17_1				
                 _t2_s18_0:
                 ;				neg SECT_LEN_H
                 ;				neg SECT_LEN
                 ;				sbc SECT_LEN_H , CONST00
                 
                 _t2_s18:
                +
0003a1 eaa1     +ldi XL , low ( _t2_s18 )
0003a2 e0b3     +ldi XH , high ( _t2_s18 )
0003a3 ff51     +sbrs FLAGS , S_D_R
0003a4 c1bd     +rjmp _start_state
0003a5 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R  _t2_s18
                 _t2_s18_1:				
                +
0003a6 eaa6     +ldi XL , low ( _t2_s18_1 )
0003a7 e0b3     +ldi XH , high ( _t2_s18_1 )
0003a8 ff51     +sbrs FLAGS , S_D_R
0003a9 c1b8     +rjmp _start_state
0003aa 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R  _t2_s18_1
0003ab 2898      				or CRC_H , CRC_L
0003ac f021      				breq _t2_s19
                 _t2_s18_2:
                +
0003ad 7f37     +andi S_REG , ~ ( 1 << S_REG_CRC_ERR )
                 	            SET_S_REG_BIT  S_REG_CRC_ERR 
                +
0003ae e4a2     +ldi XL , low ( _t2_s12 )
0003af e0b3     +ldi XH , high ( _t2_s12 )
0003b0 c1fc     +rjmp _end_state
                 				STATE_E _t2_s12 
                 _t2_s19:		
                +
0003b1 6038     +ori S_REG , ( 1 << S_REG_CRC_ERR )
                 				RES_S_REG_BIT  S_REG_CRC_ERR
                 			
                +
0003b2 e0a5     +ldi XL , low ( _t2_s31 )
0003b3 e0b4     +ldi XH , high ( _t2_s31 )
                 _t2_s20:		STATE_M _t2_s31
0003b4 fcf5      				sbrc TEMP_CMD , 5
0003b5 c1f7      					rjmp _end_state
                +
0003b6 eba9     +ldi XL , low ( _t2_s21 )
0003b7 e0b3     +ldi XH , high ( _t2_s21 )
0003b8 c1f4     +rjmp _end_state
                 				STATE_E _t2_s21			
                 _t2_s21:        
                +
0003b9 eba9     +ldi XL , low ( _t2_s21 )
0003ba e0b3     +ldi XH , high ( _t2_s21 )
                 				STATE_M _t2_s21
                +
0003bb eba9     +ldi XL , low ( _t2_s21 )
0003bc e0b3     +ldi XH , high ( _t2_s21 )
0003bd ff56     +sbrs FLAGS , SYNC
0003be c1a3     +rjmp _start_state
0003bf 7b5d     +andi FLAGS , ~ ( ( 1 << SYNC ) | ( 1 << S_D_R ) )
                +
                +
                +
                +
                 				WAIT_SYNC_A1  _t2_s21
                +
0003c0 eb04     +ldi TEMP , low ( 0xCDB4 )
0003c1 2e80     +mov CRC_L , TEMP
0003c2 ec0d     +ldi TEMP , high ( 0xCDB4 )
0003c3 2e90     +mov CRC_H , TEMP
                 				INI_CRC
                 _t2_s21_2:				
                +
0003c4 eca4     +ldi XL , low ( _t2_s21_2 )
0003c5 e0b3     +ldi XH , high ( _t2_s21_2 )
0003c6 ff51     +sbrs FLAGS , S_D_R
0003c7 c19a     +rjmp _start_state
0003c8 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R 	_t2_s21_2
0003c9 3f48      				cpi TEMP_D_REG  , 0xF8
0003ca f029      				breq _t2_s22
0003cb 3f4b      				cpi TEMP_D_REG  , 0xFB
0003cc f021      				breq _t2_s23
                +
0003cd eba9     +ldi XL , low ( _t2_s21 )
0003ce e0b3     +ldi XH , high ( _t2_s21 )
                 				STATE_M _t2_s21
0003cf c192      				rjmp _start_state
                 	_t2_s22:        
                +
0003d0 7d3f     +andi S_REG , ~ ( 1 << S_REG_TYPE_REC )
                 				SET_S_REG_BIT   S_REG_TYPE_REC  
                    	_t2_s23:
                 	_t2_s25:
                +
0003d1 eda1     +ldi XL , low ( _t2_s25 )
0003d2 e0b3     +ldi XH , high ( _t2_s25 )
0003d3 ff51     +sbrs FLAGS , S_D_R
0003d4 c18d     +rjmp _start_state
0003d5 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                                 WAIT_SHIFT_R _t2_s25
0003d6 2e74      				mov DAT_REG , TEMP_D_REG
0003d7 9470      	            com DAT_REG
                 	_t2_s26:
                +
0003d8 edae     +ldi XL , low ( _t2_s27 )
0003d9 e0b3     +ldi XH , high ( _t2_s27 )
                                 STATE_M _t2_s27
                +
0003da b109     +in TEMP , PIND
0003db ff07     +sbrs TEMP , DRQ
                 				CHECK_DRQ
0003dc c185      					rjmp _start_state
                +
0003dd 7f3b     +andi S_REG , ~ ( 1 << S_REG_DATA_LOST )
                 				SET_S_REG_BIT  S_REG_DATA_LOST 
                 	_t2_s27:
                +
                +
0003de 9857     +cbi DDRD , DRQ
                 				SET_DRQ
                +
0003df 94a3     +inc SECT_LEN
0003e0 f409     +brne $ inc_end
0003e1 94b3     +inc SECT_LEN_H
                +$ inc_end :
                 				INC_SECT_LEN
0003e2 f019      				breq _t2_s28
                +
0003e3 eda1     +ldi XL , low ( _t2_s25 )
0003e4 e0b3     +ldi XH , high ( _t2_s25 )
                 				STATE_M _t2_s25
0003e5 c17c      				rjmp _start_state
                 	_t2_s28:
                +
0003e6 eea6     +ldi XL , low ( _t2_s28 )
0003e7 e0b3     +ldi XH , high ( _t2_s28 )
0003e8 ff51     +sbrs FLAGS , S_D_R
0003e9 c178     +rjmp _start_state
0003ea 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R _t2_s28
                 	_t2_s28_1:
                +
0003eb eeab     +ldi XL , low ( _t2_s28_1 )
0003ec e0b3     +ldi XH , high ( _t2_s28_1 )
0003ed ff51     +sbrs FLAGS , S_D_R
0003ee c173     +rjmp _start_state
0003ef 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R _t2_s28_1			
0003f0 2898      				or CRC_H , CRC_L
0003f1 f021      				breq _t2_s28_3
                 	_t2_s28_2:
                +
0003f2 7f37     +andi S_REG , ~ ( 1 << S_REG_CRC_ERR )
                 				SET_S_REG_BIT  S_REG_CRC_ERR 
                +
0003f3 e5aa     +ldi XL , low ( _t2_s47 )
0003f4 e0b5     +ldi XH , high ( _t2_s47 )
0003f5 c1b7     +rjmp _end_state
                 				STATE_E _t2_s47 
                 	_t2_s28_3:	
                +
0003f6 6038     +ori S_REG , ( 1 << S_REG_CRC_ERR )
                 				RES_S_REG_BIT  S_REG_CRC_ERR 
                +
0003f7 efaa     +ldi XL , low ( _t2_s29 )
0003f8 e0b3     +ldi XH , high ( _t2_s29 )
0003f9 c1b3     +rjmp _end_state
                 				STATE_E _t2_s29 
                 	_t2_s29:
                +
0003fa e5aa     +ldi XL , low ( _t2_s47 )
0003fb e0b5     +ldi XH , high ( _t2_s47 )
                 				STATE_M _t2_s47
0003fc fef4      				sbrs TEMP_CMD , 4
0003fd c1af      					rjmp _end_state
                +
0003fe e0a1     +ldi XL , low ( _t2_s30 )
0003ff e0b4     +ldi XH , high ( _t2_s30 )
000400 c1ac     +rjmp _end_state
                 				STATE_E _t2_s30
                 	_t2_s30:	
000401 946a      				dec SECT_REG
                +
000402 e1ae     +ldi XL , low ( _t2_s10 )
000403 e0b3     +ldi XH , high ( _t2_s10 )
000404 c1a8     +rjmp _end_state
                 				STATE_E _t2_s10
                 	_t2_s31:	
000405 e008      				ldi TEMP , 8
                +
000406 9200 00b1+sts TCCR2B , CONST00
000408 9300 00b3+sts OCR2A , TEMP
00040a e002     +ldi TEMP , 2
00040b 9300 00b0+sts TCCR2A , TEMP
00040d 9200 00b2+sts TCNT2 , CONST00
00040f ba17     +out TIFR2 , CONSTFF
000410 e006     +ldi TEMP , 6
000411 9300 00b1+sts TCCR2B , TEMP
                +
                 				START_DELAY_32
                 	_t2_s32:	
                +
000413 e1a3     +ldi XL , low ( _t2_s32 )
000414 e0b4     +ldi XH , high ( _t2_s32 )
                 				STATE_M _t2_s32
                +
000415 9bb9     +sbis TIFR2 , OCF2A
                 				CHECK_DELAY_32
000416 c196      					rjmp _end_state
                +
000417 9200 00b1+sts TCCR2B , CONST00
                 				STOP_DELAY_32
                +
                +
000419 9857     +cbi DDRD , DRQ
                 				SET_DRQ			
                 				
00041a e200      				ldi TEMP , 32
                +
00041b 9200 00b1+sts TCCR2B , CONST00
00041d 9300 00b3+sts OCR2A , TEMP
00041f e002     +ldi TEMP , 2
000420 9300 00b0+sts TCCR2A , TEMP
000422 9200 00b2+sts TCNT2 , CONST00
000424 ba17     +out TIFR2 , CONSTFF
000425 e006     +ldi TEMP , 6
000426 9300 00b1+sts TCCR2B , TEMP
                +
                 				START_DELAY_32
                +
000428 e2aa     +ldi XL , low ( _t2_s33 )
000429 e0b4     +ldi XH , high ( _t2_s33 )
                 				STATE_M _t2_s33
                 	_t2_s33:
                +
00042a 9bb9     +sbis TIFR2 , OCF2A
                 				CHECK_DELAY_32
00042b c181      					rjmp _end_state
                +
00042c 9200 00b1+sts TCCR2B , CONST00
                 				STOP_DELAY_32
                +
00042e e3a1     +ldi XL , low ( _t2_s34 )
00042f e0b4     +ldi XH , high ( _t2_s34 )
000430 c17c     +rjmp _end_state
                 				STATE_E _t2_s34
                 	_t2_s34:
                +
000431 e3aa     +ldi XL , low ( _t2_s35 )
000432 e0b4     +ldi XH , high ( _t2_s35 )
                 				STATE_M _t2_s35
                +
000433 b109     +in TEMP , PIND
000434 ff07     +sbrs TEMP , DRQ
                 				CHECK_DRQ
000435 c177      					rjmp _end_state
                +
000436 7f3b     +andi S_REG , ~ ( 1 << S_REG_DATA_LOST )
                 				SET_S_REG_BIT S_REG_DATA_LOST
                +
000437 e5aa     +ldi XL , low ( _t2_s47 )
000438 e0b5     +ldi XH , high ( _t2_s47 )
000439 c173     +rjmp _end_state
                 				STATE_E _t2_s47
                 	_t2_s35:		
00043a e004      				ldi TEMP , 4
                +
00043b 9200 00b1+sts TCCR2B , CONST00
00043d 9300 00b3+sts OCR2A , TEMP
00043f e002     +ldi TEMP , 2
000440 9300 00b0+sts TCCR2A , TEMP
000442 9200 00b2+sts TCNT2 , CONST00
000444 ba17     +out TIFR2 , CONSTFF
000445 e006     +ldi TEMP , 6
000446 9300 00b1+sts TCCR2B , TEMP
                +
                 				START_DELAY_32
                +
000448 e4aa     +ldi XL , low ( _t2_s35_0 )
000449 e0b4     +ldi XH , high ( _t2_s35_0 )
                 				STATE_M _t2_s35_0
                 	_t2_s35_0:	
                +
00044a 9bb9     +sbis TIFR2 , OCF2A
                 				CHECK_DELAY_32
00044b c161      					rjmp _end_state
                +
00044c 9200 00b1+sts TCCR2B , CONST00
                 				STOP_DELAY_32
                +
00044e e5a1     +ldi XL , low ( _t2_s36 )
00044f e0b4     +ldi XH , high ( _t2_s36 )
000450 c15c     +rjmp _end_state
                 				STATE_E _t2_s36
                 	_t2_s36:	
000451 e20c      				ldi TEMP , 44
                +
000452 9200 00b1+sts TCCR2B , CONST00
000454 9300 00b3+sts OCR2A , TEMP
000456 e002     +ldi TEMP , 2
000457 9300 00b0+sts TCCR2A , TEMP
000459 9200 00b2+sts TCNT2 , CONST00
00045b ba17     +out TIFR2 , CONSTFF
00045c e006     +ldi TEMP , 6
00045d 9300 00b1+sts TCCR2B , TEMP
                +
                 				START_DELAY_32
                +
00045f e6a1     +ldi XL , low ( _t2_s37 )
000460 e0b4     +ldi XH , high ( _t2_s37 )
                 				STATE_M _t2_s37
                 	_t2_s37:
                +
000461 9bb9     +sbis TIFR2 , OCF2A
                 				CHECK_DELAY_32
000462 c14a      					rjmp _end_state
                +
000463 9200 00b1+sts TCCR2B , CONST00
                 				STOP_DELAY_32
                +
000465 e6a8     +ldi XL , low ( _t2_s38 )
000466 e0b4     +ldi XH , high ( _t2_s38 )
000467 c145     +rjmp _end_state
                 				STATE_E _t2_s38
                    	_t2_s38:
                +
000468 e008     +ldi TEMP , ( 1 << TXEN )
000469 9300 00c1+sts UCSRB , TEMP
                 				START_WRITE
                +
00046b 9a70     +sbi PORTE , WG
                 				SET_WG
                +
00046c 986e     +cbi DDRE , WF_DE
00046d 9a76     +sbi PORTE , WF_DE
                 				SET_WF_DE			
00046e e070      				ldi SHIFT_REG_S , 0 
                 				.if OLD_WRITE == 1
                 				.else
00046f e424      					ldi SHIFT_REG , 0x44
                 				.endif
000470 e360      				ldi SHIFT_COUNT , 12 * BIT_COUNT
                +
000471 e7a3     +ldi XL , low ( _t2_s38_1 )
000472 e0b4     +ldi XH , high ( _t2_s38_1 )
                 				STATE_M _t2_s38_1
                 	_t2_s38_1:			
                +
                +$ ms0 :
000473 90d0 00c0+lds TEMP1 , UCSRA
000475 fed5     +sbrs TEMP1 , UDRE
000476 c136     +rjmp _end_state
000477 9320 00c6+sts UDR , SHIFT_REG
000479 956a     +dec SHIFT_COUNT
00047a f7c1     +brne _t2_s38_1
                 				OUT_BIT_ SHIFT_REG , _t2_s38_1
                 				
                 	_t2_s39:
00047b e064      				ldi SHIFT_COUNT , BIT_COUNT
00047c e5d4      				ldi YH , high( A1_table * 2 ) + 0x40
00047d e0c8      				ldi YL , low( A1_table  * 2 )
                 				
                +
00047e e8a1     +ldi XL , low ( _t2_s39_0_2 )
00047f e0b4     +ldi XH , high ( _t2_s39_0_2 )
                 				STATE_M _t2_s39_0_2
                 	_t2_s39_0_1:
000480 9129      				ld  SHIFT_REG , Y+
                 	_t2_s39_0_2:							
                +
                +$ ms0 :
000481 90d0 00c0+lds TEMP1 , UCSRA
000483 fed5     +sbrs TEMP1 , UDRE
000484 c128     +rjmp _end_state
000485 9320 00c6+sts UDR , SHIFT_REG
000487 956a     +dec SHIFT_COUNT
000488 f7b9     +brne _t2_s39_0_1
                 				OUT_BIT_ SHIFT_REG , _t2_s39_0_1
000489 e071      				ldi SHIFT_REG_S , 1
                +
00048a eb04     +ldi TEMP , low ( 0xCDB4 )
00048b 2e80     +mov CRC_L , TEMP
00048c ec0d     +ldi TEMP , high ( 0xCDB4 )
00048d 2e90     +mov CRC_H , TEMP
                 				INI_CRC
                 				
00048e e064      				ldi SHIFT_COUNT , BIT_COUNT
00048f e5d4      				ldi YH , high( A1_table * 2 ) + 0x40
000490 e0c8      				ldi YL , low( A1_table  * 2 )
                +
000491 e9a4     +ldi XL , low ( _t2_s39_2 )
000492 e0b4     +ldi XH , high ( _t2_s39_2 )
                 				STATE_M _t2_s39_2
                 	_t2_s39_1:
000493 9129      				ld  SHIFT_REG , Y+
                 	_t2_s39_2:							
                +
                +$ ms0 :
000494 90d0 00c0+lds TEMP1 , UCSRA
000496 fed5     +sbrs TEMP1 , UDRE
000497 c115     +rjmp _end_state
000498 9320 00c6+sts UDR , SHIFT_REG
00049a 956a     +dec SHIFT_COUNT
00049b f7b9     +brne _t2_s39_1
                 				OUT_BIT_ SHIFT_REG , _t2_s39_1				
                 					
00049c ef4b      				ldi TEMP_D_REG , 0xFB
                +
00049d ff35     +sbrs S_REG , S_REG_TYPE_REC
                 				CHECK_S_REG_BIT S_REG_TYPE_REC
00049e ef48      				ldi TEMP_D_REG , 0xF8
                 			
00049f e064      				ldi SHIFT_COUNT , BIT_COUNT
0004a0 e5d4      				ldi YH , high( A1_table * 2 ) + 0x40
0004a1 e0c8      				ldi YL , low( A1_table  * 2 )
0004a2 e071      				ldi SHIFT_REG_S , 1
                +
0004a3 eaa6     +ldi XL , low ( _t2_s39_1_2 )
0004a4 e0b4     +ldi XH , high ( _t2_s39_1_2 )
                 				STATE_M _t2_s39_1_2
                 	_t2_s39_1_1:
0004a5 9129      				ld  SHIFT_REG , Y+
                 	_t2_s39_1_2:							
                +
                +$ ms0 :
0004a6 90d0 00c0+lds TEMP1 , UCSRA
0004a8 fed5     +sbrs TEMP1 , UDRE
0004a9 c103     +rjmp _end_state
0004aa 9320 00c6+sts UDR , SHIFT_REG
0004ac 956a     +dec SHIFT_COUNT
0004ad f7b9     +brne _t2_s39_1_1
                 				OUT_BIT_ SHIFT_REG , _t2_s39_1_1				
                 					
                +
0004ae 2fc4     +mov YL , TEMP_D_REG
0004af 25c9     +eor YL , CRC_H
0004b0 e5d3     +ldi YH , high ( 2 * crchi ) + 0x40
0004b1 8098     +ld CRC_H , Y
0004b2 2498     +eor CRC_H , CRC_L
0004b3 95da     +dec YH
0004b4 8088     +ld CRC_L , Y
                 				CALC_CRC TEMP_D_REG
                 	;			INC_SECT_LEN
                 				
0004b5 e064      				ldi SHIFT_COUNT , BIT_COUNT
                +
0004b6 eca2     +ldi XL , low ( _t2_s39_2_2 )
0004b7 e0b4     +ldi XH , high ( _t2_s39_2_2 )
                 				STATE_M _t2_s39_2_2
                 	_t2_s39_2_1:
                +
                +.if OLD_WRITE == 1
                +mw0 :
                +lsl TEMP_D_REG
0004b8 0f44     +brcc mw1
0004b9 1f77     +
0004ba 0f44     +ori SHIFT_REG_S , 1
0004bb 1f77     +ldi SHIFT_REG , ( 1 )
0004bc 7077     +rjmp mw2
0004bd e5d4     +mw1 :
0004be e0c0     +ldi SHIFT_REG , 0x0
0004bf 0fc7     +sbrs SHIFT_REG_S , 0
0004c0 1dd0     +ldi SHIFT_REG , ( 1 << 4 )
0004c1 8128     +andi SHIFT_REG_S , ~ ( 1 )
                +mw2 :
                 				WRITE_DATA
                 	_t2_s39_2_2:			
                +
                +$ ms0 :
0004c2 90d0 00c0+lds TEMP1 , UCSRA
0004c4 fed5     +sbrs TEMP1 , UDRE
0004c5 c0e7     +rjmp _end_state
0004c6 9320 00c6+sts UDR , SHIFT_REG
0004c8 956a     +dec SHIFT_COUNT
0004c9 f771     +brne _t2_s39_2_1
                 				OUT_BIT_ SHIFT_REG , _t2_s39_2_1 
                 				
                 	_t2_s40:		
0004ca 2d47      				mov TEMP_D_REG , DAT_REG
0004cb 9540      				com TEMP_D_REG
                +
0004cc 2fc4     +mov YL , TEMP_D_REG
0004cd 25c9     +eor YL , CRC_H
0004ce e5d3     +ldi YH , high ( 2 * crchi ) + 0x40
0004cf 8098     +ld CRC_H , Y
0004d0 2498     +eor CRC_H , CRC_L
0004d1 95da     +dec YH
0004d2 8088     +ld CRC_L , Y
                 				CALC_CRC TEMP_D_REG
                +
                +
0004d3 9857     +cbi DDRD , DRQ
                 				SET_DRQ
                 				
0004d4 e064      				ldi SHIFT_COUNT , BIT_COUNT
                +
0004d5 eea1     +ldi XL , low ( _t2_s40_2 )
0004d6 e0b4     +ldi XH , high ( _t2_s40_2 )
                 				STATE_M _t2_s40_2
                 	_t2_s40_1:
                +
                +.if OLD_WRITE == 1
                +mw0 :
                +lsl TEMP_D_REG
0004d7 0f44     +brcc mw1
0004d8 1f77     +
0004d9 0f44     +ori SHIFT_REG_S , 1
0004da 1f77     +ldi SHIFT_REG , ( 1 )
0004db 7077     +rjmp mw2
0004dc e5d4     +mw1 :
0004dd e0c0     +ldi SHIFT_REG , 0x0
0004de 0fc7     +sbrs SHIFT_REG_S , 0
0004df 1dd0     +ldi SHIFT_REG , ( 1 << 4 )
0004e0 8128     +andi SHIFT_REG_S , ~ ( 1 )
                +mw2 :
                 				WRITE_DATA
                 	_t2_s40_2:			
                +
                +$ ms0 :
0004e1 90d0 00c0+lds TEMP1 , UCSRA
0004e3 fed5     +sbrs TEMP1 , UDRE
0004e4 c0c8     +rjmp _end_state
0004e5 9320 00c6+sts UDR , SHIFT_REG
0004e7 956a     +dec SHIFT_COUNT
0004e8 f771     +brne _t2_s40_1
                 				OUT_BIT_ SHIFT_REG , _t2_s40_1
                 	_t2_s41:			
                +
0004e9 efa1     +ldi XL , low ( _t2_s42 )
0004ea e0b4     +ldi XH , high ( _t2_s42 )
                 				STATE_M _t2_s42
                +
0004eb b109     +in TEMP , PIND
0004ec ff07     +sbrs TEMP , DRQ
                 				CHECK_DRQ
0004ed c0bf      					rjmp _end_state
                +
0004ee 7f3b     +andi S_REG , ~ ( 1 << S_REG_DATA_LOST )
                 				SET_S_REG_BIT  S_REG_DATA_LOST 
0004ef 2c71      				mov DAT_REG , CONSTFF
0004f0 c0bc      				rjmp _end_state
                 	_t2_s42:			
                +
0004f1 ecaa     +ldi XL , low ( _t2_s40 )
0004f2 e0b4     +ldi XH , high ( _t2_s40 )
                 				STATE_M _t2_s40
                +
0004f3 94a3     +inc SECT_LEN
0004f4 f409     +brne $ inc_end
0004f5 94b3     +inc SECT_LEN_H
                +$ inc_end :
                 				INC_SECT_LEN
0004f6 f009      				breq _t2_s43
0004f7 c0b5      				rjmp _end_state
                 	_t2_s43:
                 ;	           	mov TEMP_D_REG , DAT_REG
                 ;				com TEMP_D_REG
                 ;				CALC_CRC TEMP_D_REG
                 ;				
                 ;				ldi SHIFT_COUNT , BIT_COUNT
                 ;				STATE_M _t2_s43_2
                 ;	_t2_s43_1:
                 ;				WRITE_DATA
                 ;	_t2_s43_2:			
                 ;				OUT_BIT_ SHIFT_REG , _t2_s43_1
                 ;		
                 	_t2_s44:		
0004f8 2d49      				mov TEMP_D_REG , CRC_H
                 				
0004f9 e064      				ldi SHIFT_COUNT , BIT_COUNT
                +
0004fa e0a6     +ldi XL , low ( _t2_s44_0_2 )
0004fb e0b5     +ldi XH , high ( _t2_s44_0_2 )
                 				STATE_M _t2_s44_0_2
                 	_t2_s44_0_1:
                +
                +.if OLD_WRITE == 1
                +mw0 :
                +lsl TEMP_D_REG
0004fc 0f44     +brcc mw1
0004fd 1f77     +
0004fe 0f44     +ori SHIFT_REG_S , 1
0004ff 1f77     +ldi SHIFT_REG , ( 1 )
000500 7077     +rjmp mw2
000501 e5d4     +mw1 :
000502 e0c0     +ldi SHIFT_REG , 0x0
000503 0fc7     +sbrs SHIFT_REG_S , 0
000504 1dd0     +ldi SHIFT_REG , ( 1 << 4 )
000505 8128     +andi SHIFT_REG_S , ~ ( 1 )
                +mw2 :
                 				WRITE_DATA
                 	_t2_s44_0_2:			
                +
                +$ ms0 :
000506 90d0 00c0+lds TEMP1 , UCSRA
000508 fed5     +sbrs TEMP1 , UDRE
000509 c0a3     +rjmp _end_state
00050a 9320 00c6+sts UDR , SHIFT_REG
00050c 956a     +dec SHIFT_COUNT
00050d f771     +brne _t2_s44_0_1
                 				OUT_BIT_ SHIFT_REG , _t2_s44_0_1
                 					
00050e 2d48      				mov TEMP_D_REG , CRC_L
00050f e064      				ldi SHIFT_COUNT , BIT_COUNT				
                +
000510 e1ac     +ldi XL , low ( _t2_s44_2 )
000511 e0b5     +ldi XH , high ( _t2_s44_2 )
                 				STATE_M _t2_s44_2
                 	_t2_s44_1:
                +
                +.if OLD_WRITE == 1
                +mw0 :
                +lsl TEMP_D_REG
000512 0f44     +brcc mw1
000513 1f77     +
000514 0f44     +ori SHIFT_REG_S , 1
000515 1f77     +ldi SHIFT_REG , ( 1 )
000516 7077     +rjmp mw2
000517 e5d4     +mw1 :
000518 e0c0     +ldi SHIFT_REG , 0x0
000519 0fc7     +sbrs SHIFT_REG_S , 0
00051a 1dd0     +ldi SHIFT_REG , ( 1 << 4 )
00051b 8128     +andi SHIFT_REG_S , ~ ( 1 )
                +mw2 :
                 				WRITE_DATA
                 	_t2_s44_2:			
                +
                +$ ms0 :
00051c 90d0 00c0+lds TEMP1 , UCSRA
00051e fed5     +sbrs TEMP1 , UDRE
00051f c08d     +rjmp _end_state
000520 9320 00c6+sts UDR , SHIFT_REG
000522 956a     +dec SHIFT_COUNT
000523 f771     +brne _t2_s44_1
                 				OUT_BIT_ SHIFT_REG , _t2_s44_1
                 					
                 	_t2_s45:		
000524 ef4f      				ser  TEMP_D_REG 
                 							
000525 e064      				ldi SHIFT_COUNT , BIT_COUNT
                +
000526 e3a2     +ldi XL , low ( _t2_s45_0_2 )
000527 e0b5     +ldi XH , high ( _t2_s45_0_2 )
                 				STATE_M _t2_s45_0_2
                 	_t2_s45_0_1:
                +
                +.if OLD_WRITE == 1
                +mw0 :
                +lsl TEMP_D_REG
000528 0f44     +brcc mw1
000529 1f77     +
00052a 0f44     +ori SHIFT_REG_S , 1
00052b 1f77     +ldi SHIFT_REG , ( 1 )
00052c 7077     +rjmp mw2
00052d e5d4     +mw1 :
00052e e0c0     +ldi SHIFT_REG , 0x0
00052f 0fc7     +sbrs SHIFT_REG_S , 0
000530 1dd0     +ldi SHIFT_REG , ( 1 << 4 )
000531 8128     +andi SHIFT_REG_S , ~ ( 1 )
                +mw2 :
                 				WRITE_DATA
                 	_t2_s45_0_2:			
                +
                +$ ms0 :
000532 90d0 00c0+lds TEMP1 , UCSRA
000534 fed5     +sbrs TEMP1 , UDRE
000535 c077     +rjmp _end_state
000536 9320 00c6+sts UDR , SHIFT_REG
000538 956a     +dec SHIFT_COUNT
000539 f771     +brne _t2_s45_0_1
                 				OUT_BIT_ SHIFT_REG , _t2_s45_0_1
                 							
00053a ef4f      				ser  TEMP_D_REG 
                 							
00053b e064      				ldi SHIFT_COUNT , BIT_COUNT
                +
00053c e4a8     +ldi XL , low ( _t2_s45_2 )
00053d e0b5     +ldi XH , high ( _t2_s45_2 )
                 				STATE_M _t2_s45_2
                 	_t2_s45_1:
                +
                +.if OLD_WRITE == 1
                +mw0 :
                +lsl TEMP_D_REG
00053e 0f44     +brcc mw1
00053f 1f77     +
000540 0f44     +ori SHIFT_REG_S , 1
000541 1f77     +ldi SHIFT_REG , ( 1 )
000542 7077     +rjmp mw2
000543 e5d4     +mw1 :
000544 e0c0     +ldi SHIFT_REG , 0x0
000545 0fc7     +sbrs SHIFT_REG_S , 0
000546 1dd0     +ldi SHIFT_REG , ( 1 << 4 )
000547 8128     +andi SHIFT_REG_S , ~ ( 1 )
                +mw2 :
                 				WRITE_DATA
                 	_t2_s45_2:			
                +
                +$ ms0 :
000548 90d0 00c0+lds TEMP1 , UCSRA
00054a fed5     +sbrs TEMP1 , UDRE
00054b c061     +rjmp _end_state
00054c 9320 00c6+sts UDR , SHIFT_REG
00054e 956a     +dec SHIFT_COUNT
00054f f771     +brne _t2_s45_1
                 				OUT_BIT_ SHIFT_REG , _t2_s45_1
                 				
                 	_t2_s46:	
                +
000550 9870     +cbi PORTE , WG
                 				RES_WG
                +
                +$ msw0 :
000551 90d0 00c0+lds TEMP1 , UCSRA
000553 fed5     +sbrs TEMP1 , UDRE
000554 cffc     +rjmp $ msw0
000555 9200 00c1+sts UCSRB , CONST00
                 				STOP_WRITE
                +
000557 efaa     +ldi XL , low ( _t2_s29 )
000558 e0b3     +ldi XH , high ( _t2_s29 )
000559 c053     +rjmp _end_state
                 				STATE_E _t2_s29
                 	_t2_s47:
                +
00055a 9200 0091+sts TCCR3B , CONST00
                 				STOP_CAPTURE
                +
00055c 6031     +ori S_REG , ( 1 << S_REG_BUSY )
                 				RES_S_REG_BIT  S_REG_BUSY 
                +
                +
00055d 9869     +cbi DDRE , INTRQ
                 				SET_INTRQ
00055e 7f5e      				andi FLAGS , ~( 1 << NEW_CMD )
                +
00055f e6a0     +ldi XL , low ( _t0 )
000560 e0b1     +ldi XH , high ( _t0 )
000561 c04b     +rjmp _end_state
                 			STATE_E _t0
                 
                 _start_state:
                +
000562 9bc5     +sbis TIFR3 , ICF3
000563 c049     +rjmp $ rdend
000564 9100 0096+lds TEMP , ICR3L
000566 9ac5     +sbi TIFR3 , ICF3
000567 2f10     +mov CURR_CAPT , TEMP
000568 191c     +sub CURR_CAPT , OLD_CAPT
000569 2ec0     +mov OLD_CAPT , TEMP
                +
00056a 311c     +cpi CURR_CAPT , LONG_PULSE
00056b f430     +brsh $ rdl
00056c 3114     +cpi CURR_CAPT , MED_PULSE
00056d f0f0     +brlo $ rds
00056e 2f02     +mov TEMP , SHIFT_REG
00056f 2f27     +mov SHIFT_REG , SHIFT_REG_S
000570 2f70     +mov SHIFT_REG_S , TEMP
000571 c00d     +rjmp $ rdm
                +$ rdl :
                +
000572 0f22     +lsl SHIFT_REG
                +.if 0 != 0
                +ori SHIFT_REG , 1
                +
                +cpi SHIFT_REG , 0xA1
                +brne $ sm5
                +cpi SHIFT_REG_S , 0x0A
                +brne $ sm6
                +ori FLAGS , ( 1 << SYNC )
                +rjmp $ sm7
                +$ sm5 :
                +.else 
                +
000573 956a     +
000574 f451     +
                +
000575 e160     +
000576 2f42     +
000577 6052     +
                +
000578 2fc4     +mov YL , TEMP_D_REG
000579 25c9     +eor YL , CRC_H
00057a e5d3     +ldi YH , high ( 2 * crchi ) + 0x40
00057b 8098     +ld CRC_H , Y
00057c 2498     +eor CRC_H , CRC_L
00057d 95da     +dec YH
00057e 8088     +ld CRC_L , Y
                +
                +.endif 
                +$ sm6 :
                +STORE 0 , SHIFT_REG , SHIFT_REG_S
                +$ rdm :
                +
00057f 0f77     +lsl SHIFT_REG_S
                +.if 0 != 0
                +ori SHIFT_REG_S , 1
                +
                +cpi SHIFT_REG_S , 0xA1
                +brne $ sm5
                +cpi SHIFT_REG , 0x0A
                +brne $ sm6
                +ori FLAGS , ( 1 << SYNC )
                +rjmp $ sm7
                +$ sm5 :
                +.else 
                +
000580 956a     +
000581 f451     +
                +
000582 e160     +
000583 2f47     +
000584 6052     +
                +
000585 2fc4     +mov YL , TEMP_D_REG
000586 25c9     +eor YL , CRC_H
000587 e5d3     +ldi YH , high ( 2 * crchi ) + 0x40
000588 8098     +ld CRC_H , Y
000589 2498     +eor CRC_H , CRC_L
00058a 95da     +dec YH
00058b 8088     +ld CRC_L , Y
                +
                +.endif 
                +$ sm6 :
                +STORE 0 , SHIFT_REG_S , SHIFT_REG
                +$ rds :
                +
00058c 0f22     +lsl SHIFT_REG
                +.if 0 != 0
                +ori SHIFT_REG , 1
                +
                +cpi SHIFT_REG , 0xA1
                +brne $ sm5
                +cpi SHIFT_REG_S , 0x0A
                +brne $ sm6
                +ori FLAGS , ( 1 << SYNC )
                +rjmp $ sm7
                +$ sm5 :
                +.else 
                +
00058d 956a     +
00058e f451     +
                +
00058f e160     +
000590 2f42     +
000591 6052     +
                +
000592 2fc4     +mov YL , TEMP_D_REG
000593 25c9     +eor YL , CRC_H
000594 e5d3     +ldi YH , high ( 2 * crchi ) + 0x40
000595 8098     +ld CRC_H , Y
000596 2498     +eor CRC_H , CRC_L
000597 95da     +dec YH
000598 8088     +ld CRC_L , Y
                +
                +.endif 
                +$ sm6 :
                +STORE 0 , SHIFT_REG , SHIFT_REG_S
                +
000599 0f77     +lsl SHIFT_REG_S
                +.if 1 != 0
00059a 6071     +ori SHIFT_REG_S , 1
                +
00059b 3a71     +cpi SHIFT_REG_S , 0xA1
00059c f421     +brne $ sm5
00059d 302a     +cpi SHIFT_REG , 0x0A
00059e f411     +brne $ sm6
00059f 6450     +ori FLAGS , ( 1 << SYNC )
0005a0 c002     +rjmp $ sm7
                +$ sm5 :
                +.else 
                +
                +
0005a1 956a     +
0005a2 f451     +
                +
0005a3 e160     +
0005a4 2f47     +
0005a5 6052     +
                +
0005a6 2fc4     +mov YL , TEMP_D_REG
0005a7 25c9     +eor YL , CRC_H
0005a8 e5d3     +ldi YH , high ( 2 * crchi ) + 0x40
0005a9 8098     +ld CRC_H , Y
0005aa 2498     +eor CRC_H , CRC_L
0005ab 95da     +dec YH
0005ac 8088     +ld CRC_L , Y
                +.endif 
                +$ sm6 :
                +dec SHIFT_COUNT
                +STORE 1 , SHIFT_REG_S , SHIFT_REG
                +$ rdend :
                 	    READ_BYTE
                 _end_state:	  	        
                +
0005ad 9b63     +sbis PINE , CLEAR
                 			CHECK_CLR
0005ae cace      				rjmp _warm_start			
                 
0005af ff50      			sbrs FLAGS , NEW_CMD
0005b0 c005      				rjmp calc_ip
                 			
0005b1 2d0f      			mov TEMP , TEMP_CMD
0005b2 7f00      			andi TEMP , 0b11110000
0005b3 3d00      			cpi TEMP , 0xD0
0005b4 f409      			brne  calc_ip
                 
0005b5 cb9e      			rjmp _break
                 		
                 calc_ip:	   
0005b6 ff52      			sbrs FLAGS , BREAK_IP
0005b7 c003      			rjmp calc_sreg
                +
0005b8 9bb0     +sbis TIFR1 , TOV1
                 			CHECK_IP						
0005b9 c001      			rjmp calc_sreg
0005ba cb99      			rjmp _break
                 calc_sreg:	   
0005bb b109      			in TEMP , PIND
                 ;			clt
                 ;			CHECK_CPRDY
                 ;				set
0005bc fb01      			bst TEMP , CPRDY
0005bd f937      			bld S_REG , S_REG_READY
                 			
0005be ff53      			sbrs FLAGS , CMD_1_TYPE
0005bf c012      			   rjmp no_1_type
                 			
0005c0 fb03      			bst TEMP , HLD
0005c1 f935      			bld S_REG , S_REG_HLD
                +
0005c2 9b65     +sbis PINE , HRDY
                 			CHECK_HRDY
                +
0005c3 7d3f     +andi S_REG , ~ ( 1 << S_REG_HLD )
                 				SET_S_REG_BIT  S_REG_HLD
                 ;			clt
                 ;			CHECK_IP_
                 ;				set  
0005c4 fb05      			bst TEMP , IP
0005c5 f931      			bld S_REG , S_REG_IP
                 			
                 ;			clt
                 ;			CHECK_TR00
                 ;				set
0005c6 fb00      			bst TEMP , TR00
0005c7 f932      			bld S_REG , S_REG_TR00
                 			
0005c8 94e8      			clt 
                +
0005c9 9962     +sbic PINE , WRPT
                 			CHECK_WRPT
0005ca 9468      			  set
0005cb f936      			bld S_REG , S_REG_WR_PR
                 
                 ;			rjmp end_calc_sreg
                 wait_clock:		
                +
0005cc 9bb9     +sbis TIFR2 , OCF2A
                 			CHECK_DELAY_4
0005cd cffe      				rjmp wait_clock	
0005ce ba17      			out TIFR2 , CONSTFF
0005cf 93af      			push XL
0005d0 93bf      			push XH
0005d1 9508      			ret
                 no_1_type:
0005d2 94e8      			clt
                +
0005d3 b109     +in TEMP , PIND
0005d4 ff07     +sbrs TEMP , DRQ
                 			CHECK_DRQ
0005d5 9468      				set
                 ;			bst TEMP , DRQ
0005d6 f931      			bld S_REG  , S_REG_DRQ
                 	
                 end_calc_sreg:
                 ;			sbrc FLAGS , SKIP_TIMER
                 ;				rjmp skip_time
                 ;check_time:
                 ;			lds TEMP , TCNT2
                 ;			cp TEMP , TIME
                 ;			breq check_time
                 ;			mov TIME , TEMP
                 ;skip_time:
                 ;		  ijmp
0005d7 93af      			push XL
0005d8 93bf      			push XH
0005d9 9508      			ret
                 
                 
                 _cmd_type_3:
                 	_t3_s01:
                +
0005da ef3f     +ser S_REG
                 		    	CLR_S_REG
                +
0005db 7f3e     +andi S_REG , ~ ( 1 << S_REG_BUSY )
                 				SET_S_REG_BIT  S_REG_BUSY 
                +
                +
0005dc 9a57     +sbi DDRD , DRQ
                 				RES_DRQ
                +
                +
0005dd 9a69     +sbi DDRE , INTRQ
                 				RES_INTRQ
                +
0005de eea1     +ldi XL , low ( _t3_s02 )
0005df e0b5     +ldi XH , high ( _t3_s02 )
0005e0 cfcc     +rjmp _end_state
                 				STATE_E _t3_s02   
                 	_t3_s02:
                +
0005e1 eea8     +ldi XL , low ( _t3_s03 )
0005e2 e0b5     +ldi XH , high ( _t3_s03 )
                 				STATE_M _t3_s03
                +
0005e3 9949     +sbic PIND , CPRDY
                 				CHECK_CPRDY
0005e4 cfc8      					rjmp _end_state
                +
0005e5 eeaf     +ldi XL , low ( _t3_s25 )
0005e6 e0b6     +ldi XH , high ( _t3_s25 )
0005e7 cfc5     +rjmp _end_state
                                 STATE_E _t3_s25
                 	_t3_s03:
                +
0005e8 9a5b     +sbi PORTD , HLD
                 				SET_HLD
                 	_t3_s04:
                +
0005e9 e1a3     +ldi XL , low ( _t3_s06 )
0005ea e0b6     +ldi XH , high ( _t3_s06 )
                 				STATE_M _t3_s06
0005eb fef2      				sbrs TEMP_CMD , 2
0005ec cfc0      					rjmp _end_state
0005ed e002      				ldi TEMP , 0x02
                +
0005ee ba18     +out TIFR3 , CONSTFF
0005ef 9200 0095+sts TCNT3H , CONST00
0005f1 9200 0094+sts TCNT3L , CONST00
0005f3 3000     +cpi TEMP , 0
0005f4 f411     +brne $ ma1
0005f5 e006     +ldi TEMP , 6 * KOEFF
0005f6 c009     +rjmp $ mae
                +$ ma1 :
0005f7 3001     +cpi TEMP , 1
0005f8 f411     +brne $ ma2
0005f9 e00c     +ldi TEMP , 12 * KOEFF
0005fa c005     +rjmp $ mae
                +$ ma2 :
0005fb 3002     +cpi TEMP , 2
0005fc f411     +brne $ ma3
0005fd e104     +ldi TEMP , 20 * KOEFF
0005fe c001     +rjmp $ mae
                +$ ma3 :
0005ff e10e     +ldi TEMP , 30 * KOEFF
                +$ mae :
000600 9300 0099+sts OCR3AH , TEMP
000602 9200 0098+sts OCR3AL , CONST00
000604 e00b     +ldi TEMP , ( 1 << WGM12 ) | ( 1 << CS11 ) | ( 1 << CS10 )
000605 9300 0091+sts TCCR3B , TEMP
                 				START_DELAY 
                +
000607 e0aa     +ldi XL , low ( _t3_s05 )
000608 e0b6     +ldi XH , high ( _t3_s05 )
000609 cfa3     +rjmp _end_state
                 				STATE_E _t3_s05
                 	_t3_s05:	
                +
00060a e0aa     +ldi XL , low ( _t3_s05 )
00060b e0b6     +ldi XH , high ( _t3_s05 )
                 				STATE_M _t3_s05
                +
00060c 9bc1     +sbis TIFR3 , OCF3A
                 				CHECK_DELAY
00060d cf9f      					rjmp _end_state
                +
00060e 9200 0091+sts TCCR3B , CONST00
                 				STOP_DELAY
                +
000610 e1a3     +ldi XL , low ( _t3_s06 )
000611 e0b6     +ldi XH , high ( _t3_s06 )
000612 cf9a     +rjmp _end_state
                 				STATE_E _t3_s06
                 	_t3_s06:	
                +
000613 e1a3     +ldi XL , low ( _t3_s06 )
000614 e0b6     +ldi XH , high ( _t3_s06 )
                 				STATE_M _t3_s06
                +
000615 9b65     +sbis PINE , HRDY
                 				CHECK_HRDY
000616 cf96      					rjmp _end_state
                +
000617 e1aa     +ldi XL , low ( _t3_s07 )
000618 e0b6     +ldi XH , high ( _t3_s07 )
000619 cf93     +rjmp _end_state
                 				STATE_E _t3_s07
                 	_t3_s07:				
                +
                +
                 	            SET_TR43
                +
00061a e1ad     +ldi XL , low ( _t3_s08 )
00061b e0b6     +ldi XH , high ( _t3_s08 )
00061c cf90     +rjmp _end_state
                 				STATE_E  _t3_s08
                 	_t3_s08:
                +
00061d e6a1     +ldi XL , low ( _t3_s17_0 )
00061e e0b6     +ldi XH , high ( _t3_s17_0 )
                 				STATE_M _t3_s17_0
00061f fef5      				sbrs TEMP_CMD , 5
000620 cf8c      					rjmp _end_state
000621 6150      				ori  FLAGS , ( 1 << READ_TR )
                +
000622 9a6e     +sbi DDRE , WF_DE
000623 9876     +cbi PORTE , WF_DE
                 				RES_WF_DE
000624 ef0f      				ldi TEMP , ( -1 )
                +
000625 9200 0081+sts TCCR1B , CONST00
000627 9200 0080+sts TCCR1A , CONST00
000629 9210 0085+sts TCNT1H , CONSTFF
00062b 9300 0084+sts TCNT1L , TEMP
00062d ba16     +out TIFR1 , CONSTFF
00062e e006     +ldi TEMP , ( 1 << CS12 ) | ( 1 << CS11 )
00062f 9300 0081+sts TCCR1B , TEMP
                +
                 				START_IP
                +
000631 e002     +ldi TEMP , 0x02
000632 9300 0091+sts TCCR3B , TEMP
                 				START_CAPTURE
                 	
                 	_t3_s09:
                +
000634 e3a6     +ldi XL , low ( _t3_s10 )
000635 e0b6     +ldi XH , high ( _t3_s10 )
                 				STATE_M _t3_s10
                 	_t3_s10:
                +
000636 9bb0     +sbis TIFR1 , TOV1
                 				CHECK_IP
000637 cf75      					rjmp _end_state
000638 e160      				ldi SHIFT_COUNT , 16
                 ;				ori FLAGS  , ( 1 << IP_R )
                +
000639 9200 0081+sts TCCR1B , CONST00
                 				STOP_IP
00063b ef0f      				ldi TEMP , ( -1 )
                +
00063c 9200 0081+sts TCCR1B , CONST00
00063e 9200 0080+sts TCCR1A , CONST00
000640 9210 0085+sts TCNT1H , CONSTFF
000642 9300 0084+sts TCNT1L , TEMP
000644 ba16     +out TIFR1 , CONSTFF
000645 e006     +ldi TEMP , ( 1 << CS12 ) | ( 1 << CS11 )
000646 9300 0081+sts TCCR1B , TEMP
                +
                 				START_IP 
                 	_t3_s11:		
                +
000648 e5a0     +ldi XL , low ( _t3_s12 )
000649 e0b6     +ldi XH , high ( _t3_s12 )
                 				STATE_M _t3_s12
                +
00064a 9bb0     +sbis TIFR1 , TOV1
                 				CHECK_IP
00064b cf16      					rjmp _start_state
00064c 7e5f      				andi FLAGS , ~( 1 << READ_TR ) 
                +
00064d eeaf     +ldi XL , low ( _t3_s25 )
00064e e0b6     +ldi XH , high ( _t3_s25 )
00064f cf5d     +rjmp _end_state
                 				STATE_E _t3_s25
                 	_t3_s12:        
                +
000650 e4a8     +ldi XL , low ( _t3_s11 )
000651 e0b6     +ldi XH , high ( _t3_s11 )
                 				STATE_M _t3_s11
                 	;			READ_BYTE 
000652 ff51      				sbrs FLAGS , S_D_R
000653 cf0e      					rjmp _start_state	
000654 7f5d      				andi  FLAGS , ~( 1 << S_D_R )
                 	_t3_s13:		
                +
000655 e5ab     +ldi XL , low ( _t3_s14 )
000656 e0b6     +ldi XH , high ( _t3_s14 )
                 				STATE_M _t3_s14
                +
000657 b109     +in TEMP , PIND
000658 ff07     +sbrs TEMP , DRQ
                 				CHECK_DRQ
000659 cf08      					rjmp _start_state
                +
00065a 7f3b     +andi S_REG , ~ ( 1 << S_REG_DATA_LOST )
                 				SET_S_REG_BIT  S_REG_DATA_LOST 
                 	_t3_s14:
                 	_t3_s15:
00065b 2e74      				mov DAT_REG , TEMP_D_REG
00065c 9470      				com DAT_REG
                +
                +
00065d 9857     +cbi DDRD , DRQ
                 				SET_DRQ
                 	_t3_s16:
                +
00065e e4a8     +ldi XL , low ( _t3_s11 )
00065f e0b6     +ldi XH , high ( _t3_s11 )
                 				STATE_M _t3_s11
000660 cf01      				rjmp _start_state
                 	_t3_s17_0:	
000661 ef0b      				ldi TEMP , ( -5 )
                +
000662 9200 0081+sts TCCR1B , CONST00
000664 9200 0080+sts TCCR1A , CONST00
000666 9210 0085+sts TCNT1H , CONSTFF
000668 9300 0084+sts TCNT1L , TEMP
00066a ba16     +out TIFR1 , CONSTFF
00066b e006     +ldi TEMP , ( 1 << CS12 ) | ( 1 << CS11 )
00066c 9300 0081+sts TCCR1B , TEMP
                +
                 				START_IP  
                +
00066e e002     +ldi TEMP , 0x02
00066f 9300 0091+sts TCCR3B , TEMP
                 				START_CAPTURE
                +
000671 e7a4     +ldi XL , low ( _t3_s17 )
000672 e0b6     +ldi XH , high ( _t3_s17 )
000673 cf39     +rjmp _end_state
                 				STATE_E _t3_s17
                 	_t3_s17:
                +
000674 e7ab     +ldi XL , low ( _t3_s18 )
000675 e0b6     +ldi XH , high ( _t3_s18 )
                                 STATE_M _t3_s18
                +
000676 9bb0     +sbis TIFR1 , TOV1
                 				CHECK_IP 
000677 cf35      					rjmp _end_state
                +
000678 eeaf     +ldi XL , low ( _t3_s25 )
000679 e0b6     +ldi XH , high ( _t3_s25 )
00067a cf32     +rjmp _end_state
                 				STATE_E _t3_s25
                 	_t3_s18:    
                +
00067b e7a4     +ldi XL , low ( _t3_s17 )
00067c e0b6     +ldi XH , high ( _t3_s17 )
                 	            STATE_M _t3_s17
                +
00067d e7a4     +ldi XL , low ( _t3_s17 )
00067e e0b6     +ldi XH , high ( _t3_s17 )
00067f ff56     +sbrs FLAGS , SYNC
000680 cee1     +rjmp _start_state
000681 7b5d     +andi FLAGS , ~ ( ( 1 << SYNC ) | ( 1 << S_D_R ) )
                +
                +
                +
                +
                 				WAIT_SYNC_A1  _t3_s17
                +
000682 eb04     +ldi TEMP , low ( 0xCDB4 )
000683 2e80     +mov CRC_L , TEMP
000684 ec0d     +ldi TEMP , high ( 0xCDB4 )
000685 2e90     +mov CRC_H , TEMP
                 				INI_CRC
                 	_t3_s19:
                +
000686 e8a6     +ldi XL , low ( _t3_s19 )
000687 e0b6     +ldi XH , high ( _t3_s19 )
000688 ff51     +sbrs FLAGS , S_D_R
000689 ced8     +rjmp _start_state
00068a 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R 	_t3_s19
00068b 3f4e      				cpi TEMP_D_REG  , 0xFE
00068c f019      				breq _t3_s19_1
                +
00068d e7a4     +ldi XL , low ( _t3_s17 )
00068e e0b6     +ldi XH , high ( _t3_s17 )
00068f cf1d     +rjmp _end_state
                 				STATE_E _t3_s17
                 	_t3_s19_1:
                +
000690 e9a0     +ldi XL , low ( _t3_s19_1 )
000691 e0b6     +ldi XH , high ( _t3_s19_1 )
000692 ff51     +sbrs FLAGS , S_D_R
000693 cece     +rjmp _start_state
000694 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R 	_t3_s19_1
000695 9540      				com TEMP_D_REG
000696 2e64      				mov SECT_REG , TEMP_D_REG
000697 2e74      				mov	DAT_REG , TEMP_D_REG
                +
                +
000698 9857     +cbi DDRD , DRQ
                 				SET_DRQ
                +
000699 e9ac     +ldi XL , low ( _t3_s19_2 )
00069a e0b6     +ldi XH , high ( _t3_s19_2 )
00069b cf11     +rjmp _end_state
                 				STATE_E _t3_s19_2	
                 	_t3_s19_2:
                +
00069c e9ac     +ldi XL , low ( _t3_s19_2 )
00069d e0b6     +ldi XH , high ( _t3_s19_2 )
00069e ff51     +sbrs FLAGS , S_D_R
00069f cec2     +rjmp _start_state
0006a0 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R 	_t3_s19_2
0006a1 2e74      				mov	DAT_REG , TEMP_D_REG
0006a2 9470      				com DAT_REG
                +
                +
0006a3 9857     +cbi DDRD , DRQ
                 				SET_DRQ
                +
0006a4 eaa7     +ldi XL , low ( _t3_s19_3 )
0006a5 e0b6     +ldi XH , high ( _t3_s19_3 )
0006a6 cf06     +rjmp _end_state
                 				STATE_E _t3_s19_3	
                 	_t3_s19_3:
                +
0006a7 eaa7     +ldi XL , low ( _t3_s19_3 )
0006a8 e0b6     +ldi XH , high ( _t3_s19_3 )
0006a9 ff51     +sbrs FLAGS , S_D_R
0006aa ceb7     +rjmp _start_state
0006ab 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R 	_t3_s19_3
0006ac 2e74      				mov	DAT_REG , TEMP_D_REG
0006ad 9470      				com DAT_REG
                +
                +
0006ae 9857     +cbi DDRD , DRQ
                 				SET_DRQ
                +
0006af eba2     +ldi XL , low ( _t3_s19_4 )
0006b0 e0b6     +ldi XH , high ( _t3_s19_4 )
0006b1 cefb     +rjmp _end_state
                 				STATE_E _t3_s19_4	
                 	_t3_s19_4:				
                +
0006b2 eba2     +ldi XL , low ( _t3_s19_4 )
0006b3 e0b6     +ldi XH , high ( _t3_s19_4 )
0006b4 ff51     +sbrs FLAGS , S_D_R
0006b5 ceac     +rjmp _start_state
0006b6 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R 	_t3_s19_4
0006b7 2e74      				mov	DAT_REG , TEMP_D_REG
0006b8 9470      				com DAT_REG
                +
                +
0006b9 9857     +cbi DDRD , DRQ
                 				SET_DRQ
                +
0006ba ebad     +ldi XL , low ( _t3_s20 )
0006bb e0b6     +ldi XH , high ( _t3_s20 )
0006bc cef0     +rjmp _end_state
                 				STATE_E _t3_s20	
                 	_t3_s20:
                 	_t3_s21:
                 	_t3_s22:
                 	_t3_s23:
                 	_t3_s24:							
                +
0006bd ebad     +ldi XL , low ( _t3_s24 )
0006be e0b6     +ldi XH , high ( _t3_s24 )
0006bf ff51     +sbrs FLAGS , S_D_R
0006c0 cea1     +rjmp _start_state
0006c1 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R  _t3_s24
0006c2 2e74      				mov	DAT_REG , TEMP_D_REG
0006c3 9470      				com DAT_REG
                +
                +
0006c4 9857     +cbi DDRD , DRQ
                 				SET_DRQ
                 	_t3_s24_1:				
                +
0006c5 eca5     +ldi XL , low ( _t3_s24_1 )
0006c6 e0b6     +ldi XH , high ( _t3_s24_1 )
0006c7 ff51     +sbrs FLAGS , S_D_R
0006c8 ce99     +rjmp _start_state
0006c9 7f5d     +andi FLAGS , ~ ( 1 << S_D_R )
                 				WAIT_SHIFT_R  _t3_s24_1
0006ca 2e74      				mov	DAT_REG , TEMP_D_REG
0006cb 9470      				com DAT_REG
                +
                +
0006cc 9857     +cbi DDRD , DRQ
                 				SET_DRQ
0006cd 2898      	            or CRC_H , CRC_L
0006ce f021      				breq _t3_s24_3
                 	_t3_s24_2:
                +
0006cf 7f37     +andi S_REG , ~ ( 1 << S_REG_CRC_ERR )
                 	            SET_S_REG_BIT  S_REG_CRC_ERR 
                +
0006d0 eda7     +ldi XL , low ( _t3_s24_4 )
0006d1 e0b6     +ldi XH , high ( _t3_s24_4 )
0006d2 ceda     +rjmp _end_state
                 				STATE_E _t3_s24_4 
                 
                 	_t3_s24_3:		
                +
0006d3 6038     +ori S_REG , ( 1 << S_REG_CRC_ERR )
                 				RES_S_REG_BIT  S_REG_CRC_ERR 
                +
0006d4 eda7     +ldi XL , low ( _t3_s24_4 )
0006d5 e0b6     +ldi XH , high ( _t3_s24_4 )
0006d6 ced6     +rjmp _end_state
                 				STATE_E _t3_s24_4
                     _t3_s24_4:
0006d7 e001             			ldi TEMP , 1
                +
0006d8 9200 00b1+sts TCCR2B , CONST00
0006da 9300 00b3+sts OCR2A , TEMP
0006dc e002     +ldi TEMP , 2
0006dd 9300 00b0+sts TCCR2A , TEMP
0006df 9200 00b2+sts TCNT2 , CONST00
0006e1 ba17     +out TIFR2 , CONSTFF
0006e2 e006     +ldi TEMP , 6
0006e3 9300 00b1+sts TCCR2B , TEMP
                +
                 				START_DELAY_32
                +
0006e5 eea8     +ldi XL , low ( _t3_s24_5 )
0006e6 e0b6     +ldi XH , high ( _t3_s24_5 )
0006e7 cec5     +rjmp _end_state
                 				STATE_E _t3_s24_5
                     _t3_s24_5:
                +
0006e8 9bb9     +sbis TIFR2 , OCF2A
                 	            CHECK_DELAY_32
0006e9 cec3      					rjmp _end_state
                +
0006ea 9200 00b1+sts TCCR2B , CONST00
                 				STOP_DELAY_32 	    
                +
0006ec eeaf     +ldi XL , low ( _t3_s25 )
0006ed e0b6     +ldi XH , high ( _t3_s25 )
0006ee cebe     +rjmp _end_state
                 				STATE_E _t3_s25
                 	_t3_s25:
                +
0006ef 986e     +cbi DDRE , WF_DE
0006f0 9a76     +sbi PORTE , WF_DE
                 				SET_WF_DE
                +
0006f1 9200 0091+sts TCCR3B , CONST00
                 				STOP_CAPTURE
                +
0006f3 6031     +ori S_REG , ( 1 << S_REG_BUSY )
                 				RES_S_REG_BIT  S_REG_BUSY 
                +
                +
0006f4 9869     +cbi DDRE , INTRQ
                 	      		SET_INTRQ
0006f5 7f5e      				andi FLAGS , ~( 1 << NEW_CMD )
                +
0006f6 e6a0     +ldi XL , low ( _t0 )
0006f7 e0b1     +ldi XH , high ( _t0 )
0006f8 ceb4     +rjmp _end_state
                 			STATE_E _t0
                 
                 
                 _cmd_type_4:
                 _t4_s01:
                +
0006f9 ef3f     +ser S_REG
                 _t4_s02:	    CLR_S_REG
                +
0006fa 7f3e     +andi S_REG , ~ ( 1 << S_REG_BUSY )
                 				SET_S_REG_BIT  S_REG_BUSY
                +
                +
0006fb 9a57     +sbi DDRD , DRQ
                 				RES_DRQ
                +
                +
0006fc 9a69     +sbi DDRE , INTRQ
                 				RES_INTRQ
                +
0006fd e0a0     +ldi XL , low ( _t4_s03 )
0006fe e0b7     +ldi XH , high ( _t4_s03 )
0006ff cead     +rjmp _end_state
                 				STATE_E _t4_s03  
                 _t4_s03:    
                +
000700 e0a7     +ldi XL , low ( _t4_s04 )
000701 e0b7     +ldi XH , high ( _t4_s04 )
                 				STATE_M _t4_s04
                +
000702 9949     +sbic PIND , CPRDY
                 				CHECK_CPRDY
000703 cea9      					rjmp _end_state
                +
000704 e3ae     +ldi XL , low ( _t4_s47 )
000705 e0b8     +ldi XH , high ( _t4_s47 )
000706 cea6     +rjmp _end_state
                                 STATE_E _t4_s47
                 _t4_s04:
                +
000707 9a5b     +sbi PORTD , HLD
                 				SET_HLD
                 _t4_s05:
                +
000708 e3a2     +ldi XL , low ( _t4_s07 )
000709 e0b7     +ldi XH , high ( _t4_s07 )
                 				STATE_M _t4_s07
00070a fef2      				sbrs TEMP_CMD , 2
00070b cea1      					rjmp _end_state
                 				
00070c e002      				ldi TEMP,0x02
                +
00070d ba18     +out TIFR3 , CONSTFF
00070e 9200 0095+sts TCNT3H , CONST00
000710 9200 0094+sts TCNT3L , CONST00
000712 3000     +cpi TEMP , 0
000713 f411     +brne $ ma1
000714 e006     +ldi TEMP , 6 * KOEFF
000715 c009     +rjmp $ mae
                +$ ma1 :
000716 3001     +cpi TEMP , 1
000717 f411     +brne $ ma2
000718 e00c     +ldi TEMP , 12 * KOEFF
000719 c005     +rjmp $ mae
                +$ ma2 :
00071a 3002     +cpi TEMP , 2
00071b f411     +brne $ ma3
00071c e104     +ldi TEMP , 20 * KOEFF
00071d c001     +rjmp $ mae
                +$ ma3 :
00071e e10e     +ldi TEMP , 30 * KOEFF
                +$ mae :
00071f 9300 0099+sts OCR3AH , TEMP
000721 9200 0098+sts OCR3AL , CONST00
000723 e00b     +ldi TEMP , ( 1 << WGM12 ) | ( 1 << CS11 ) | ( 1 << CS10 )
000724 9300 0091+sts TCCR3B , TEMP
                 				START_DELAY 
                +
000726 e2a9     +ldi XL , low ( _t4_s06 )
000727 e0b7     +ldi XH , high ( _t4_s06 )
000728 ce84     +rjmp _end_state
                 				STATE_E _t4_s06
                 _t4_s06:	
                +
000729 e2a9     +ldi XL , low ( _t4_s06 )
00072a e0b7     +ldi XH , high ( _t4_s06 )
                 				STATE_M _t4_s06
                +
00072b 9bc1     +sbis TIFR3 , OCF3A
                 				CHECK_DELAY
00072c ce80      					rjmp _end_state
                +
00072d 9200 0091+sts TCCR3B , CONST00
                 				STOP_DELAY
                +
00072f e3a2     +ldi XL , low ( _t4_s07 )
000730 e0b7     +ldi XH , high ( _t4_s07 )
000731 ce7b     +rjmp _end_state
                 				STATE_E _t4_s07
                 _t4_s07:	
                +
000732 e3a2     +ldi XL , low ( _t4_s07 )
000733 e0b7     +ldi XH , high ( _t4_s07 )
                 				STATE_M _t4_s07
                +
000734 9b65     +sbis PINE , HRDY
                 				CHECK_HRDY
000735 ce77      					rjmp _end_state
                +
000736 e3a9     +ldi XL , low ( _t4_s08 )
000737 e0b7     +ldi XH , high ( _t4_s08 )
000738 ce74     +rjmp _end_state
                 				STATE_E _t4_s08
                 _t4_s08:				
                +
000739 986e     +cbi DDRE , WF_DE
00073a 9a76     +sbi PORTE , WF_DE
                 				SET_WF_DE
00073b 2d05      				mov TEMP , TR_REG
00073c 9500      				com TEMP
00073d 320b      				cpi TEMP , 43
00073e f41a      				brpl _t4_s09_0
                +
                +
                                 RES_TR43
                +
00073f e4a5     +ldi XL , low ( _t4_s09 )
000740 e0b7     +ldi XH , high ( _t4_s09 )
000741 ce6b     +rjmp _end_state
                 				STATE_E  _t4_s09
                 _t4_s09_0:
                +
                +
                 				SET_TR43
                +
000742 e4a5     +ldi XL , low ( _t4_s09 )
000743 e0b7     +ldi XH , high ( _t4_s09 )
000744 ce68     +rjmp _end_state
                 				STATE_E _t4_s09
                 _t4_s09:       
                +
000745 e4ad     +ldi XL , low ( _t4_s10 )
000746 e0b7     +ldi XH , high ( _t4_s10 )
                  				STATE_M _t4_s10
                +
000747 9962     +sbic PINE , WRPT
                 				CHECK_WRPT
000748 ce64      					rjmp _end_state
                +
000749 7b3f     +andi S_REG , ~ ( 1 << S_REG_WR_PR )
                 				SET_S_REG_BIT  S_REG_WR_PR 
                +
00074a e3ae     +ldi XL , low ( _t4_s47 )
00074b e0b8     +ldi XH , high ( _t4_s47 )
00074c ce60     +rjmp _end_state
                 				STATE_E _t4_s47
                 _t4_s10:
                +
                +
00074d 9857     +cbi DDRD , DRQ
                 				SET_DRQ
00074e e00c      				ldi TEMP , 12
                +
00074f 9200 00b1+sts TCCR2B , CONST00
000751 9300 00b3+sts OCR2A , TEMP
000753 e002     +ldi TEMP , 2
000754 9300 00b0+sts TCCR2A , TEMP
000756 9200 00b2+sts TCNT2 , CONST00
000758 ba17     +out TIFR2 , CONSTFF
000759 e006     +ldi TEMP , 6
00075a 9300 00b1+sts TCCR2B , TEMP
                +
                 				START_DELAY_32
                +
00075c e5af     +ldi XL , low ( _t4_s11 )
00075d e0b7     +ldi XH , high ( _t4_s11 )
00075e ce4e     +rjmp _end_state
                 				STATE_E _t4_s11
                 _t4_s11:
                +
00075f 9bb9     +sbis TIFR2 , OCF2A
                 				CHECK_DELAY_32
000760 ce4c      					rjmp _end_state
                +
000761 9200 00b1+sts TCCR2B , CONST00
                 				STOP_DELAY_32
                +
000763 e6a6     +ldi XL , low ( _t4_s12 )
000764 e0b7     +ldi XH , high ( _t4_s12 )
000765 ce47     +rjmp _end_state
                 				STATE_E _t4_s12
                 
                +
000766 e6af     +ldi XL , low ( _t4_s13 )
000767 e0b7     +ldi XH , high ( _t4_s13 )
                 _t4_s12:		STATE_M _t4_s13
                +
000768 b109     +in TEMP , PIND
000769 ff07     +sbrs TEMP , DRQ
                 				CHECK_DRQ
00076a ce42      					rjmp _end_state
                +
00076b 7f3b     +andi S_REG , ~ ( 1 << S_REG_DATA_LOST )
                 				SET_S_REG_BIT  S_REG_DATA_LOST 
                +
00076c e3ae     +ldi XL , low ( _t4_s47 )
00076d e0b8     +ldi XH , high ( _t4_s47 )
00076e ce3e     +rjmp _end_state
                 				STATE_E _t4_s47
                 _t4_s13:		
                 ;				STATE_M _t4_s13_0
                 ;				CHECK_IP
                 ;					rjmp _end_state
                 ;				STATE_E _t4_s13	
00076f ef0f      				ldi TEMP , ( -1 )
                +
000770 9200 0081+sts TCCR1B , CONST00
000772 9200 0080+sts TCCR1A , CONST00
000774 9210 0085+sts TCNT1H , CONSTFF
000776 9300 0084+sts TCNT1L , TEMP
000778 ba16     +out TIFR1 , CONSTFF
000779 e006     +ldi TEMP , ( 1 << CS12 ) | ( 1 << CS11 )
00077a 9300 0081+sts TCCR1B , TEMP
                +
                 				START_IP
                 _t4_s13_0:
                +
00077c e7ac     +ldi XL , low ( _t4_s13_0 )
00077d e0b7     +ldi XH , high ( _t4_s13_0 )
                 				STATE_M _t4_s13_0
                +
00077e 9bb0     +sbis TIFR1 , TOV1
                 				CHECK_IP
00077f ce2d      					rjmp _end_state
                 ;				ori FLAGS , (1 << IP_R )
000780 ef0f      				ldi TEMP , (-1 )
                +
000781 9200 0081+sts TCCR1B , CONST00
000783 9200 0080+sts TCCR1A , CONST00
000785 9210 0085+sts TCNT1H , CONSTFF
000787 9300 0084+sts TCNT1L , TEMP
000789 ba16     +out TIFR1 , CONSTFF
00078a e006     +ldi TEMP , ( 1 << CS12 ) | ( 1 << CS11 )
00078b 9300 0081+sts TCCR1B , TEMP
                +
                 				START_IP 
                +
00078d 9a70     +sbi PORTE , WG
                 				SET_WG
                +
00078e 986e     +cbi DDRE , WF_DE
00078f 9a76     +sbi PORTE , WF_DE
                 				SET_WF_DE
                +
000790 e008     +ldi TEMP , ( 1 << TXEN )
000791 9300 00c1+sts UCSRB , TEMP
                 				START_WRITE
                +
000793 e9a6     +ldi XL , low ( _t4_s14 )
000794 e0b7     +ldi XH , high ( _t4_s14 )
000795 ce17     +rjmp _end_state
                 				STATE_E _t4_s14
                 		
000796 2d47      _t4_s14:		mov TEMP_D_REG , DAT_REG 
000797 9540      				com TEMP_D_REG
                 _t4_s15:
                +
                +
000798 9857     +cbi DDRD , DRQ
                 				SET_DRQ
                 _t4_s16:
                +
000799 eca2     +ldi XL , low ( _t4_s24 )
00079a e0b7     +ldi XH , high ( _t4_s24 )
00079b ce11     +rjmp _end_state
                 				STATE_E _t4_s24
                 _t4_s17:
                 _t4_s18:
                 _t4_s19:
                 _t4_s20:
                 _t4_s21:	
                +
00079c eaa3     +ldi XL , low ( _t4_s22 )
00079d e0b7     +ldi XH , high ( _t4_s22 )
                 				STATE_M _t4_s22
                +
00079e 9bb0     +sbis TIFR1 , TOV1
                 				CHECK_IP
00079f ce0d      					rjmp _end_state
                +
0007a0 e3ae     +ldi XL , low ( _t4_s47 )
0007a1 e0b8     +ldi XH , high ( _t4_s47 )
0007a2 ce0a     +rjmp _end_state
                 				STATE_E _t4_s47
                 _t4_s22:		
                +
0007a3 e9a6     +ldi XL , low ( _t4_s14 )
0007a4 e0b7     +ldi XH , high ( _t4_s14 )
                 				STATE_M _t4_s14
                +
0007a5 b109     +in TEMP , PIND
0007a6 ff07     +sbrs TEMP , DRQ
                 				CHECK_DRQ
0007a7 ce05      					rjmp _end_state
                +
0007a8 7f3b     +andi S_REG , ~ ( 1 << S_REG_DATA_LOST )
                 				SET_S_REG_BIT  S_REG_DATA_LOST 
0007a9 2744      				clr TEMP_D_REG
                 						
0007aa e064      				ldi SHIFT_COUNT , BIT_COUNT
                +
0007ab eba7     +ldi XL , low ( _t4_s22_2 )
0007ac e0b7     +ldi XH , high ( _t4_s22_2 )
                 				STATE_M _t4_s22_2
                 	_t4_s22_1:
                +
                +.if OLD_WRITE == 1
                +mw0 :
                +lsl TEMP_D_REG
0007ad 0f44     +brcc mw1
0007ae 1f77     +
0007af 0f44     +ori SHIFT_REG_S , 1
0007b0 1f77     +ldi SHIFT_REG , ( 1 )
0007b1 7077     +rjmp mw2
0007b2 e5d4     +mw1 :
0007b3 e0c0     +ldi SHIFT_REG , 0x0
0007b4 0fc7     +sbrs SHIFT_REG_S , 0
0007b5 1dd0     +ldi SHIFT_REG , ( 1 << 4 )
0007b6 8128     +andi SHIFT_REG_S , ~ ( 1 )
                +mw2 :
                 				WRITE_DATA
                 	_t4_s22_2:			
                +
                +$ ms0 :
0007b7 90d0 00c0+lds TEMP1 , UCSRA
0007b9 fed5     +sbrs TEMP1 , UDRE
0007ba cdf2     +rjmp _end_state
0007bb 9320 00c6+sts UDR , SHIFT_REG
0007bd 956a     +dec SHIFT_COUNT
0007be f771     +brne _t4_s22_1
                 				OUT_BIT_ SHIFT_REG , _t4_s22_1
                +
0007bf e9ac     +ldi XL , low ( _t4_s21 )
0007c0 e0b7     +ldi XH , high ( _t4_s21 )
0007c1 cdeb     +rjmp _end_state
                 				STATE_E _t4_s21
                 _t4_s23:
0007c2 3f45      _t4_s24:		cpi TEMP_D_REG , 0xF5
0007c3 f4b1      				brne _t4_s25
                 				
0007c4 e064      				ldi SHIFT_COUNT , BIT_COUNT
0007c5 e5d4      				ldi YH , high( A1_table * 2 ) + 0x40
0007c6 e0c8      				ldi YL , low( A1_table  * 2 )
0007c7 e071      				ldi SHIFT_REG_S , 1
                +
0007c8 ecab     +ldi XL , low ( _t4_s24_2 )
0007c9 e0b7     +ldi XH , high ( _t4_s24_2 )
                 				STATE_M _t4_s24_2
                 	_t4_s24_1:
0007ca 9129      				ld  SHIFT_REG , Y+
                 	_t4_s24_2:							
                +
                +$ ms0 :
0007cb 90d0 00c0+lds TEMP1 , UCSRA
0007cd fed5     +sbrs TEMP1 , UDRE
0007ce cdde     +rjmp _end_state
0007cf 9320 00c6+sts UDR , SHIFT_REG
0007d1 956a     +dec SHIFT_COUNT
0007d2 f7b9     +brne _t4_s24_1
                 				OUT_BIT_ SHIFT_REG , _t4_s24_1
                 
                +
0007d3 eb04     +ldi TEMP , low ( 0xCDB4 )
0007d4 2e80     +mov CRC_L , TEMP
0007d5 ec0d     +ldi TEMP , high ( 0xCDB4 )
0007d6 2e90     +mov CRC_H , TEMP
                 				INI_CRC
                +
0007d7 e9ac     +ldi XL , low ( _t4_s21 )
0007d8 e0b7     +ldi XH , high ( _t4_s21 )
0007d9 cdd3     +rjmp _end_state
                 				STATE_E _t4_s21
                 _t4_s25:
0007da 3f46      				cpi TEMP_D_REG , 0xF6
0007db f491      				brne _t4_s26
                 				
0007dc e064      				ldi SHIFT_COUNT , BIT_COUNT
0007dd e5d4      				ldi YH , high( C2_table * 2 ) + 0x40
0007de e0cc      				ldi YL , low( C2_table  * 2 )
0007df e070      				ldi SHIFT_REG_S , 0
                +
0007e0 eea3     +ldi XL , low ( _t4_s25_2 )
0007e1 e0b7     +ldi XH , high ( _t4_s25_2 )
                 				STATE_M _t4_s25_2
                 	_t4_s25_1:
0007e2 9129      				ld  SHIFT_REG , Y+
                 	_t4_s25_2:							
                +
                +$ ms0 :
0007e3 90d0 00c0+lds TEMP1 , UCSRA
0007e5 fed5     +sbrs TEMP1 , UDRE
0007e6 cdc6     +rjmp _end_state
0007e7 9320 00c6+sts UDR , SHIFT_REG
0007e9 956a     +dec SHIFT_COUNT
0007ea f7b9     +brne _t4_s25_1
                 				OUT_BIT_ SHIFT_REG , _t4_s25_1
                +
0007eb e9ac     +ldi XL , low ( _t4_s21 )
0007ec e0b7     +ldi XH , high ( _t4_s21 )
0007ed cdbf     +rjmp _end_state
                 				STATE_E _t4_s21
                 _t4_s26:
0007ee 3f47      				cpi TEMP_D_REG , 0xF7
0007ef f579      				brne _t4_s27
0007f0 2d49      				mov TEMP_D_REG , CRC_H
                 				
0007f1 e064      				ldi SHIFT_COUNT , BIT_COUNT
                +
0007f2 efae     +ldi XL , low ( _t4_s26_0_2 )
0007f3 e0b7     +ldi XH , high ( _t4_s26_0_2 )
                 				STATE_M _t4_s26_0_2
                 	_t4_s26_0_1:
                +
                +.if OLD_WRITE == 1
                +mw0 :
                +lsl TEMP_D_REG
0007f4 0f44     +brcc mw1
0007f5 1f77     +
0007f6 0f44     +ori SHIFT_REG_S , 1
0007f7 1f77     +ldi SHIFT_REG , ( 1 )
0007f8 7077     +rjmp mw2
0007f9 e5d4     +mw1 :
0007fa e0c0     +ldi SHIFT_REG , 0x0
0007fb 0fc7     +sbrs SHIFT_REG_S , 0
0007fc 1dd0     +ldi SHIFT_REG , ( 1 << 4 )
0007fd 8128     +andi SHIFT_REG_S , ~ ( 1 )
                +mw2 :
                 				WRITE_DATA
                 	_t4_s26_0_2:			
                +
                +$ ms0 :
0007fe 90d0 00c0+lds TEMP1 , UCSRA
000800 fed5     +sbrs TEMP1 , UDRE
000801 cdab     +rjmp _end_state
000802 9320 00c6+sts UDR , SHIFT_REG
000804 956a     +dec SHIFT_COUNT
000805 f771     +brne _t4_s26_0_1
                 				OUT_BIT_ SHIFT_REG , _t4_s26_0_1
                 	
000806 2d48      				mov TEMP_D_REG , CRC_L
                 							
000807 e064      				ldi SHIFT_COUNT , BIT_COUNT
                +
000808 e1a4     +ldi XL , low ( _t4_s26_2 )
000809 e0b8     +ldi XH , high ( _t4_s26_2 )
                 				STATE_M _t4_s26_2
                 	_t4_s26_1:
                +
                +.if OLD_WRITE == 1
                +mw0 :
                +lsl TEMP_D_REG
00080a 0f44     +brcc mw1
00080b 1f77     +
00080c 0f44     +ori SHIFT_REG_S , 1
00080d 1f77     +ldi SHIFT_REG , ( 1 )
00080e 7077     +rjmp mw2
00080f e5d4     +mw1 :
000810 e0c0     +ldi SHIFT_REG , 0x0
000811 0fc7     +sbrs SHIFT_REG_S , 0
000812 1dd0     +ldi SHIFT_REG , ( 1 << 4 )
000813 8128     +andi SHIFT_REG_S , ~ ( 1 )
                +mw2 :
                 				WRITE_DATA
                 	_t4_s26_2:			
                +
                +$ ms0 :
000814 90d0 00c0+lds TEMP1 , UCSRA
000816 fed5     +sbrs TEMP1 , UDRE
000817 cd95     +rjmp _end_state
000818 9320 00c6+sts UDR , SHIFT_REG
00081a 956a     +dec SHIFT_COUNT
00081b f771     +brne _t4_s26_1
                 				OUT_BIT_ SHIFT_REG , _t4_s26_1
                +
00081c e9ac     +ldi XL , low ( _t4_s21 )
00081d e0b7     +ldi XH , high ( _t4_s21 )
00081e cd8e     +rjmp _end_state
                 				STATE_E _t4_s21 
                 	_t4_s27:
                +
00081f 2fc4     +mov YL , TEMP_D_REG
000820 25c9     +eor YL , CRC_H
000821 e5d3     +ldi YH , high ( 2 * crchi ) + 0x40
000822 8098     +ld CRC_H , Y
000823 2498     +eor CRC_H , CRC_L
000824 95da     +dec YH
000825 8088     +ld CRC_L , Y
                 				CALC_CRC TEMP_D_REG
000826 e064      				ldi SHIFT_COUNT , BIT_COUNT
                +
000827 e3a3     +ldi XL , low ( _t4_s27_2 )
000828 e0b8     +ldi XH , high ( _t4_s27_2 )
                 				STATE_M _t4_s27_2
                 	_t4_s27_1:
                +
                +.if OLD_WRITE == 1
                +mw0 :
                +lsl TEMP_D_REG
000829 0f44     +brcc mw1
00082a 1f77     +
00082b 0f44     +ori SHIFT_REG_S , 1
00082c 1f77     +ldi SHIFT_REG , ( 1 )
00082d 7077     +rjmp mw2
00082e e5d4     +mw1 :
00082f e0c0     +ldi SHIFT_REG , 0x0
000830 0fc7     +sbrs SHIFT_REG_S , 0
000831 1dd0     +ldi SHIFT_REG , ( 1 << 4 )
000832 8128     +andi SHIFT_REG_S , ~ ( 1 )
                +mw2 :
                 				WRITE_DATA
                 	_t4_s27_2:			
                +
                +$ ms0 :
000833 90d0 00c0+lds TEMP1 , UCSRA
000835 fed5     +sbrs TEMP1 , UDRE
000836 cd76     +rjmp _end_state
000837 9320 00c6+sts UDR , SHIFT_REG
000839 956a     +dec SHIFT_COUNT
00083a f771     +brne _t4_s27_1
                 				OUT_BIT_ SHIFT_REG , _t4_s27_1
                 
                +
00083b e9ac     +ldi XL , low ( _t4_s21 )
00083c e0b7     +ldi XH , high ( _t4_s21 )
00083d cd6f     +rjmp _end_state
                 				STATE_E _t4_s21 
                 _t4_s47:
                +
00083e 9870     +cbi PORTE , WG
                 				RES_WG
                 				
                +
                +$ msw0 :
00083f 90d0 00c0+lds TEMP1 , UCSRA
000841 fed5     +sbrs TEMP1 , UDRE
000842 cffc     +rjmp $ msw0
000843 9200 00c1+sts UCSRB , CONST00
                 				STOP_WRITE
                +
000845 9200 0091+sts TCCR3B , CONST00
                 				STOP_CAPTURE
                +
000847 6031     +ori S_REG , ( 1 << S_REG_BUSY )
                 				RES_S_REG_BIT  S_REG_BUSY 
                +
                +
000848 9869     +cbi DDRE , INTRQ
                 				SET_INTRQ
000849 7f5e      				andi FLAGS , ~( 1 << NEW_CMD )
                +
00084a e6a0     +ldi XL , low ( _t0 )
00084b e0b1     +ldi XH , high ( _t0 )
00084c cd60     +rjmp _end_state
                 			STATE_E _t0
                 	
                 
                 ;.if OLD_WRITE == 1
                 ;
                 ;
                 ;write_A1:
                 	;                           A1 	    1 0 1 0 0 0 0 1
                 	;	                        sinc   0 0 0 0 1 0 1 0
                 ;		ldi TEMP  , ( 1 )
                 ;       OUT_BIT TEMP
                 ;		ldi TEMP  , ( 0 )
                 ;        OUT_BIT TEMP
                 ;		ldi TEMP  , ( 1 ) 
                 ;		OUT_BIT TEMP
                 ;		ldi TEMP  , ( 0 )
                 ;		OUT_BIT TEMP
                 ;		ldi TEMP  , (1 << 4)
                 ;		OUT_BIT TEMP
                 ;		ldi TEMP  , ( 0 )
                 ;		OUT_BIT TEMP
                 ;		ldi TEMP  , (1 << 4)
                 ;		OUT_BIT TEMP
                 ;		ldi TEMP  , ( 1 )
                 ;		OUT_BIT TEMP
                 ;		ori SHIFT_REG_S ,  1 
                 ;ret
                 
                 ;write_C2:
                 	;						C2        1 1 0 0 0 0 1 0
                 	;	                    sinc     0 0 0 1 0 1 0 0
                 ;		ldi TEMP  , ( 1)
                 ;       OUT_BIT TEMP
                 ;		ldi TEMP  , ( 1 )
                 ;       OUT_BIT TEMP
                 ;		ldi TEMP  , ( 0 )
                 ;		OUT_BIT TEMP
                 ;		ldi TEMP  , (1 << 4)
                 ;		OUT_BIT TEMP
                 ;		ldi TEMP  , ( 0 )
                 ;		OUT_BIT TEMP
                 ;		ldi TEMP  , (1 << 4)
                 ;		OUT_BIT TEMP
                 ;		ldi TEMP  , ( 1 )
                 ;		OUT_BIT TEMP
                 ;		ldi TEMP  , (  0 )
                 ;		OUT_BIT TEMP
                 ;		andi SHIFT_REG_S , ~( 1)
                 ;ret
                 ;
                 ;.else
                 ;
                 ;write_A1:
                 	;                           A1 	    1 0 1 0 0 0 0 1
                 	;	                        sinc   0 0 0 0 1 0 1 0
                 ;		ldi TEMP  ,  0x10
                 ;       OUT_BIT TEMP
                 ;		ldi TEMP  ,  0x10
                 ;       OUT_BIT TEMP
                 ;		ldi TEMP  ,  0x40
                 ;		OUT_BIT TEMP
                 ;		ldi TEMP  ,  0x41
                 ;		OUT_BIT TEMP
                 ;		ldi SHIFT_REG_S , 1 
                 ;ret
                 
                 ;write_C2:
                 	;						C2        1 1 0 0 0 0 1 0     0 0 0 1 0 1 0 0 
                 	;	                    sinc     0 0 0 1 0 1 0 0       1 1 0 0 0 0 1 0  0101001000100100 
                 ;		ldi TEMP  ,  0x11 
                 ;		OUT_BIT TEMP
                 ;		ldi TEMP  ,  0x04
                 ;		OUT_BIT TEMP
                 ;		ldi TEMP  ,  0x04
                 ;		OUT_BIT TEMP
                 ;		ldi TEMP  ,  0x10
                 ;		OUT_BIT TEMP
                 ;       ldi SHIFT_REG_S , 0 
                 ;ret
                 ;.endif
                 ;
                 
                 .include "CRC.inc"
                 
                 ;
                 ;	low byte CRC lookup table
                 ;
                 
                +
                +    .org 256 + PC - PC % 256
                 align 256
                 ;.org 0x2000
                 crclo:
000900 2100
000901 6342
000902 a584
000903 e7c6
000904 2908
000905 6b4a
000906 ad8c
000907 efce       .db 0x00,0x21,0x42,0x63,0x84,0xA5,0xC6,0xE7,0x08,0x29,0x4A,0x6B,0x8C,0xAD,0xCE,0xEF
000908 1031
000909 5273
00090a 94b5
00090b d6f7
00090c 1839
00090d 5a7b
00090e 9cbd
00090f deff       .db 0x31,0x10,0x73,0x52,0xB5,0x94,0xF7,0xD6,0x39,0x18,0x7B,0x5A,0xBD,0x9C,0xFF,0xDE
000910 4362
000911 0120
000912 c7e6
000913 85a4
000914 4b6a
000915 0928
000916 cfee
000917 8dac       .db 0x62,0x43,0x20,0x01,0xE6,0xC7,0xA4,0x85,0x6A,0x4B,0x28,0x09,0xEE,0xCF,0xAC,0x8D
000918 7253
000919 3011
00091a f6d7
00091b b495
00091c 7a5b
00091d 3819
00091e fedf
00091f bc9d       .db 0x53,0x72,0x11,0x30,0xD7,0xF6,0x95,0xB4,0x5B,0x7A,0x19,0x38,0xDF,0xFE,0x9D,0xBC
000920 e5c4
000921 a786
000922 6140
000923 2302
000924 edcc
000925 af8e
000926 6948
000927 2b0a       .db 0xC4,0xE5,0x86,0xA7,0x40,0x61,0x02,0x23,0xCC,0xED,0x8E,0xAF,0x48,0x69,0x0A,0x2B
000928 d4f5
000929 96b7
00092a 5071
00092b 1233
00092c dcfd
00092d 9ebf
00092e 5879
00092f 1a3b       .db 0xF5,0xD4,0xB7,0x96,0x71,0x50,0x33,0x12,0xFD,0xDC,0xBF,0x9E,0x79,0x58,0x3B,0x1A
000930 87a6
000931 c5e4
000932 0322
000933 4160
000934 8fae
000935 cdec
000936 0b2a
000937 4968       .db 0xA6,0x87,0xE4,0xC5,0x22,0x03,0x60,0x41,0xAE,0x8F,0xEC,0xCD,0x2A,0x0B,0x68,0x49
000938 b697
000939 f4d5
00093a 3213
00093b 7051
00093c be9f
00093d fcdd
00093e 3a1b
00093f 7859       .db 0x97,0xB6,0xD5,0xF4,0x13,0x32,0x51,0x70,0x9F,0xBE,0xDD,0xFC,0x1B,0x3A,0x59,0x78
000940 a988
000941 ebca
000942 2d0c
000943 6f4e
000944 a180
000945 e3c2
000946 2504
000947 6746       .db 0x88,0xA9,0xCA,0xEB,0x0C,0x2D,0x4E,0x6F,0x80,0xA1,0xC2,0xE3,0x04,0x25,0x46,0x67
000948 98b9
000949 dafb
00094a 1c3d
00094b 5e7f
00094c 90b1
00094d d2f3
00094e 1435
00094f 5677       .db 0xB9,0x98,0xFB,0xDA,0x3D,0x1C,0x7F,0x5E,0xB1,0x90,0xF3,0xD2,0x35,0x14,0x77,0x56
000950 cbea
000951 89a8
000952 4f6e
000953 0d2c
000954 c3e2
000955 81a0
000956 4766
000957 0524       .db 0xEA,0xCB,0xA8,0x89,0x6E,0x4F,0x2C,0x0D,0xE2,0xC3,0xA0,0x81,0x66,0x47,0x24,0x05
000958 fadb
000959 b899
00095a 7e5f
00095b 3c1d
00095c f2d3
00095d b091
00095e 7657
00095f 3415       .db 0xDB,0xFA,0x99,0xB8,0x5F,0x7E,0x1D,0x3C,0xD3,0xF2,0x91,0xB0,0x57,0x76,0x15,0x34
000960 6d4c
000961 2f0e
000962 e9c8
000963 ab8a
000964 6544
000965 2706
000966 e1c0
000967 a382       .db 0x4C,0x6D,0x0E,0x2F,0xC8,0xE9,0x8A,0xAB,0x44,0x65,0x06,0x27,0xC0,0xE1,0x82,0xA3
000968 5c7d
000969 1e3f
00096a d8f9
00096b 9abb
00096c 5475
00096d 1637
00096e d0f1
00096f 92b3       .db 0x7D,0x5C,0x3F,0x1E,0xF9,0xD8,0xBB,0x9A,0x75,0x54,0x37,0x16,0xF1,0xD0,0xB3,0x92
000970 0f2e
000971 4d6c
000972 8baa
000973 c9e8
000974 0726
000975 4564
000976 83a2
000977 c1e0       .db 0x2E,0x0F,0x6C,0x4D,0xAA,0x8B,0xE8,0xC9,0x26,0x07,0x64,0x45,0xA2,0x83,0xE0,0xC1
000978 3e1f
000979 7c5d
00097a ba9b
00097b f8d9
00097c 3617
00097d 7455
00097e b293
00097f f0d1       .db 0x1F,0x3E,0x5D,0x7C,0x9B,0xBA,0xD9,0xF8,0x17,0x36,0x55,0x74,0x93,0xB2,0xD1,0xF0 
                 ;
                 ;	high byte CRC lookup table
                 ;
                 crchi:
000980 1000
000981 3020
000982 5040
000983 7060
000984 9181
000985 b1a1
000986 d1c1
000987 f1e1       .db 0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x81,0x91,0xA1,0xB1,0xC1,0xD1,0xE1,0xF1
000988 0212
000989 2232
00098a 4252
00098b 6272
00098c 8393
00098d a3b3
00098e c3d3
00098f e3f3       .db 0x12,0x02,0x32,0x22,0x52,0x42,0x72,0x62,0x93,0x83,0xB3,0xA3,0xD3,0xC3,0xF3,0xE3
000990 3424
000991 1404
000992 7464
000993 5444
000994 b5a5
000995 9585
000996 f5e5
000997 d5c5       .db 0x24,0x34,0x04,0x14,0x64,0x74,0x44,0x54,0xA5,0xB5,0x85,0x95,0xE5,0xF5,0xC5,0xD5
000998 2636
000999 0616
00099a 6676
00099b 4656
00099c a7b7
00099d 8797
00099e e7f7
00099f c7d7       .db 0x36,0x26,0x16,0x06,0x76,0x66,0x56,0x46,0xB7,0xA7,0x97,0x87,0xF7,0xE7,0xD7,0xC7
0009a0 5848
0009a1 7868
0009a2 1808
0009a3 3828
0009a4 d9c9
0009a5 f9e9
0009a6 9989
0009a7 b9a9       .db 0x48,0x58,0x68,0x78,0x08,0x18,0x28,0x38,0xC9,0xD9,0xE9,0xF9,0x89,0x99,0xA9,0xB9
0009a8 4a5a
0009a9 6a7a
0009aa 0a1a
0009ab 2a3a
0009ac cbdb
0009ad ebfb
0009ae 8b9b
0009af abbb       .db 0x5A,0x4A,0x7A,0x6A,0x1A,0x0A,0x3A,0x2A,0xDB,0xCB,0xFB,0xEB,0x9B,0x8B,0xBB,0xAB
0009b0 7c6c
0009b1 5c4c
0009b2 3c2c
0009b3 1c0c
0009b4 fded
0009b5 ddcd
0009b6 bdad
0009b7 9d8d       .db 0x6C,0x7C,0x4C,0x5C,0x2C,0x3C,0x0C,0x1C,0xED,0xFD,0xCD,0xDD,0xAD,0xBD,0x8D,0x9D
0009b8 6e7e
0009b9 4e5e
0009ba 2e3e
0009bb 0e1e
0009bc efff
0009bd cfdf
0009be afbf
0009bf 8f9f       .db 0x7E,0x6E,0x5E,0x4E,0x3E,0x2E,0x1E,0x0E,0xFF,0xEF,0xDF,0xCF,0xBF,0xAF,0x9F,0x8F
0009c0 8191
0009c1 a1b1
0009c2 c1d1
0009c3 e1f1
0009c4 0010
0009c5 2030
0009c6 4050
0009c7 6070       .db 0x91,0x81,0xB1,0xA1,0xD1,0xC1,0xF1,0xE1,0x10,0x00,0x30,0x20,0x50,0x40,0x70,0x60
0009c8 9383
0009c9 b3a3
0009ca d3c3
0009cb f3e3
0009cc 1202
0009cd 3222
0009ce 5242
0009cf 7262       .db 0x83,0x93,0xA3,0xB3,0xC3,0xD3,0xE3,0xF3,0x02,0x12,0x22,0x32,0x42,0x52,0x62,0x72
0009d0 a5b5
0009d1 8595
0009d2 e5f5
0009d3 c5d5
0009d4 2434
0009d5 0414
0009d6 6474
0009d7 4454       .db 0xB5,0xA5,0x95,0x85,0xF5,0xE5,0xD5,0xC5,0x34,0x24,0x14,0x04,0x74,0x64,0x54,0x44
0009d8 b7a7
0009d9 9787
0009da f7e7
0009db d7c7
0009dc 3626
0009dd 1606
0009de 7666
0009df 5646       .db 0xA7,0xB7,0x87,0x97,0xE7,0xF7,0xC7,0xD7,0x26,0x36,0x06,0x16,0x66,0x76,0x46,0x56
0009e0 c9d9
0009e1 e9f9
0009e2 8999
0009e3 a9b9
0009e4 4858
0009e5 6878
0009e6 0818
0009e7 2838       .db 0xD9,0xC9,0xF9,0xE9,0x99,0x89,0xB9,0xA9,0x58,0x48,0x78,0x68,0x18,0x08,0x38,0x28
0009e8 dbcb
0009e9 fbeb
0009ea 9b8b
0009eb bbab
0009ec 5a4a
0009ed 7a6a
0009ee 1a0a
0009ef 3a2a       .db 0xCB,0xDB,0xEB,0xFB,0x8B,0x9B,0xAB,0xBB,0x4A,0x5A,0x6A,0x7A,0x0A,0x1A,0x2A,0x3A
0009f0 edfd
0009f1 cddd
0009f2 adbd
0009f3 8d9d
0009f4 6c7c
0009f5 4c5c
0009f6 2c3c
0009f7 0c1c       .db 0xFD,0xED,0xDD,0xCD,0xBD,0xAD,0x9D,0x8D,0x7C,0x6C,0x5C,0x4C,0x3C,0x2C,0x1C,0x0C
0009f8 ffef
0009f9 dfcf
0009fa bfaf
0009fb 9f8f
0009fc 7e6e
0009fd 5e4e
0009fe 3e2e
0009ff 1e0e       .db 0xEF,0xFF,0xCF,0xDF,0xAF,0xBF,0x8F,0x9F,0x6E,0x7E,0x4E,0x5E,0x2E,0x3E,0x0E,0x1E 
                 
                 MFM_table:
                 ; .db 0x77 , 0x7D , 0xDF , 0xDD , 0xF7 , 0xFD , 0xDF , 0xDD   
000a00 4144
000a01 1110
000a02 0104
000a03 1110       .db  0x44 , 0x41 , 0x10 , 0x11 , 0x04 , 0x01 , 0x10 , 0x11
                 
                  A1_table:
                 .if OLD_WRITE == 1
                 .else
000a04 1010
000a05 4140      .db 0x10 , 0x10 , 0x40 , 0x41  
                 .endif
                 
                  C2_table:
                 .if OLD_WRITE == 1
                 .else
000a06 0411
000a07 1004      .db 0x11 , 0x04 , 0x04 , 0x10


RESOURCE USE INFORMATION
------------------------

Notice:
The register and instruction counts are symbol table hit counts,
and hence implicitly used resources are not counted, eg, the
'lpm' instruction without operands implicitly uses r0 and z,
none of which are counted.

x,y,z are separate entities in the symbol table and are
counted separately from r26..r31 here.

.dseg memory usage only counts static data declared with .byte

"LGT8F328P" register use summary:
r0 : 100 r1 :  36 r2 :   2 r3 :   0 r4 :   0 r5 :  14 r6 :   7 r7 :  24 
r8 :  26 r9 :  33 r10:   4 r11:   4 r12:   2 r13:  36 r14:   0 r15:  28 
r16: 265 r17:   4 r18:  39 r19:  42 r20:  76 r21:  83 r22:  41 r23:  53 
r24:   0 r25:   0 r26: 210 r27: 210 r28:  39 r29:  39 r30:   2 r31:   1 
x  :   0 y  :  29 z  :   0 
Registers used: 28 out of 35 (80.0%)

"LGT8F328P" instruction use summary:
.lds  :   0 .sts  :   0 adc   :  10 add   :  10 adiw  :   0 and   :   1 
andi  :  73 asr   :   0 bclr  :   0 bld   :   6 brbc  :   0 brbs  :   0 
brcc  :   0 brcs  :   0 break :   0 breq  :  17 brge  :   0 brhc  :   0 
brhs  :   0 brid  :   0 brie  :   0 brlo  :   1 brlt  :   0 brmi  :   0 
brne  :  45 brpl  :   2 brsh  :   2 brtc  :   0 brts  :   0 brvc  :   0 
brvs  :   0 bset  :   0 bst   :   4 call  :   0 cbi   :  54 cbr   :   0 
clc   :   0 clh   :   0 cli   :   1 cln   :   0 clr   :   4 cls   :   0 
clt   :   2 clv   :   0 clz   :   0 com   :  18 cp    :   6 cpc   :   0 
cpi   :  31 cpse  :   0 dec   :  30 eor   :  14 fmul  :   0 fmuls :   0 
fmulsu:   0 icall :   0 ijmp  :   1 in    :  15 inc   :   5 jmp   :   0 
ld    :  29 ldd   :   0 ldi   : 588 lds   :  22 lpm   :   0 lsl   :  25 
lsr   :   0 mov   :  59 movw  :   0 mul   :   0 muls  :   0 mulsu :   0 
neg   :   0 nop   :  37 or    :   4 ori   :  27 out   :  42 pop   :   0 
push  :   4 rcall :   0 ret   :   2 reti  :   1 rjmp  : 264 rol   :  21 
ror   :   0 sbc   :   0 sbci  :   0 sbi   :  38 sbic  :   9 sbis  :  32 
sbiw  :   0 sbr   :   0 sbrc  :   6 sbrs  :  78 sec   :   0 seh   :   0 
sei   :   1 sen   :   0 ser   :   8 ses   :   0 set   :   2 sev   :   0 
sez   :   0 sleep :   0 spm   :   0 st    :   0 std   :   0 sts   : 174 
sub   :   1 subi  :   0 swap  :   0 tst   :   0 wdr   :   0 
Instructions used: 47 out of 113 (41.6%)

"LGT8F328P" memory use summary [bytes]:
Segment   Begin    End      Code   Data   Used    Size   Use%
---------------------------------------------------------------
[.cseg] 0x000000 0x001410   4044    528   4572   32768  14.0%
[.dseg] 0x000100 0x000100      0      0      0    2048   0.0%
[.eseg] 0x000000 0x000000      0      0      0 9999999   0.0%

Assembly complete, 0 errors, 0 warnings
