/*
 * vg93_lgt_evo.asm
 *
 *  Created: 31.05.2023 9:13:34
 *   Author: ugryumov_ep
 */ 


 .include "lgt8f328pdef.inc"
 
 .equ OLD_WRITE = 0

 .include "macro.inc"
 .include "hardware.inc"
 
   
 .org 0x0000
	rjmp _reset
 .org INT0addr
;	movw TEMP_ZL , ZL
	in SREG_TEMP ,SREG
;	ldi ZH , 0x01
	in ZL , PEREHOD
	andi ZL , 0b00111100
;	nop						;
;	nop	`					;	
;	nop						;	
;	nop						;  работает в норм режиме 16 тактов 
;	nop						;
	ijmp
;.org WDTaddr
;	rjmp _reset
 .org INT_VECTORS_SIZE


 _reset:
		
	cli
	clr CONST00
	ldi TEMP ,( 1 << WDCE ) |  ( 1 << WDE )
	sts WDTCSR , TEMP
	ldi TEMP , ( 0 << WDE )
	sts WDTCSR , CONST00

	ser TEMP
	mov CONSTFF , TEMP
	
	ldi TEMP , 0x80
	sts PMCR , TEMP
	ldi TEMP , 1
	sts PMCR , TEMP
	
	
	ldi TEMP , 0x80 
	sts CLKPR , TEMP
	sts CLKPR , CONST00
	nop
	nop
	nop


	out DDRB , CONST00
	out PORTB , CONST00
	
	ldi TEMP , ( 1<<STEP) | ( 1 << DIR )
	out DDRC ,TEMP
	out PORTC , CONST00 
	
	ldi TEMP ,  ( 1 << 6 )

	out DDRD , TEMP
	;out PORTD , CONST00

	cbi DDRF , 4
	sbi PORTF , 4
	
  	sts DIDR0 , CONST00		
	;=========================================================
	// init stack pointer 0x45F
	ldi	TEMP,low(RAMEND)
	out	SPL,TEMP
	ldi	TEMP,high(RAMEND)
	out	SPH,TEMP
	
	ldi ZH , 0x01

	ldi TEMP , ( 1 << ISC01 )
	sts EICRA , TEMP
	ldi TEMP , ( 1 << INT0 )
	out EIMSK , TEMP 

	in TEMP , MCUSR
	ori TEMP , ( 1 << 7 )
	out MCUSR , TEMP
	out MCUSR , TEMP

	lds TEMP , PMX0
	ori TEMP , (1 << WCE )
	sts PMX0  , TEMP
	ori TEMP , ( 1 << TXD6 )
	sts PMX0 , TEMP 

	lds TEMP , PMX2
	ori TEMP , (1 << WCE )
	sts PMX2  , TEMP
	ori TEMP , ( 1 << E6EN )
	sts PMX2 , TEMP 




;	ldi TEMP , ( 1 << U2X )
;	sts UCSRA , TEMP
;	ldi TEMP , 7
;	sts UBRRH , CONST00
;	sts UBRRL , TEMP
;	ldi TEMP , ( 1 << UCSZ0 ) | ( 1 << UCSZ1 )
;	sts UCSRC , TEMP
;	ldi TEMP , ( 1 << TXEN )
;	sts UCSRB , TEMP


_warm_start:
		
	INI_DELAY
	INI_DELAY_32
	INI_INTRQ
	INI_DRQ
	INI_TR00
	INI_IP
	INI_HLD
	INI_WG
	INI_DIR
	INI_STEP
	INI_CLR
	INI_HRDY
	INI_CPRDY
	INI_TR43
	INI_WRPT
	INI_CAPTURE

	INI_WRITE
	
	ldi TEMP , ( 1 << INTF0 )
	out EIFR , TEMP
	sei

	rjmp _start


	_start:	
		
;		sts UDR , CONST00
		RES_WG
		clr FLAGS
		ldi TEMP , 0x03
		mov TEMP_CMD , TEMP
		ori FLAGS , ( 1  << NEW_CMD )
		mov TR_REG  , CONST00
		ldi TEMP , 0x01
		mov SECT_REG , TEMP
		clr DAT_REG 
		CLR_S_REG
		STOP_IP
		STATE_M _t0_0
_start_1:
		CHECK_CLR
			rjmp _start_1
        rjmp _end_state


.org 0x100
	
; rw = 00 a10=00
	nop
	nop
	nop
	rjmp end_INT0
; rw = 00 a10=01
	nop
	nop
	nop
	rjmp end_INT0
; rw = 00 a10=10
	nop
	nop
	nop
	rjmp end_INT0
; rw = 00 a10=11
	nop
	nop
	nop
	rjmp end_INT0

; rw = 01 a10 = 00
	out DIR_BUS , CONSTFF
	out DATA_BUS , S_REG
	RES_INTRQ
	rjmp end_INT0
; rw = 01 a10 = 01
	out DIR_BUS , CONSTFF
	out DATA_BUS , TR_REG
	nop
	rjmp end_INT0
; rw = 01 a10 = 10
	out DIR_BUS , CONSTFF
	out DATA_BUS , SECT_REG
	nop
	rjmp end_INT0
; rw = 01 a10 = 11
	out DIR_BUS , CONSTFF
	out DATA_BUS , DAT_REG
	RES_DRQ
	rjmp end_INT0

; rw = 10 a10 = 00
	in   TEMP_CMD ,  PIN_BUS
	ori FLAGS , ( 1 << NEW_CMD )
	nop	
	rjmp end_INT0
; rw = 10 a10 = 01
	in  TR_REG ,  PIN_BUS
	nop
	nop
	rjmp end_INT0
; rw = 10 a10 = 10
	in   SECT_REG , PIN_BUS 
	nop
	nop
	rjmp end_INT0
; rw = 10 a10 = 11
	in   DAT_REG ,  PIN_BUS
	nop
	RES_DRQ
 	rjmp end_INT0

; rw = 11 a10 = 00
	nop
	nop
	nop
	rjmp end_INT0
; rw = 11 a10 = 01
	nop
	nop
	nop
	rjmp end_INT0
; rw = 11 a10 = 10
	nop
	nop
	nop
	rjmp end_INT0
; rw = 11 a10 = 11
	nop
	nop
	nop
	rjmp end_INT0

end_INT0 :
		sbis PIND , 2
		rjmp end_INT0
		out DDRB , CONST00
		out PORTB , CONST00
;		movw ZL , TEMP_ZL
		out SREG , SREG_TEMP
		
		reti
 
 

.include "cmd_int.inc"	

;.if OLD_WRITE == 1
;
;
;write_A1:
	;                           A1 	    1 0 1 0 0 0 0 1
	;	                        sinc   0 0 0 0 1 0 1 0
;		ldi TEMP  , ( 1 )
;       OUT_BIT TEMP
;		ldi TEMP  , ( 0 )
;        OUT_BIT TEMP
;		ldi TEMP  , ( 1 ) 
;		OUT_BIT TEMP
;		ldi TEMP  , ( 0 )
;		OUT_BIT TEMP
;		ldi TEMP  , (1 << 4)
;		OUT_BIT TEMP
;		ldi TEMP  , ( 0 )
;		OUT_BIT TEMP
;		ldi TEMP  , (1 << 4)
;		OUT_BIT TEMP
;		ldi TEMP  , ( 1 )
;		OUT_BIT TEMP
;		ori SHIFT_REG_S ,  1 
;ret

;write_C2:
	;						C2        1 1 0 0 0 0 1 0
	;	                    sinc     0 0 0 1 0 1 0 0
;		ldi TEMP  , ( 1)
;       OUT_BIT TEMP
;		ldi TEMP  , ( 1 )
;       OUT_BIT TEMP
;		ldi TEMP  , ( 0 )
;		OUT_BIT TEMP
;		ldi TEMP  , (1 << 4)
;		OUT_BIT TEMP
;		ldi TEMP  , ( 0 )
;		OUT_BIT TEMP
;		ldi TEMP  , (1 << 4)
;		OUT_BIT TEMP
;		ldi TEMP  , ( 1 )
;		OUT_BIT TEMP
;		ldi TEMP  , (  0 )
;		OUT_BIT TEMP
;		andi SHIFT_REG_S , ~( 1)
;ret
;
;.else
;
;write_A1:
	;                           A1 	    1 0 1 0 0 0 0 1
	;	                        sinc   0 0 0 0 1 0 1 0
;		ldi TEMP  ,  0x10
;       OUT_BIT TEMP
;		ldi TEMP  ,  0x10
;       OUT_BIT TEMP
;		ldi TEMP  ,  0x40
;		OUT_BIT TEMP
;		ldi TEMP  ,  0x41
;		OUT_BIT TEMP
;		ldi SHIFT_REG_S , 1 
;ret

;write_C2:
	;						C2        1 1 0 0 0 0 1 0     0 0 0 1 0 1 0 0 
	;	                    sinc     0 0 0 1 0 1 0 0       1 1 0 0 0 0 1 0  0101001000100100 
;		ldi TEMP  ,  0x11 
;		OUT_BIT TEMP
;		ldi TEMP  ,  0x04
;		OUT_BIT TEMP
;		ldi TEMP  ,  0x04
;		OUT_BIT TEMP
;		ldi TEMP  ,  0x10
;		OUT_BIT TEMP
;       ldi SHIFT_REG_S , 0 
;ret
;.endif
;

.include "CRC.inc"
