_break_:	
			ori FLAGS , ( 1 << CMD_1_TYPE )
			START_DELAY_4
_break:
;			sts UDR , CMD_REG
			STOP_WRITER
			STOP_CAPTURE
			STOP_DELAY
			andi FLAGS , ~( (1 << NEW_CMD)  | (1 << READ_TR) | (1 << BREAK_IP ) )
			RES_S_REG_BIT  S_REG_BUSY
			ldi TEMP , 0b00001111
			and TEMP , TEMP_CMD
			breq _t0
			SET_INTRQ
			ori FLAGS , ( 1 << BREAK_D8 )
_t0:	
			ldi TEMP , (-15)  
			START_IP 
			STATE_E _t0_0
_t0_0:		
			sbis PORTD , HLD
				rjmp _t0_1
			CHECK_IP
				rjmp _t0_1
			RES_HLD
			SET_WF_DE
_t0_1:		
		STATE_M _t0_0
		
		CHECK_CLR
			rjmp _warm_start
		sbrs  FLAGS , NEW_CMD
			rjmp calc_ip

		mov TEMP , TEMP_CMD
	    andi TEMP , 0xF0
	    cpi TEMP , 0xD0
	    breq _break_
;		sts UDR , CMD_REG 
		andi FLAGS , ~( 1 << NEW_CMD )
; 		mov TEMP_CMD , CMD_REG
		sbrs TEMP_CMD , 7 
			rjmp _cmd_type_1
	   	andi FLAGS , ~(1 << CMD_1_TYPE)
	   	sbrs TEMP_CMD , 6
			rjmp _cmd_type_2
	
		sbrs TEMP_CMD , 4
			rjmp _cmd_type_3
	    
		sbrs TEMP_CMD , 3
			rjmp _cmd_type_4
		SET_INTRQ
		rjmp _t0_0

_cmd_type_1:
				ori FLAGS , (1 << CMD_1_TYPE)
				START_DELAY_4
				CLR_S_REG
	_t1_s02:
				SET_S_REG_BIT  S_REG_BUSY 
				RES_DRQ
				RES_INTRQ
				STATE_E _t1_s03
	_t1_s03:
				STATE_M _t1_s04
				sbrs TEMP_CMD , 3
				rjmp _end_state
				SET_HLD
;				SET_S_REG_BIT   S_REG_HLD
				STATE_E _t1_s05
	_t1_s04:					
				RES_HLD
;				RES_S_REG_BIT  S_REG_HLD
				STATE_E _t1_s05


	_t1_s05:
				STATE_M _t1_s07
				sbrs TEMP_CMD , 6
				rjmp _end_state
				
				STATE_M _t1_s06
				sbrs TEMP_CMD , 5
				rjmp _end_state			
				RES_DIR
				STATE_E _t1_C
	_t1_s06:	
				SET_DIR
				STATE_E _t1_C
	_t1_s07:	
				STATE_M _t1_s08
				sbrs TEMP_CMD , 5
				rjmp _end_state
	_t1_C:		
				STATE_M _t1_s17
				sbrs TEMP_CMD , 4
				rjmp _end_state 
				STATE_E _t1_s15
	_t1_s08:
				STATE_M _t1_s11
				sbrc TEMP_CMD , 4
		        rjmp _end_state
				STATE_E _t1_s09
	_t1_s09:
				mov TR_REG , CONSTFF
				STATE_E _t1_s10
	_t1_s10:
				mov DAT_REG , CONST00
				STATE_E _t1_s11
	_t1_s11:
				mov TEMP_D_REG , DAT_REG
				STATE_E _t1_s12
	_t1_s12:
				cp TEMP_D_REG , TR_REG
				brne _t1_s13
				STATE_E _t1_s21
	_t1_s13:
				cp TEMP_D_REG , TR_REG
				brlo _t1_s14
				SET_DIR
				STATE_E _t1_s15
	_t1_s14:
				RES_DIR
				STATE_E _t1_s15
	_t1_s15:
				STATE_M _t1_s16
				CHECK_DIR
					rjmp _end_state
				dec TR_REG
				STATE_E _t1_s17
	_t1_s16:
				inc TR_REG
				STATE_E _t1_s17
	_t1_s17:
				STATE_M _t1_s18
				CHECK_TR00
					rjmp _end_state
				CHECK_DIR
					rjmp _end_state
				mov TR_REG , CONST00
				STATE_E _t1_s21
	_t1_s18:
;	           	STATE_E _t1_s18_0		
	_t1_s18_0: 
				SET_STEP
				STATE_E _t1_s18_1
	_t1_s18_1:			
;				STATE_E _t1_s18_2
;	_t1_s18_2:			
;				STATE_E _t1_s18_3
;	_t1_s18_3:			
;				STATE_E _t1_s18_3_1
;	_t1_s18_3_1:			
;				STATE_E _t1_s18_3_2
;	_t1_s18_3_2:
;				STATE_E _t1_s18_4
;	_t1_s18_4:			
				RES_STEP			
		
				mov TEMP , TEMP_CMD
				andi TEMP , 0x3
				START_DELAY 
				STATE_E _t1_s19
	_t1_s19:
				STATE_M _t1_s19
				CHECK_DELAY
					rjmp _end_state
				STOP_DELAY
				STATE_E _t1_s20
	_t1_s20:
				STATE_M _t1_s21
				sbrc TEMP_CMD , 6
					rjmp _end_state
				sbrc TEMP_CMD , 5
					rjmp _end_state
				STATE_E _t1_s11

	_t1_s21:
				STATE_M _t1_s30
				sbrs TEMP_CMD , 2
					rjmp _end_state
				STATE_E _t1_s22
	_t1_s22:
				SET_HLD
;				SET_S_REG_BIT  S_REG_HLD
				ldi TEMP,0x01
				START_DELAY 
				STATE_E _t1_s23
	_t1_s23:
				STATE_M _t1_s23
				CHECK_DELAY
					rjmp _end_state
				STOP_DELAY
				STATE_E _t1_s24
	_t1_s24:
				STATE_M _t1_s24
				CHECK_HRDY
					rjmp _end_state
				ldi TEMP , (-9 )
				RES_WF_DE
				START_IP 
				START_CAPTURE
				STATE_E _t1_s25
	
	_t1_s25:
				
				STATE_M _t1_s26
				CHECK_IP 
					rjmp _end_state
				SET_S_REG_BIT  S_REG_SEEK_ERR
				STATE_E _t1_s30

	_t1_s26:    
	            STATE_M _t1_s25
				WAIT_SYNC_A1  _t1_s25
				INI_CRC
	_t1_s26_1:
				WAIT_SHIFT_R 	_t1_s26_1
				cpi TEMP_D_REG  , 0xFE
				breq _t1_s27
				STATE_E _t1_s25
	_t1_s27:
				WAIT_SHIFT_R 	_t1_s27
;				com TEMP_D_REG
				cp TR_REG , TEMP_D_REG
				breq	_t1_s28
				STATE_E _t1_s25
	_t1_s28:
				WAIT_SHIFT_R  _t1_s28
	_t1_s28_1:			
				WAIT_SHIFT_R  _t1_s28_1
	_t1_s28_2:			
				WAIT_SHIFT_R  _t1_s28_2
	_t1_s28_3:			
				WAIT_SHIFT_R _t1_s28_3
	_t1_s28_4:			
				WAIT_SHIFT_R _t1_s28_4
				or CRC_H , CRC_L
				breq _t1_s29
;				STATE_E _t1_s28_5
    _t1_s28_5:
	            SET_S_REG_BIT   S_REG_CRC_ERR 
				STATE_E _t1_s25
	_t1_s29:
				RES_S_REG_BIT  S_REG_CRC_ERR
				STATE_E _t1_s30
	_t1_s30:
				SET_WF_DE
				STOP_CAPTURE
				RES_S_REG_BIT  S_REG_BUSY 
				SET_INTRQ
				andi FLAGS , ~(( 1 << NEW_CMD ) | ( 1 << BREAK_D8))
				STATE_E _t0

_cmd_type_2:
	_t2_s01:
	_t2_s02:	CLR_S_REG 
				SET_S_REG_BIT  S_REG_BUSY 
				RES_DRQ
				RES_INTRQ
				STATE_E _t2_s03   
	_t2_s03:    
				STATE_M _t2_s04
				CHECK_CPRDY
					rjmp _end_state
				STATE_E _t2_s47
	_t2_s04:
				SET_HLD
	_t2_s05:
				STATE_M _t2_s07
				sbrs TEMP_CMD , 2
					rjmp _end_state
				ldi TEMP,0x02
				START_DELAY 
				STATE_E _t2_s06
	_t2_s06:	
				STATE_M _t2_s06
				CHECK_DELAY
					rjmp _end_state
				STOP_DELAY
				STATE_E _t2_s07
	_t2_s07:	
				STATE_M _t2_s07
				CHECK_HRDY
					rjmp _end_state
				STATE_E _t2_s08
	_t2_s08:				
				mov TEMP , TR_REG
				cpi TEMP , 43
				brpl _t2_s09
                RES_TR43
				STATE_E  _t2_s10
	_t2_s09:
				SET_TR43
				STATE_E _t2_s10	
	_t2_s10:
				STATE_M _t2_s11
				sbrc TEMP_CMD , 5
					rjmp _end_state
				STATE_E _t2_s12_0
	_t2_s11:	
				STATE_M _t2_s12_0
				CHECK_WRPT
					rjmp _end_state
				SET_S_REG_BIT   S_REG_WR_PR
				STATE_E _t2_s47				
	_t2_s12_0:
				RES_WF_DE
				ldi TEMP , (-5)
				START_IP  
				START_CAPTURE
				STATE_E _t2_s12
	_t2_s12:
                STATE_M _t2_s13
				CHECK_IP
					rjmp _end_state
				SET_S_REG_BIT  S_REG_SEEK_ERR 
				STATE_E _t2_s47
	_t2_s13:    
	            STATE_M _t2_s12
				WAIT_SYNC_A1  _t2_s12
				INI_CRC
	_t2_s13_1:
				WAIT_SHIFT_R 	_t2_s13_1
				cpi TEMP_D_REG  , 0xFE
				breq _t2_s14
				STATE_E _t2_s12
	_t2_s14:
				WAIT_SHIFT_R 	_t2_s14
				cp TR_REG , TEMP_D_REG
				breq _t2_s15
				STATE_E _t2_s12
	_t2_s15:	
				WAIT_SHIFT_R  _t2_s15
				STATE_M _t2_s16
				sbrs TEMP_CMD , 1
					rjmp _start_state
				andi TEMP_D_REG , 0b00000001
				STATE_M _t2_s15_1
				sbrs TEMP_CMD , 3
					rjmp _start_state
					STATE_M _t2_s16
				sbrc TEMP_D_REG  , 0
					rjmp _end_state
				STATE_E _t2_s12

	_t2_s15_1:				  
  				STATE_M _t2_s16
				sbrs TEMP_D_REG  , 0
					rjmp _end_state
				STATE_E _t2_s12  
	_t2_s16:
				WAIT_SHIFT_R  _t2_s16
				cp SECT_REG , TEMP_D_REG
				breq _t2_s17
				
				STATE_M _t2_s12
					rjmp _start_state
	_t2_s17:			
				WAIT_SHIFT_R  _t2_s17
               	STATE_M _t2_s18
				
				ldi TEMP , 0x80
				mov SECT_LEN , TEMP
				mov SECT_LEN_H , CONSTFF

	            cp TEMP_D_REG , CONST00
				breq _t2_s18
_t2_s17_1:
				lsl SECT_LEN
				rol SECT_LEN_H
				dec TEMP_D_REG
				brne _t2_s17_1				

_t2_s18:
				WAIT_SHIFT_R  _t2_s18
_t2_s18_1:				
				WAIT_SHIFT_R  _t2_s18_1
				or CRC_H , CRC_L
				breq _t2_s19
_t2_s18_2:
	            SET_S_REG_BIT  S_REG_CRC_ERR 
				STATE_E _t2_s12 
_t2_s19:		
				RES_S_REG_BIT  S_REG_CRC_ERR
			
_t2_s20:		STATE_M _t2_s31
				sbrc TEMP_CMD , 5
					rjmp _end_state
				STATE_E _t2_s21			
_t2_s21:        
				STATE_M _t2_s21
				WAIT_SYNC_A1  _t2_s21
				INI_CRC
_t2_s21_2:				
				WAIT_SHIFT_R 	_t2_s21_2
				cpi TEMP_D_REG  , 0xF8
				breq _t2_s22
				cpi TEMP_D_REG  , 0xFB
				breq _t2_s23
				STATE_M _t2_s21
				rjmp _start_state
	_t2_s22:        
				SET_S_REG_BIT   S_REG_TYPE_REC  
   	_t2_s23:
	_t2_s25:
                WAIT_SHIFT_R _t2_s25
				mov DAT_REG , TEMP_D_REG
	_t2_s26:
                STATE_M _t2_s27
				CHECK_DRQ
					rjmp _start_state
				SET_S_REG_BIT  S_REG_DATA_LOST 
	_t2_s27:
				SET_DRQ
				INC_SECT_LEN
				breq _t2_s28
				STATE_M _t2_s25
				rjmp _start_state
	_t2_s28:
				WAIT_SHIFT_R _t2_s28
	_t2_s28_1:
				WAIT_SHIFT_R _t2_s28_1			
				or CRC_H , CRC_L
				breq _t2_s28_3
	_t2_s28_2:
				SET_S_REG_BIT  S_REG_CRC_ERR 
				STATE_E _t2_s47 
	_t2_s28_3:	
				RES_S_REG_BIT  S_REG_CRC_ERR 
				STATE_E _t2_s29 
	_t2_s29:
				STATE_M _t2_s47
				sbrs TEMP_CMD , 4
					rjmp _end_state
				STATE_E _t2_s30
	_t2_s30:	
				inc SECT_REG
				STATE_E _t2_s10
	_t2_s31:	
				ldi TEMP , 8
				START_DELAY_32
	_t2_s32:	
				STATE_M _t2_s32
				CHECK_DELAY_32
					rjmp _end_state
				STOP_DELAY_32
				SET_DRQ			
				
				ldi TEMP , 32
				START_DELAY_32
				STATE_M _t2_s33
	_t2_s33:
				CHECK_DELAY_32
					rjmp _end_state
				STOP_DELAY_32
				STATE_E _t2_s34
	_t2_s34:
				STATE_M _t2_s35
				CHECK_DRQ
					rjmp _end_state
				SET_S_REG_BIT S_REG_DATA_LOST
				STATE_E _t2_s47
	_t2_s35:		
				ldi TEMP , 4
				START_DELAY_32
				STATE_M _t2_s35_0
	_t2_s35_0:	
				CHECK_DELAY_32
					rjmp _end_state
				STOP_DELAY_32
				STATE_E _t2_s36
	_t2_s36:	
				ldi TEMP , 44
				START_DELAY_32
				STATE_M _t2_s37
	_t2_s37:
				CHECK_DELAY_32
					rjmp _end_state
				STOP_DELAY_32
				STATE_E _t2_s38
   	_t2_s38:
				START_WRITE
				SET_WG
				SET_WF_DE			
				ldi SHIFT_REG_S , 0 
				.if OLD_WRITE == 1
					ldi SHIFT_REG , (1 << 4 )
				.else
					ldi SHIFT_REG , 0x44
				.endif
				ldi SHIFT_COUNT , 12 * BIT_COUNT
				STATE_M _t2_s38_1
	_t2_s38_1:			
				OUT_BIT_ SHIFT_REG , _t2_s38_1
				
	_t2_s39:
				ldi SHIFT_COUNT , BIT_COUNT
				ldi YH , high( A1_table * 2 ) + 0x40
				ldi YL , low( A1_table  * 2 )
				
				STATE_M _t2_s39_0_2
	_t2_s39_0_1:
				ld  SHIFT_REG , Y+
	_t2_s39_0_2:							
				OUT_BIT_ SHIFT_REG , _t2_s39_0_1
				ldi SHIFT_REG_S , 1
				INI_CRC
				
				ldi SHIFT_COUNT , BIT_COUNT
				ldi YH , high( A1_table * 2 ) + 0x40
				ldi YL , low( A1_table  * 2 )
				STATE_M _t2_s39_2
	_t2_s39_1:
				ld  SHIFT_REG , Y+
	_t2_s39_2:							
				OUT_BIT_ SHIFT_REG , _t2_s39_1				
					
				ldi TEMP_D_REG , 0xFB
				CHECK_S_REG_BIT S_REG_TYPE_REC
				ldi TEMP_D_REG , 0xF8
			
				ldi SHIFT_COUNT , BIT_COUNT
				ldi YH , high( A1_table * 2 ) + 0x40
				ldi YL , low( A1_table  * 2 )
				ldi SHIFT_REG_S , 1
				STATE_M _t2_s39_1_2
	_t2_s39_1_1:
				ld  SHIFT_REG , Y+
	_t2_s39_1_2:							
				OUT_BIT_ SHIFT_REG , _t2_s39_1_1				
					
				CALC_CRC TEMP_D_REG
	;			INC_SECT_LEN
				
				ldi SHIFT_COUNT , BIT_COUNT
				STATE_M _t2_s39_2_2
	_t2_s39_2_1:
				WRITE_DATA
	_t2_s39_2_2:			
				OUT_BIT_ SHIFT_REG , _t2_s39_2_1 
				
	_t2_s40:		
				mov TEMP_D_REG , DAT_REG
				CALC_CRC TEMP_D_REG
				SET_DRQ
				
				ldi SHIFT_COUNT , BIT_COUNT
				STATE_M _t2_s40_2
	_t2_s40_1:
				WRITE_DATA
	_t2_s40_2:			
				OUT_BIT_ SHIFT_REG , _t2_s40_1
	_t2_s41:			
				STATE_M _t2_s42
				CHECK_DRQ
					rjmp _end_state
				SET_S_REG_BIT  S_REG_DATA_LOST 
				mov DAT_REG , CONST00
				rjmp _end_state
	_t2_s42:			
				STATE_M _t2_s40
				INC_SECT_LEN
				breq _t2_s43
				rjmp _end_state
	_t2_s43:
;	           	mov TEMP_D_REG , DAT_REG
;				com TEMP_D_REG
;				CALC_CRC TEMP_D_REG
;				
;				ldi SHIFT_COUNT , BIT_COUNT
;				STATE_M _t2_s43_2
;	_t2_s43_1:
;				WRITE_DATA
;	_t2_s43_2:			
;				OUT_BIT_ SHIFT_REG , _t2_s43_1
;		
	_t2_s44:		
				mov TEMP_D_REG , CRC_H
				
				ldi SHIFT_COUNT , BIT_COUNT
				STATE_M _t2_s44_0_2
	_t2_s44_0_1:
				WRITE_DATA
	_t2_s44_0_2:			
				OUT_BIT_ SHIFT_REG , _t2_s44_0_1
					
				mov TEMP_D_REG , CRC_L
				ldi SHIFT_COUNT , BIT_COUNT				
				STATE_M _t2_s44_2
	_t2_s44_1:
				WRITE_DATA
	_t2_s44_2:			
				OUT_BIT_ SHIFT_REG , _t2_s44_1
					
	_t2_s45:		
				ser  TEMP_D_REG 
							
				ldi SHIFT_COUNT , BIT_COUNT
				STATE_M _t2_s45_0_2
	_t2_s45_0_1:
				WRITE_DATA
	_t2_s45_0_2:			
				OUT_BIT_ SHIFT_REG , _t2_s45_0_1
							
				ser  TEMP_D_REG 
							
				ldi SHIFT_COUNT , BIT_COUNT
				STATE_M _t2_s45_2
	_t2_s45_1:
				WRITE_DATA
	_t2_s45_2:			
				OUT_BIT_ SHIFT_REG , _t2_s45_1
				
	_t2_s46:	
				RES_WG
				STOP_WRITE
				STATE_E _t2_s29
	_t2_s47:
				STOP_CAPTURE
				RES_S_REG_BIT  S_REG_BUSY 
				SET_INTRQ
				andi FLAGS , ~(( 1 << NEW_CMD ) | ( 1 << BREAK_D8))
			STATE_E _t0

_start_state:
			 READ_BYTE
_end_state:	  	        
			CHECK_CLR
				rjmp _warm_start
   			sbrs FLAGS , NEW_CMD
				rjmp calc_ip
;			andi FLAGS , ~( 1 << NEW_CMD )
			mov TEMP , TEMP_CMD
			andi TEMP , 0b11110000
			cpi TEMP , 0xD0
			brne  calc_ip
			
			sbrc TEMP_CMD , 3
			rjmp _break
			
			sbrs TEMP_CMD , 2
			rjmp break_no_ip
			ori FLAGS ,  1 << BREAK_IP			
			STOP_IP
			ldi TEMP , (-1 )
			START_IP
			rjmp calc_ip
break_no_ip:
			rjmp _break
		
calc_ip:	   
			sbrs FLAGS , BREAK_IP
			rjmp calc_sreg
			CHECK_IP						
			rjmp calc_sreg
			rjmp _break

calc_sreg:	   
			sbrc FLAGS , BREAK_D8
				SET_INTRQ
			in TEMP , PIND
			com TEMP
;			clt
;			CHECK_CPRDY
;				set
			bst TEMP , CPRDY
			bld S_REG , S_REG_READY
			
			sbrs FLAGS , CMD_1_TYPE
			   rjmp no_1_type
			
			bst TEMP , HLD
			bld S_REG , S_REG_HLD
			CHECK_HRDY
				SET_S_REG_BIT  S_REG_HLD

;			clt
;			CHECK_IP_
;				set  
			bst TEMP , IP
			bld S_REG , S_REG_IP
			
;			clt
;			CHECK_TR00
;				set
			bst TEMP , TR00
			bld S_REG , S_REG_TR00
			
			set
			CHECK_WRPT
			  clt
			bld S_REG , S_REG_WR_PR

;			rjmp end_calc_sreg
wait_clock:
            CHECK_DELAY_4
				rjmp wait_clock
			out TIFR2 , CONSTFF
			push XL
			push XH
			ret

no_1_type:
			set
			CHECK_DRQ
				clt
;			bst TEMP , DRQ
			bld S_REG  , S_REG_DRQ
	
end_calc_sreg:
;			sbrc FLAGS , SKIP_TIMER
;				rjmp skip_time
;check_time:
;			lds TEMP , TCNT2
;			cp TEMP , TIME
;			breq check_time
;			mov TIME , TEMP
;skip_time:
;		  ijmp
			push XL
			push XH
			ret


_cmd_type_3:
	_t3_s01:
		    	CLR_S_REG
				SET_S_REG_BIT  S_REG_BUSY 
				RES_DRQ
				RES_INTRQ
				STATE_E _t3_s02   
	_t3_s02:
				STATE_M _t3_s03
				CHECK_CPRDY
					rjmp _end_state
                STATE_E _t3_s25
	_t3_s03:
				SET_HLD
				STATE_E _t3_s04
	_t3_s04:
				STATE_M _t3_s06
				sbrs TEMP_CMD , 2
					rjmp _end_state
				ldi TEMP , 0x02
				START_DELAY 
				STATE_E _t3_s05
	_t3_s05:	
				STATE_M _t3_s05
				CHECK_DELAY
					rjmp _end_state
				STOP_DELAY
				STATE_E _t3_s06
	_t3_s06:	
				STATE_M _t3_s06
				CHECK_HRDY
					rjmp _end_state
				STATE_E _t3_s07
	_t3_s07:				
	            RES_WF_DE
				SET_TR43
				START_CAPTURE
				STATE_E  _t3_s08
	_t3_s08:
				STATE_M _t3_s17_0
				sbrs TEMP_CMD , 5
					rjmp _end_state
				ori  FLAGS , ( 1 << READ_TR )
				ldi TEMP , ( -1 )
				START_IP
				STATE_E _t3_s09
	_t3_s09:
;				STATE_M _t3_s10
;				CHECK_IP
;					rjmp _end_state
;				STATE_E _t3_s09	
	_t3_s10:
				STATE_M _t3_s10
				CHECK_IP
					rjmp _end_state
				ldi SHIFT_COUNT , 16
;				ori FLAGS  , ( 1 << IP_R )
				STOP_IP
				ldi TEMP , ( -1 )
				START_IP 
				STATE_E _t3_s11
	_t3_s11:		
				STATE_M _t3_s12
				CHECK_IP
					rjmp _start_state
				andi FLAGS , ~( 1 << READ_TR ) 
				STATE_E _t3_s25

	_t3_s12:        
				STATE_M _t3_s11
;				READ_BYTE 
				sbrs FLAGS , S_D_R
					rjmp _start_state	
				andi  FLAGS , ~( 1 << S_D_R )
	_t3_s13:		
				STATE_M _t3_s14
				CHECK_DRQ
					rjmp _start_state
				SET_S_REG_BIT  S_REG_DATA_LOST 
	_t3_s14:
	_t3_s15:
				mov DAT_REG , TEMP_D_REG
;				com DAT_REG
				SET_DRQ
	_t3_s16:
				STATE_M _t3_s11
				rjmp _start_state
	_t3_s17_0:	
				ldi TEMP , ( -5 )
				START_IP  
				START_CAPTURE
				STATE_E _t3_s17
	_t3_s17:
                STATE_M _t3_s18
				CHECK_IP 
					rjmp _end_state
				STATE_E _t3_s25
	_t3_s18:    
	            STATE_M _t3_s17
				WAIT_SYNC_A1  _t3_s17
				INI_CRC
	_t3_s19:
				WAIT_SHIFT_R 	_t3_s19
				cpi TEMP_D_REG  , 0xFE
				breq _t3_s19_1
				STATE_E _t3_s17
	_t3_s19_1:
				WAIT_SHIFT_R 	_t3_s19_1
;				com TEMP_D_REG
				mov SECT_REG , TEMP_D_REG
				mov	DAT_REG , TEMP_D_REG
				SET_DRQ
				STATE_E _t3_s19_2	
	_t3_s19_2:
				WAIT_SHIFT_R 	_t3_s19_2
				mov	DAT_REG , TEMP_D_REG
	;			com DAT_REG
				SET_DRQ
				STATE_E _t3_s19_3	
	_t3_s19_3:
				WAIT_SHIFT_R 	_t3_s19_3
				mov	DAT_REG , TEMP_D_REG
	;			com DAT_REG
				SET_DRQ
				STATE_E _t3_s19_4	
	_t3_s19_4:				
				WAIT_SHIFT_R 	_t3_s19_4
				mov	DAT_REG , TEMP_D_REG
	;			com DAT_REG
				SET_DRQ
				STATE_E _t3_s20	
	_t3_s20:
	_t3_s21:
	_t3_s22:
	_t3_s23:
	_t3_s24:							
				WAIT_SHIFT_R  _t3_s24
				mov	DAT_REG , TEMP_D_REG
	;			com DAT_REG
				SET_DRQ
	_t3_s24_1:				
				WAIT_SHIFT_R  _t3_s24_1
				mov	DAT_REG , TEMP_D_REG
	;			com DAT_REG
				SET_DRQ
	            or CRC_H , CRC_L
				breq _t3_s24_3
	_t3_s24_2:
	            SET_S_REG_BIT  S_REG_CRC_ERR 
				STATE_E _t3_s24_4 

	_t3_s24_3:		
				RES_S_REG_BIT  S_REG_CRC_ERR 
				STATE_E _t3_s24_4
    _t3_s24_4:
       			ldi TEMP , 4
				START_DELAY_32
				STATE_E _t3_s24_5
    _t3_s24_5:
	            CHECK_DELAY_32
					rjmp _end_state
				STOP_DELAY_32 	    
				STATE_E _t3_s25
	_t3_s25:
				SET_WF_DE
				STOP_CAPTURE
				RES_S_REG_BIT  S_REG_BUSY 
	      		andi FLAGS , ~(( 1 << NEW_CMD ) | ( 1 << BREAK_D8))
				SET_INTRQ
			STATE_E _t0


_cmd_type_4:
_t4_s01:
_t4_s02:	    CLR_S_REG
				SET_S_REG_BIT  S_REG_BUSY
				RES_DRQ
				RES_INTRQ
				STATE_E _t4_s03  
_t4_s03:    
				STATE_M _t4_s04
				CHECK_CPRDY
					rjmp _end_state
                STATE_E _t4_s47
_t4_s04:
				SET_HLD
_t4_s05:
				STATE_M _t4_s07
				sbrs TEMP_CMD , 2
					rjmp _end_state
				
				ldi TEMP,0x02
				START_DELAY 
				STATE_E _t4_s06
_t4_s06:	
				STATE_M _t4_s06
				CHECK_DELAY
					rjmp _end_state
				STOP_DELAY
				STATE_E _t4_s07
_t4_s07:	
				STATE_M _t4_s07
				CHECK_HRDY
					rjmp _end_state
				STATE_E _t4_s08
_t4_s08:				
				SET_WF_DE
				mov TEMP , TR_REG
	;			com TEMP
				cpi TEMP , 43
				brpl _t4_s09_0
                RES_TR43
				STATE_E  _t4_s09
_t4_s09_0:
				SET_TR43
				STATE_E _t4_s09
_t4_s09:       
 				STATE_M _t4_s10
				CHECK_WRPT
					rjmp _end_state
				SET_S_REG_BIT  S_REG_WR_PR 
				STATE_E _t4_s47
_t4_s10:
				SET_DRQ
				ldi TEMP , 12
				START_DELAY_32
				STATE_E _t4_s11
_t4_s11:
				CHECK_DELAY_32
					rjmp _end_state
				STOP_DELAY_32
				STATE_E _t4_s12

_t4_s12:		STATE_M _t4_s13
				CHECK_DRQ
					rjmp _end_state
				SET_S_REG_BIT  S_REG_DATA_LOST 
				STATE_E _t4_s47
_t4_s13:		
;				STATE_M _t4_s13_0
;				CHECK_IP
;					rjmp _end_state
;				STATE_E _t4_s13	
				ldi TEMP , ( -1 )
				START_IP
_t4_s13_0:
				STATE_M _t4_s13_0
				CHECK_IP
					rjmp _end_state
;				ori FLAGS , (1 << IP_R )
				ldi TEMP , (-1 )
				START_IP 
				SET_WG
				SET_WF_DE
				START_WRITE
				STATE_E _t4_s14
		
_t4_s14:		mov TEMP_D_REG , DAT_REG 
	;			com TEMP_D_REG
_t4_s15:
				SET_DRQ
_t4_s16:
				STATE_E _t4_s24
_t4_s17:
_t4_s18:
_t4_s19:
_t4_s20:
_t4_s21:	
				STATE_M _t4_s22
				CHECK_IP
					rjmp _end_state
				STATE_E _t4_s47
_t4_s22:		
				STATE_M _t4_s14
				CHECK_DRQ
					rjmp _end_state
				SET_S_REG_BIT  S_REG_DATA_LOST 
				clr TEMP_D_REG
						
				ldi SHIFT_COUNT , BIT_COUNT
				STATE_M _t4_s22_2
	_t4_s22_1:
				WRITE_DATA
	_t4_s22_2:			
				OUT_BIT_ SHIFT_REG , _t4_s22_1
				STATE_E _t4_s21
_t4_s23:
_t4_s24:		cpi TEMP_D_REG , 0xF5
				brne _t4_s25
				
				ldi SHIFT_COUNT , BIT_COUNT
				ldi YH , high( A1_table * 2 ) + 0x40
				ldi YL , low( A1_table  * 2 )
				ldi SHIFT_REG_S , 1
				STATE_M _t4_s24_2
	_t4_s24_1:
				ld  SHIFT_REG , Y+
	_t4_s24_2:							
				OUT_BIT_ SHIFT_REG , _t4_s24_1

				INI_CRC
				STATE_E _t4_s21
_t4_s25:
				cpi TEMP_D_REG , 0xF6
				brne _t4_s26
				
				ldi SHIFT_COUNT , BIT_COUNT
				ldi YH , high( C2_table * 2 ) + 0x40
				ldi YL , low( C2_table  * 2 )
				ldi SHIFT_REG_S , 0
				STATE_M _t4_s25_2
	_t4_s25_1:
				ld  SHIFT_REG , Y+
	_t4_s25_2:							
				OUT_BIT_ SHIFT_REG , _t4_s25_1
				STATE_E _t4_s21
_t4_s26:
				cpi TEMP_D_REG , 0xF7
				brne _t4_s27
				mov TEMP_D_REG , CRC_H
				
				ldi SHIFT_COUNT , BIT_COUNT
				STATE_M _t4_s26_0_2
	_t4_s26_0_1:
				WRITE_DATA
	_t4_s26_0_2:			
				OUT_BIT_ SHIFT_REG , _t4_s26_0_1
	
				mov TEMP_D_REG , CRC_L
							
				ldi SHIFT_COUNT , BIT_COUNT
				STATE_M _t4_s26_2
	_t4_s26_1:
				WRITE_DATA
	_t4_s26_2:			
				OUT_BIT_ SHIFT_REG , _t4_s26_1
				STATE_E _t4_s21 
	_t4_s27:
				CALC_CRC TEMP_D_REG
				ldi SHIFT_COUNT , BIT_COUNT
				STATE_M _t4_s27_2
	_t4_s27_1:
				WRITE_DATA
	_t4_s27_2:			
				OUT_BIT_ SHIFT_REG , _t4_s27_1

				STATE_E _t4_s21 
_t4_s47:
				RES_WG
				
				STOP_WRITE
				STOP_CAPTURE
				RES_S_REG_BIT  S_REG_BUSY 
				SET_INTRQ
				andi FLAGS , ~(( 1 << NEW_CMD ) | ( 1 << BREAK_D8 )) 
			STATE_E _t0
	
;	rjmp _end_state