# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 14:32:59  February 06, 2026
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		d_fix_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7064SLC44-10"
set_global_assignment -name TOP_LEVEL_ENTITY zx_cartridge
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:32:59  FEBRUARY 06, 2026"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 44
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 10
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
set_global_assignment -name VERILOG_FILE src/zx_cartridge.v
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_location_assignment PIN_1 -to reset_n
set_location_assignment PIN_2 -to rd_n
set_location_assignment PIN_4 -to wr_n
set_location_assignment PIN_6 -to A14
set_location_assignment PIN_8 -to A15
set_location_assignment PIN_9 -to A13
set_location_assignment PIN_11 -to CR_ROM_CS[0]
set_location_assignment PIN_12 -to CR_ROM_CS[1]
set_location_assignment PIN_16 -to CR_ROM_A[5]
set_location_assignment PIN_18 -to CR_ROM_A[4]
set_location_assignment PIN_19 -to CR_ROM_A[3]
set_location_assignment PIN_20 -to CR_ROM_A[1]
set_location_assignment PIN_21 -to CR_ROM_A[2]
set_location_assignment PIN_24 -to A7
set_location_assignment PIN_25 -to CR_ROM_A[0]
set_location_assignment PIN_26 -to CR_ROM_oe_n
set_location_assignment PIN_14 -to CR_ROM_CS[2]
set_location_assignment PIN_28 -to D[0]
set_location_assignment PIN_29 -to D[1]
set_location_assignment PIN_31 -to D[7]
set_location_assignment PIN_33 -to ZX_ROM_blk
set_location_assignment PIN_34 -to D[2]
set_location_assignment PIN_37 -to D[6]
set_location_assignment PIN_39 -to D[4]
set_location_assignment PIN_40 -to D[3]
set_location_assignment PIN_41 -to D[5]
set_location_assignment PIN_43 -to mreq_n
set_location_assignment PIN_44 -to iorq_n

set_location_assignment PIN_27 -to CR_ROM_CS[3]