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https://github.com/MikhaelKaa/zx_cartridge.git
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56 lines
1.6 KiB
Verilog
56 lines
1.6 KiB
Verilog
`timescale 1ns / 1ps
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// ZX SPECTRUM cartrige module
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// 17.02.2026 Mikhael Kaa
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// CPU adr bus A0...A12 connect directly to CR_ROM chip
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module zx_cartrige #(
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// default example parameter
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parameter SELF_LOCK_VAL = 15
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)(
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// Reset
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input reset_n,
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// CPU ctrl signals
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input iorq_n,
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input rd_n,
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input mreq_n,
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// Part of CPU adr bus
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input A7,
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input A13,
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input A14,
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input A15,
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// ZX ROM block
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output ZX_ROM_blk,
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// Cartrige ROM enable
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output CR_ROM_oe_n,
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// Up part cartrige ROM adr bus (A13...A18)
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output [5:0] CR_ROM_A
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);
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// CR_ROM 8kb bank counter
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reg [5:0] CR_ROM_bank_cnt = 6'b0;
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// Self lock register, disable all logic and CR_ROM
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reg self_lock = 1'b0;
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// rd or wr port 0x7f increment CR_ROM bank
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wire rom_page_up = iorq_n | A7 | self_lock;
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// CPU work with 0000...1fff adr
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wire lower_rom = ({A13, A14, A15} == 3'b000) ? 1'b1 : 1'b0;
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always @(negedge rom_page_up or negedge reset_n) begin
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if(!reset_n) begin
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CR_ROM_bank_cnt <= 6'b0;
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self_lock <= 1'b0;
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end else begin
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// increment bank counter
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CR_ROM_bank_cnt <= CR_ROM_bank_cnt + 1'b1;
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// check self lock
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if(CR_ROM_bank_cnt == SELF_LOCK_VAL) begin
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self_lock <= 1'b1;
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end
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end
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end
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assign CR_ROM_oe_n = ~lower_rom | rd_n | mreq_n | self_lock ;
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assign ZX_ROM_blk = ~CR_ROM_oe_n;
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assign CR_ROM_A = CR_ROM_bank_cnt;
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endmodule
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