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Contributing 68000, VAX, Z80, SH4, PDP-11, NS32000 docs plus various README.md files

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The Blue Wizard 2016-04-20 20:29:44 -04:00 committed by Lars Brinkhoff
parent c1878866cc
commit b7508b9900
23 changed files with 17272 additions and 0 deletions
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680x0bin.txt
Instruction set of the 680x0 in binary order
1988/WJvG
0 1 2 3
0000 000000 aaaaaa 00000000 dddddddd ori.b #datab,a
0000 000000 111100 00000000 dddddddd ori.b #datab,ccr
0000 000001 aaaaaa dddddddd dddddddd ori.w #dataw,a
0000 000001 111100 dddddddd dddddddd ori.w #dataw,sr (sup)
0000 000010 aaaaaa longword ori.l #datal,a
0000 000011 aaaaaa nnnn0000 00000000 cmp2.b a,Rn (020)
0000 000011 aaaaaa nnnn1000 00000000 chk2.b a,Rn (020)
0000 001000 aaaaaa 00000000 dddddddd andi.b #datab,a
0000 001000 111100 00000000 dddddddd andi.b #datab,ccr
0000 001001 aaaaaa dddddddd dddddddd andi.w #dataw,a
0000 001001 111100 dddddddd dddddddd andi.w #dataw,sr (sup)
0000 001010 aaaaaa longword andi.l #datal,a
0000 001011 aaaaaa nnnn0000 00000000 cmp2.w a,Rn (020)
0000 001011 aaaaaa nnnn1000 00000000 chk2.w a,Rn (020)
0000 010000 aaaaaa 00000000 dddddddd subi.b #datab,a
0000 010001 aaaaaa dddddddd dddddddd subi.w #dataw,a
0000 010010 aaaaaa longword subi.l #datal,a
0000 010011 aaaaaa nnnn0000 00000000 cmp2.l a,Rn (020)
0000 010011 aaaaaa nnnn1000 00000000 chk2.l a,Rn (020)
0000 011000 aaaaaa 00000000 dddddddd addi.b #datab,a
0000 011001 aaaaaa dddddddd dddddddd addi.w #dataw,a
0000 011010 aaaaaa longword addi.l #datal,a
0000 011011 00nnnn rtm Rn (020)
0000 011011 aaaaaa 00000000 dddddddd callm #data8,a (020)
0000 100000 aaaaaa 00000000 000bbbbb btst #bitnr,a
0000 100001 aaaaaa 00000000 000bbbbb bchg #bitnr,a
0000 100010 aaaaaa 00000000 000bbbbb bclr #bitnr,a
0000 100011 aaaaaa 00000000 000bbbbb bset #bitnr,a
0000 101000 aaaaaa 00000000 dddddddd eori.b #datab,a
0000 101000 111100 00000000 dddddddd eori.b #datab,ccr
0000 101001 aaaaaa dddddddd dddddddd eori.w #dataw,a
0000 101001 111100 dddddddd dddddddd eori.w #dataw,sr (sup)
0000 101010 aaaaaa longword eori.l #datal,a
0000 101011 aaaaaa 0000000u uu000ccc cas.b Dc,Du,ea (020)
0000 101011 111100 nnnn000u uu000ccc cas2.b Dc1:Dc2,Du1:Du2,
nnnn000u uu000ccc (Rn):(Rn) (020)
0000 1100zz aaaaaa cmpi.z #dataz,a
0000 110011 aaaaaa 0000000u uu000ccc cas.w Dc,Du,ea (020)
0000 110011 111100 nnnn000u uu000ccc cas2.w Dc1:Dc2,Du1:Du2,
nnnn000u uu000ccc (Rn):(Rn) (020)
0000 1110zz aaaaaa nnnn0000 00000000 moves.z a,Rn (010,sup)
0000 1110zz aaaaaa nnnn1000 00000000 moves.z Rn,a (010,sup)
0000 111011 aaaaaa 0000000u uu000ccc cas.l Dc,Du,ea (020)
0000 111011 111100 nnnn000u uu000ccc cas2.l Dc1:Dc2,Du1:Du2,
nnnn000u uu000ccc (Rn):(Rn) (020)
0000 nnn100 aaaaaa btst Dn,a
0000 nnn101 aaaaaa bchg Dn,a
0000 ddd10z 001sss dddddddd dddddddd movep.z data16(As),Dd
0000 nnn110 aaaaaa bclr Dn,a
0000 nnn111 aaaaaa bset Dn,a
0000 sss11z 001ddd dddddddd dddddddd movep.z Ds,data16(Ad)
0001 dddddd ssssss move.b as,ad (dddddd reversed)
0010 dddddd ssssss move.l as,ad (dddddd reversed)
0010 ddd001 ssssss movea.l as,Ad
0011 dddddd ssssss move.w as,ad (dddddd reversed)
0011 ddd001 ssssss movea.w as,Ad
0100 0000zz aaaaaa negx.z a
0100 000011 aaaaaa move SR,a (010,sup)
0100 0010zz aaaaaa clr.z a
0100 001011 aaaaaa move CCR,a (010)
0100 0100zz aaaaaa neg.z a
0100 010011 aaaaaa move a,CCR
0100 0110zz aaaaaa not.z a
0100 011011 aaaaaa move a,SR (sup)
0100 100000 aaaaaa nbcd a
0100 100000 001nnn dddddddd dddddddd link An,#disp32.l (020)
dddddddd dddddddd
0100 100001 000nnn swap Dn
0100 100001 001vvv bkpt #vector (010)
0100 100001 aaaaaa pea a
0100 10001z 000nnn ext.z Dn
0100 10001z aaaaaa a6543210 d6543210 movem.z reg-list,a (rev in pred mode)
0100 1010zz aaaaaa tst.z a
0100 101011 aaaaaa tas a
0100 101011 111100 illegal
0100 101011 111010 bgnd (cpu32)
0100 110000 aaaaaa 0lll0000 0000hhhh mulu.l a,Dl (020)
0100 110000 aaaaaa 0lll0100 0000hhhh mulu.q a,Dh:Dl (020)
0100 110000 aaaaaa 0lll1000 0000hhhh muls.l a,Dl (020)
0100 110000 aaaaaa 0lll1100 0000hhhh muls.q a,Dh:Dl (020)
0100 110001 aaaaaa 0qqq0000 00000rrr divu.l a,Dq (020)
0100 110001 aaaaaa 0qqq0100 00000rrr divu.q a,Dr:Dq (020)
0100 110001 aaaaaa 0qqq1000 00000rrr divs.l a,Dq (020)
0100 110001 aaaaaa 0qqq1100 00000rrr divs.q a,Dr:Dq (020)
0100 11001z aaaaaa a6543210 d6543210 movem.z a,reg-list (rev in pred mode)
0100 111001 00vvvv trap #vector
0100 111001 010nnn dddddddd dddddddd link An,data16
0100 111001 011nnn unlk An
0100 111001 100nnn move An,USP (sup)
0100 111001 101nnn move USP,An (sup)
0100 111001 110000 reset (sup)
0100 111001 110001 nop
0100 111001 110010 dddddddd dddddddd stop #data16 (sup)
0100 111001 110011 rte (sup)
0100 111001 110100 rtd (010)
0100 111001 110101 rts
0100 111001 110110 trapv
0100 111001 110111 rtr
0100 111001 111010 nnnn0000 00000000 movec SFC,Rn (010,sup)
0100 111001 111010 nnnn0000 00000001 movec DFC,Rn (010,sup)
0100 111001 111010 nnnn0000 00000010 movec CACR,Rn (020,sup)
0100 111001 111010 nnnn1000 00000000 movec USP,Rn (010,sup)
0100 111001 111010 nnnn1000 00000001 movec VBR,Rn (010,sup)
0100 111001 111010 nnnn1000 00000010 movec CAAR,Rn (020,sup)
0100 111001 111010 nnnn1000 00000011 movec MSP,Rn (020,sup)
0100 111001 111010 nnnn1000 00000100 movec ISP,Rn (020,sup)
0100 111001 111011 nnnn0000 00000000 movec Rn,SFC (010,sup)
0100 111001 111011 nnnn0000 00000001 movec Rn,DFC (010,sup)
0100 111001 111011 nnnn0000 00000010 movec Rn,CACR (020,sup)
0100 111001 111011 nnnn1000 00000000 movec Rn,USP (010,sup)
0100 111001 111011 nnnn1000 00000001 movec Rn,VBR (010,sup)
0100 111001 111011 nnnn1000 00000010 movec Rn,CAAR (020,sup)
0100 111001 111011 nnnn1000 00000011 movec Rn,MSP (020,sup)
0100 111001 111011 nnnn1000 00000100 movec Rn,ISP (020,sup)
0100 nnn100 aaaaaa chk.l a,Dn (020)
0100 nnn110 aaaaaa chk.w a,Dn
0100 nnn111 aaaaaa lea a,An
0100 100111 000nnn extb Dn (020)
0100 111010 aaaaaa jsr a
0100 111011 aaaaaa jmp a
0101 ddd0zz aaaaaa addq.z #data3,a (data3 = 8,1..7)
0101 ddd1zz aaaaaa subq.z #data3,a (data3 = 8,1..7)
0101 cccc11 aaaaaa sCC a
0101 cccc11 001nnn llllllll llllllll dbCC Dn,label
0101 cccc11 111010 dddddddd dddddddd trapCC #operand.w (020)
0101 cccc11 111011 longword trapCC #operand.l (020)
0101 cccc11 111100 trapCC (020)
0110 0000 llllllll bra label
0110 0001 llllllll bsr label
0110 cccc llllllll bCC label
0111 nnn0 dddddddd moveq #data8,Dn
1000 nnn0zz aaaaaa or.z a,Dn
1000 nnn011 aaaaaa divu.w a,Dn
1000 nnn1zz aaaaaa or.z Dn,a
1000 nnn111 aaaaaa divs.w a,Dn
1000 ddd100 000sss sbcd Ds,Dd
1000 ddd100 001sss sbcd -(As),-(Ad)
1000 ddd101 000sss dddddddd dddddddd pack Ds,Dd,#adj (020)
1000 ddd101 001sss dddddddd dddddddd pack -(As),-(Ad),#adj (020)
1000 ddd110 000sss dddddddd dddddddd unpk Ds,Dd,#adj (020)
1000 ddd110 001sss dddddddd dddddddd unpk -(As),-(Ad),#adj (020)
1001 nnn0zz aaaaaa sub.z a,Dn
1001 nnn1zz aaaaaa sub.z Dn,a
1001 nnnz11 aaaaaa suba.z a,An
1001 ddd1zz 000sss subx.z Ds,Dd
1001 ddd1zz 001sss subx.z -(As),-(Ad)
1011 nnn0zz aaaaaa cmp.z a,Dn
1011 nnn1zz aaaaaa eor.z a,Dn
1011 nnnz11 aaaaaa cmpa.z a,An
1011 ddd1zz 000sss cmpm.z Ds,Dd
1011 ddd1zz 001sss cmpm.z (As)+,(Ad)+
1100 nnn0zz aaaaaa and.z a,Dn
1100 nnn011 aaaaaa mulu.w a,Dn
1100 nnn1zz aaaaaa and.z Dn,a
1100 nnn111 aaaaaa muls.w a,Dn
1100 ddd100 000sss abcd Ds,Dd
1100 ddd100 001sss abcd -(As),-(Ad)
1100 ddd101 000sss exg Ds,Dd
1100 ddd101 001sss exg As,Ad
1100 ddd110 001sss exg As,Dd
1101 nnn0zz aaaaaa add.z a,Dn
1101 nnn1zz aaaaaa add.z Dn,a
1101 nnnz11 aaaaaa adda.z a,An
1101 ddd1zz 000sss addx.z Ds,Dd
1101 ddd1zz 001sss addx.z -(As),-(Ad)
1110 ccc0zz 000nnn asrd.z #ccc,Dn
1110 ccc1zz 000nnn asld.z #ccc,Dn
1110 ccc0zz 001nnn lsrd.z #ccc,Dn
1110 ccc1zz 001nnn lsld.z #ccc,Dn
1110 ccc0zz 010nnn roxrd.z #ccc,Dn
1110 ccc1zz 010nnn roxld.z #ccc,Dn
1110 ccc0zz 011nnn rord.z #ccc,Dn
1110 ccc1zz 011nnn rold.z #ccc,Dn
1110 ccc0zz 100nnn asrd.z Dc,Dn
1110 ccc1zz 100nnn asld.z Dc,Dn
1110 ccc0zz 101nnn lsrd.z Dc,Dn
1110 ccc1zz 101nnn lsld.z Dc,Dn
1110 ccc0zz 110nnn roxrd.z Dc,Dn
1110 ccc1zz 110nnn roxld.z Dc,Dn
1110 ccc0zz 111nnn rord.z Dc,Dn
1110 ccc1zz 111nnn rold.z Dc,Dn
1110 000011 aaaaaa asrd a
1110 000111 aaaaaa asld a
1110 001011 aaaaaa lsrd a
1110 001111 aaaaaa lsld a
1110 010011 aaaaaa roxrd a
1110 010111 aaaaaa roxld a
1110 011011 aaaaaa rord a
1110 011111 aaaaaa rold a
1110 100011 aaaaaa 0000dooo oofwwwww bftst a[offs:wid] (020)
1110 100111 aaaaaa 0nnndooo oofwwwww bfextu a[offs:wid],Dn (020)
1110 101011 aaaaaa 0000dooo oofwwwww bfchg a[offs:wid] (020)
1110 101111 aaaaaa 0nnndooo oofwwwww bfexts a[offs:wid],Dn (020)
1110 110011 aaaaaa 0000dooo oofwwwww bfclr a[offs:wid] (020)
1110 110111 aaaaaa 0nnndooo oofwwwww bfffo a[offs:wid],Dn (020)
1110 111011 aaaaaa 0000dooo oofwwwww bfset a[offs:wid] (020)
1110 111111 aaaaaa 0nnndooo oofwwwww bfins Dn,a[offs:wid] (020)
1111 000000 aaaaaa 0000100f 00000000 pmove[fd] a,tt0 (030,sup)
1111 000000 aaaaaa 0000110f 00000000 pmove[fd] a,tt1 (030,sup)
1111 000000 aaaaaa 0000101f 00000000 pmove tt0,a (030,sup)
1111 000000 aaaaaa 0000111f 00000000 pmove tt1,a (030,sup)
1111 000000 aaaaaa 001000r0 000fffff pload fc,a (851,030,sup)
1111 000000 aaaaaa 00100100 mmmfffff pflusha (851,sup)
1111 000000 aaaaaa 00110000 mmmfffff pflush fc,#mask (851,sup)
1111 000000 aaaaaa 00111000 mmmfffff pflush fc,#mask,a (851,sup)
1111 000000 aaaaaa 0100000f 00000000 pmove[fd] a,tc (030,sup)
1111 000000 aaaaaa 0100100f 00000000 pmove[fd] a,srp (030,sup)
1111 000000 aaaaaa 0100110f 00000000 pmove[fd] a,crp (030,sup)
1111 000000 aaaaaa 0100001f 00000000 pmove tc,a (030,sup)
1111 000000 aaaaaa 0100101f 00000000 pmove srp,a (030,sup)
1111 000000 aaaaaa 0100111f 00000000 pmove crp,a (030,sup)
1111 000000 aaaaaa 01000000 00000000 pmove a,tc (851,sup)
1111 000000 aaaaaa 01000100 00000000 pmove a,drp (851,sup)
1111 000000 aaaaaa 01001000 00000000 pmove a,srp (851,sup)
1111 000000 aaaaaa 01001100 00000000 pmove a,crp (851,sup)
1111 000000 aaaaaa 01010000 00000000 pmove a,cal (851,sup)
1111 000000 aaaaaa 01010100 00000000 pmove a,val (851,sup)
1111 000000 aaaaaa 01011000 00000000 pmove a,scc (851,sup)
1111 000000 aaaaaa 01011100 00000000 pmove a,ac (851,sup)
1111 000000 aaaaaa 01000010 00000000 pmove tc,a (851,sup)
1111 000000 aaaaaa 01000110 00000000 pmove drp,a (851,sup)
1111 000000 aaaaaa 01001010 00000000 pmove srp,a (851,sup)
1111 000000 aaaaaa 01001110 00000000 pmove crp,a (851,sup)
1111 000000 aaaaaa 01010010 00000000 pmove cal,a (851,sup)
1111 000000 aaaaaa 01010110 00000000 pmove val,a (851,sup)
1111 000000 aaaaaa 01011010 00000000 pmove scc,a (851,sup)
1111 000000 aaaaaa 01011110 00000000 pmove ac,a (851,sup)
1111 000000 aaaaaa 01100000 00000000 pmove a,mmusr (030,sup)
1111 000000 aaaaaa 01100010 00000000 pmove mmusr,a (030,sup)
1111 000000 aaaaaa 100lll00 000fffff ptestw fc,a,#level (851,030,sup)
1111 000000 aaaaaa 100lll10 000fffff ptestr fc,a,#level (851,030,sup)
1111 000000 aaaaaa 100lll01 rrrfffff ptestw fc,a,#level,An (851,030,sup)
1111 000000 aaaaaa 100lll11 rrrfffff ptestr fc,a,#level,An (851,030,sup)
1111 000000 aaaaaa 10100000 00000000 pflushr a (851,sup)
1111 000001 001nnn 00000000 00cccccc pdbCC.w Dn,label (851,sup)
1111 000001 aaaaaa 00000000 00cccccc psCC (851,sup)
1111 00001z cccccc w [w] pbCC.z label (851,sup)
1111 000100 aaaaaa psave a (851,sup)
1111 000101 aaaaaa prestore a (851,sup)
1111 001000 aaaaaa 011nnnmmm kkkkkkk fmove.p fpm,a{,Dn|#k} (88x,040)
1111 010000 000nnn pflushn (An) (040,sup)
1111 010000 001nnn pflush (An) (040,sup)
1111 010000 010nnn pflushan (040,sup)
1111 010000 011nnn pflusha (040,sup)
1111 0100cc 001nnn cinvl caches,(An) (sup,040)
1111 0100cc 010nnn cinvp caches,(An) (sup,040)
1111 0100cc 011nnn cinva caches (sup,040)
1111 0100cc 101nnn cpushl caches,(An) (sup,040)
1111 0100cc 110nnn cpushp caches,(An) (sup,040)
1111 0100cc 111nnn cpusha caches (sup,040)
1111 010101 001nnn ptestw An (040,sup)
1111 010101 101nnn ptestr An (040,sup)
1111 100000 000000 00000001 11000000 lpstop #data (cpu32)
1111 100000 000mmm 0xxx0000 zz000yyy tblu.z Dym:Dyn,Dx
1111 100000 000mmm 0xxx0100 zz000yyy tblun.z Dym:Dyn,Dx
1111 100000 aaaaaa 0xxx0001 zz000000 tblu.z a,Dx
1111 100000 aaaaaa 0xxx0101 zz000000 tblun.z a,Dx
1111 100000 000mmm 0xxx1000 zz000yyy tbls.z Dym:Dyn,Dx
1111 100000 000mmm 0xxx1100 zz000yyy tblsn.z Dym:Dyn,Dx
1111 100000 aaaaaa 0xxx1001 zz000000 tbls.z a,Dx
1111 100000 aaaaaa 0xxx1101 zz000000 tblsn.z a,Dx
1111 100001 111010 00000000 00cccccc ptrapCC #oper.w (851)
1111 100001 111011 00000000 00cccccc ptrapCC #oper.l (851)
1111 100001 111100 00000000 00cccccc ptrapCC (851)
1111 ccc000 aaaaaa CPgen a,user-defined (020)
1111 ccc001 aaaaaa 00000000 00cccccc CPsCC (020)
1111 ccc001 001nnn 00000000 00cccccc CPdbCC Dn,disp16 (020)
1111 ccc001 111010 00000000 00cccccc CPtrapCC #oper.w (020)
1111 ccc001 111011 00000000 00cccccc CPtrapCC #oper.l (020)
1111 ccc001 111100 00000000 00cccccc CPtrapCC (020)
1111 ccc01z cccccc dddddddd dddddddd CPbCC.z disp16 (020)
1111 ccc100 aaaaaa CPsave a (020,sup)
1111 ccc101 aaaaaa CPrestore a (020,sup)
1111 ccc000 000000 010111nnn rrrrrrr fmovecr.l #ccc,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0000001 fint.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0000010 fsinh.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0000011 fintrz.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0000110 flognp1.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0001001 ftanh.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0001010 fatan.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0001100 fasin.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0001101 fatanh.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0001110 fsin.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0001111 ftan.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0010000 fetox.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0010001 ftwotox.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0010010 ftentox.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0010100 flogn.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0010101 flog10.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0010110 flog2.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0011001 fcosh.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0011100 facos.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0011101 fcos.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0011110 fgetexp.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0011111 fgetman.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0100001 fmod.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0100100 fsgldiv.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0100101 frem.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0100110 fscale.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0100111 fsglmul.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmsss 0110ccc fsincos.z fpm/a,fpc:fps (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0111000 fcmp.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn 0111010 ftst.z fpm/a (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn g???d?? fabs.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn g000d00 fmove.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn g000d0x fsqrt.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn g011d10 fneg.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn g100d00 fdiv.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn g100d10 fadd.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn g100d11 fmul.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 0r0mmmnnn g101d00 fsub.z fpm/a,fpn (88x,040)
1111 ccc000 aaaaaa 100001000 0000000 fmove.l a,fpiar (88x,040)
1111 ccc000 aaaaaa 100010000 0000000 fmove.l a,fpsr (88x,040)
1111 ccc000 aaaaaa 100100000 0000000 fmove.l a,fpcr (88x,040)
1111 ccc000 aaaaaa 100csi00 00000000 fmovem.z a,list (88x,040)
1111 ccc000 aaaaaa 101001000 0000000 fmove.l fpiar,a (88x,040)
1111 ccc000 aaaaaa 101010000 0000000 fmove.l fpsr,a (88x,040)
1111 ccc000 aaaaaa 101100000 0000000 fmove.l fpcr,a (88x,040)
1111 ccc000 aaaaaa 101csi00 00000000 fmovem.z list,a (88x,040)
1111 ccc000 aaaaaa 110m0000 rrrrrrrr fmovem.z a,list (88x,040)
1111 ccc000 aaaaaa 110m1000 0nnn0000 fmovem.z a,Dn (88x,040)
1111 ccc000 aaaaaa 111m0000 rrrrrrrr fmovem.z list,a (88x,040)
1111 ccc000 aaaaaa 111m1000 0mmm0000 fmovem.z Dm,a (88x,040)
1111 ccc001 001nnn 00000000 00cccccc fdbCC.z Dn,disp16 (88x,040)
1111 ccc001 111010 00000000 00cccccc ftrapCC #oper.w (88x,040)
1111 ccc001 111011 00000000 00cccccc ftrapCC #oper.l (88x,040)
1111 ccc001 111100 00000000 00cccccc ftrapCC (88x,040)
1111 ccc001 aaaaaa 00000000 00cccccc fsCC.b (88x,040)
1111 ccc010 000000 00000000 00000000 fnop (88x,040)
1111 ccc01z cccccc dddddddd dddddddd fbCC.z disp16 (88x,040)
1111 ccc100 aaaaaa fsave a (88x,040,sup)
1111 ccc101 aaaaaa frestore a (88x,040,sup)
coprocessor primitives (020)
1p100100 00000000 busy
cpd00001 llllllll transfer multiple coprocessor registers
cpd0001s 00000000 transfer status register and scanpc
1p000100 00000000 supervisor check
cpd00110 00000000 transfer multiple processor registers
cp000111 00000000 transfer operation word
cp00100i 000000ft null
cp001010 00000000 evaluate and transfer effective address
cpd01100 0000nnnn transfer single main processor register
cpd01101 00000000 transfer main processor control register
cpd1110l llllllll transfer to/from top of stack
cp001111 llllllll transfer from instruction stream
cpd10aaa llllllll evaluate effective address and transfer data
0p011101 vvvvvvvv take mid-instruction exception
0p011110 vvvvvvvv take post-instruction exception
cp100000 llllllll write to previously evaluated effective address
subfields:
ddd data3 (1..8)
zz 00=b, 01=w, 10=l
ss 01=b, 10=w, 11=l
z 0=w, 1=l
s 0=l, 1=w
llllllll if $00 -> 16 bits label follows
llllllll if $ff -> 32 bits label follows (020)
d bitfields: 0 offset is imm, 1 offs = Dr
f bitfields: 0 width is imm, 1 width = Dr
addressing modes (aaaaaa):
000 nnn Dn
001 nnn An
010 nnn (An)
011 nnn (An)+
100 nnn -(An)
101 nnn dddddddd dddddddd (d16,An)
110 nnn iiiiz000 dddddddd (d8,An,Ri.z)
iiiizss0 dddddddd (d8,An,Ri.z*scale) (020)
iiiizss1 bfxx0iii (bd,An,Ri.z*scale) (020)
1 1 = base register suppressed
1 1 = index operand suppressed
xx base disp size (01=null disp, 10=word, 11=long)
0 000 ( bd,An,Ri.z*scale )
0 001 ([bd,An,Ri.z*scale] )
0 010 ([bd,An,Ri.z*scale],od.w)
0 011 ([bd,An,Ri.z*scale],od.l)
0 100 reserved
0 101 ([bd,An],Ri.z*scale )
0 110 ([bd,An],Ri.z*scale,od.w)
0 111 ([bd,An],Ri.z*scale,od.l)
1 000 ( bd,An )
1 001 ([bd,An] )
1 010 ([bd,An] ,od.w)
1 011 ([bd,An] ,od.l)
111 000 dddddddd dddddddd addr16
111 001 longword addr32
111 010 dddddddd dddddddd d16(PC)
111 011 iiiiz000 dddddddd d8(PC,ix)
iiiizss0 dddddddd d8(PC,ix*scale) (020)
iiiizss1 bfxx0iii d8(PC,ix*scale) (020)
111 100 imm/implied
flags:
0000 t allways
0001 f never
0010 hi
0011 ls
0100 cc
0101 cs
0110 ne
0111 eq
1000 vc
1001 vs
1010 pl
1011 mi
1100 ge
1101 lt
1110 gt
1111 le

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68000abc.txt
Instruction set of the 68000 in alphabetical order
1988/wjvg
0 2 3 4 5
abcd Ds,Dd 1100 ddd100 000sss
abcd -(As),-(Ad) 1100 ddd100 001sss
add.z a,Dd 1101 ddd0zz aaaaaa
add.z Ds,a 1101 sss1zz aaaaaa
adda.z a,Ad 1101 dddz11 aaaaaa
addi.z #kz,a 0000 0110zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk
addq.z #k3,a 0101 kkk0zz aaaaaa
addx.z Ds,Dd 1101 ddd1zz 000sss
addx.z -(As),-(Ad) 1101 ddd1zz 001sss
and.z a,Dd 1100 ddd0zz aaaaaa
and.z Ds,a 1100 sss1zz aaaaaa
andi.z #kz,a 0000 0010zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk
asld.z Ds,Dd 1110 sss1zz 100ddd
asld.z #k,Dd 1110 kkk1zz 000ddd
asld.w #1,a 1110 000111 aaaaaa
asrd.z Ds,Dd 1110 sss0zz 100ddd
asrd.z #k,Dd 1110 kkk0zz 000ddd
asrd.w #1,a 1110 000011 aaaaaa
bcc label 0110 ccccll llllll if zero, a 16bit address follows
bra label 0110 0000ll llllll if zero, a 16bit address follows
bsr label 0110 0001ll llllll if zero, a 16bit address follows
bchg #n,a 0000 100001 aaaaaa 00000000 000nnnnn
bchg Ds,a 0000 sss101 aaaaaa
bclr #n,a 0000 100010 aaaaaa 00000000 000nnnnn
bclr Ds,a 0000 sss110 aaaaaa
bset #n,a 0000 100011 aaaaaa 00000000 000nnnnn
bset Ds,a 0000 sss111 aaaaaa
btst #n,a 0000 100000 aaaaaa 00000000 000nnnnn
btst Ds,a 0000 sss100 aaaaaa
chk.w a,Dd 0100 ddd110 aaaaaa
clr.z a 0100 0010zz aaaaaa
cmp.z a,Dd 1011 ddd0zz aaaaaa
cmpa.z a,Ad 1011 dddz11 aaaaaa
cmpi.z #kz,a 0000 1100zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk
cmpm.z Ds,Dd 1011 ddd1zz 000sss
cmpm.z (As)+,(Ad)+ 1011 ddd1zz 001sss
db(cc) Ds,label 0101 cccc11 001sss llllllll llllllll
divs.w a,Dd 1000 ddd111 aaaaaa
divu.w a,Dd 1000 ddd011 aaaaaa
eor.z a,Dd 1011 ddd1zz aaaaaa
eori.z #kz,a 0000 1010zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk
exg.l As,Ad 1100 ddd101 001sss
exg.l Ds,Dd 1100 ddd101 000sss
exg.l As,Dd 1100 ddd110 001sss
ext.z Dd 0100 10001z 000ddd
jmp a 0100 111011 aaaaaa
jsr a 0100 111010 aaaaaa
lea a,Ad 0100 ddd111 aaaaaa
link As,d16 0100 111001 010sss dddddddd dddddddd
lsld.z Ds,Dd 1110 sss1zz 101ddd
lsld.z #k,Dd 1110 kkk1zz 001ddd
lsld.w #1,a 1110 001111 aaaaaa
lsrd.z Ds,Dd 1110 sss0zz 101ddd
lsrd.z #k,Dd 1110 kkk0zz 001ddd
lsrd.w #1,a 1110 001011 aaaaaa
move SR,a 0100 000011 aaaaaa
move a,CCR 0100 010011 aaaaaa
move a,SR 0100 011011 aaaaaa
move As,USP 0100 111001 100sss
move USP,Ad 0100 111001 101ddd
move.b as,ad 0001 dddddd ssssss (dddddd reversed)
move.l as,ad 0010 dddddd ssssss (dddddd reversed)
move.w as,ad 0011 dddddd ssssss (dddddd reversed)
movem.z a,reg-list 0100 11001z aaaaaa a6543210 d6543210
movem.z reg-list,a 0100 10001z aaaaaa a6543210 d6543210
movep.z Ds,d16(Ad) 0000 sss11z 001ddd dddddddd dddddddd
movep.z d16(As),Dd 0000 ddd10z 001sss dddddddd dddddddd
moveq.l #k8,Dd 0111 ddd0kk kkkkkk
muls.w a,Dd 1100 ddd111 aaaaaa
mulu.w a,Dd 1100 ddd011 aaaaaa
nbcd a 0100 100000 aaaaaa
neg.z a 0100 0100zz aaaaaa
negx.z a 0100 0000zz aaaaaa
nop 0100 111001 110001
not.z a 0100 0110zz aaaaaa
or.z a,Dd 1000 ddd0zz aaaaaa
or.z Ds,a 1000 sss1zz aaaaaa
ori.z #kz,a 0000 0000zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk
pea a 0100 100001 aaaaaa
reset 0100 111001 110000
rold.z Ds,Dd 1110 sss1zz 111ddd
rold.z #k,Dd 1110 kkk1zz 011ddd
rold.w #1,a 1110 011111 aaaaaa
rord.z Ds,Dd 1110 sss0zz 111ddd
rord.z #k,Dd 1110 kkk0zz 011ddd
rord.w #1,a 1110 011011 aaaaaa
roxld.z Ds,Dd 1110 sss1zz 110ddd
roxld.z #k,Dd 1110 kkk1zz 010ddd
roxld.w #1,a 1110 010111 aaaaaa
roxrd.z Ds,Dd 1110 sss0zz 110ddd
roxrd.z #k,Dd 1110 kkk0zz 010ddd
roxrd.w #1,a 1110 010011 aaaaaa
rte 0100 111001 110011
rtr 0100 111001 110111
rts 0100 111001 110101
sbcd Ds,Dd 1000 ddd100 000sss
sbcd -(As),-(Ad) 1000 ddd100 001sss
stcc.b a 0101 cccc11 aaaaaa
stop #k16 0100 111001 110010 kkkkkkkk kkkkkkkk
sub.z Ds,a 1001 sss1zz aaaaaa
sub.z a,Dd 1001 ddd0zz aaaaaa
subi.z #kz,a 0000 0100zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk
suba.z a,Ad 1001 dddz11 aaaaaa
subq.z #k3,a 0101 kkk1zz aaaaaa
subx.z Ds,Dd 1001 ddd1zz 000sss
subx.z -(As),-(Ad) 1001 ddd1zz 001sss
swap.w Dd 0100 100001 000ddd
tas.b a 0100 101011 aaaaaa
trap vector 0100 111001 00vvvv
trapv 0100 111001 110110
tst.z a 0100 1010zz aaaaaa
unlk Ad 0100 111001 011ddd
general subfields
zz 00=b, 01=w, 10=l
z 0=w, 1=l
kkk immediate data in addq etc.: 0==8
immediate data in movq is sign extended to 32bits
shift count also represents 1..8 (how?)
addresssing modes (aaaaaa):
000 rrr Dr
001 rrr Ar
010 rrr (Ar)
011 rrr (Ar)+
100 rrr -(Ar)
101 rrr d16(Ar) dddddddd dddddddd
110 rrr d8(Ar,ix) aiiiz000 dddddddd
111 000 addr16 dddddddd dddddddd
111 001 addr32 dddddddd dddddddd ddddddddd dddddddd
111 010 d16(PC) dddddddd dddddddd
111 011 d8(PC,ix) aiiiz000 dddddddd
111 100 imm/implied
flags:
0000 t allways or bra ipv btr
0001 f never or bsr ipv bnv
0010 hi
0011 ls
0100 cc
0101 cs
0110 ne
0111 eq
1000 vc
1001 vs
1010 pl
1011 mi
1100 ge
1101 lt
1110 gt
1111 le

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68000bin.txt
Instruction set of the 68000 in binary order
1988/wjvg
0 2 3 4 5
0000 0000zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk ori.z #kz,a
0000 0010zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk andi.z #kz,a
0000 0100zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk subi.z #kz,a
0000 0110zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk addi.z #kz,a
0000 1010zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk eori.z #kz,a
0000 1100zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk cmpi.z #kz,a
0000 100000 aaaaaa 00000000 000nnnnn btst #n,a
0000 100001 aaaaaa 00000000 000nnnnn bchg #n,a
0000 100010 aaaaaa 00000000 000nnnnn bclr #n,a
0000 100011 aaaaaa 00000000 000nnnnn bset #n,a
0000 sss100 aaaaaa btst Ds,a
0000 sss101 aaaaaa bchg Ds,a
0000 sss110 aaaaaa bclr Ds,a
0000 sss111 aaaaaa bset Ds,a
0000 ddd10z 001sss dddddddd dddddddd movep.z d16(As),Dd
0000 sss11z 001ddd dddddddd dddddddd movep.z Ds,d16(Ad)
0001 dddddd ssssss (dddddd reversed) move.b as,ad
0010 dddddd ssssss (dddddd reversed) move.l as,ad
0011 dddddd ssssss (dddddd reversed) move.w as,ad
0100 0000zz aaaaaa negx.z a
0100 000011 aaaaaa move SR,a
0100 0010zz aaaaaa clr.z a
0100 0100zz aaaaaa neg.z a
0100 010011 aaaaaa move a,CCR
0100 0110zz aaaaaa not.z a
0100 011011 aaaaaa move a,SR
0100 100000 aaaaaa nbcd a
0100 100001 000ddd swap.w Dd
0100 100001 aaaaaa pea a
0100 10001z 000ddd ext.z Dd
0100 10001z aaaaaa a6543210 d6543210 movem.z reg-list,a
0100 1010zz aaaaaa tst.z a
0100 101011 aaaaaa tas.b a
0100 11001z aaaaaa a6543210 d6543210 movem.z a,reg-list
0100 111001 00vvvv trap #vector
0100 111001 010sss dddddddd dddddddd link As,#k16
0100 111001 011ddd unlk Ad
0100 111001 100sss move As,USP
0100 111001 101ddd move USP,Ad
0100 111001 110000 reset
0100 111001 110001 nop
0100 111001 110010 kkkkkkkk kkkkkkkk stop #k16
0100 111001 110011 rte
0100 111001 110101 rts
0100 111001 110110 trapv
0100 111001 110111 rtr
0100 111010 aaaaaa jsr a
0100 111011 aaaaaa jmp a
0100 ddd110 aaaaaa chk.w a,Dd
0100 ddd111 aaaaaa lea a,Ad
0101 cccc11 001sss llllllll llllllll db(cc) Ds,label
0101 cccc11 aaaaaa stcc.b a
0101 kkk0zz aaaaaa addq.z #k3,a
0101 kkk1zz aaaaaa subq.z #k3,a
0110 0000ll llllll if zero, a 16bit address follows bra label
0110 0001ll llllll if zero, a 16bit address follows bsr label
0110 ccccll llllll if zero, a 16bit address follows bcc label
0111 ddd0kk kkkkkk moveq.l #k8,Dd
1000 ddd0zz aaaaaa or.z a,Dd
1000 ddd011 aaaaaa divu.w a,Dd
1000 ddd100 000sss sbcd Ds,Dd
1000 ddd100 001sss sbcd -(As),-(Ad)
1000 sss1zz aaaaaa or.z Ds,a
1000 ddd111 aaaaaa divs.w a,Dd
1001 ddd0zz aaaaaa sub.z a,Dd
1001 ddd1zz 000sss subx.z Ds,Dd
1001 ddd1zz 001sss subx.z -(As),-(Ad)
1001 sss1zz aaaaaa sub.z Ds,a
1001 dddz11 aaaaaa suba.z a,Ad
1011 ddd0zz aaaaaa cmp.z a,Dd
1011 ddd1zz 000sss cmpm.z Ds,Dd
1011 ddd1zz 001sss cmpm.z (As)+,(Ad)+
1011 ddd1zz aaaaaa eor.z a,Dd
1011 dddz11 aaaaaa cmpa.z a,Ad
1100 ddd0zz aaaaaa and.z a,Dd
1100 ddd011 aaaaaa mulu.w a,Dd
1100 ddd100 000sss abcd Ds,Dd
1100 ddd101 000sss exg.l Ds,Dd
1100 ddd100 001sss abcd -(As),-(Ad)
1100 ddd101 001sss exg.l As,Ad
1100 ddd110 001sss exg.l As,Dd
1100 sss1zz aaaaaa and.z Ds,a
1100 ddd111 aaaaaa muls.w a,Dd
1101 ddd0zz aaaaaa add.z a,Dd
1101 ddd1zz 000sss addx.z Ds,Dd
1101 ddd1zz 001sss addx.z -(As),-(Ad)
1101 sss1zz aaaaaa add.z Ds,a
1101 dddz11 aaaaaa adda.z a,Ad
1110 kkk0zz 000ddd asrd.z #k,Dd
1110 kkk0zz 001ddd lsrd.z #k,Dd
1110 kkk0zz 010ddd roxrd.z #k,Dd
1110 kkk0zz 011ddd rord.z #k,Dd
1110 kkk1zz 000ddd asld.z #k,Dd
1110 kkk1zz 001ddd lsld.z #k,Dd
1110 kkk1zz 010ddd roxld.z #k,Dd
1110 kkk1zz 011ddd rold.z #k,Dd
1110 sss0zz 100ddd asrd.z Ds,Dd
1110 sss0zz 101ddd lsrd.z Ds,Dd
1110 sss0zz 110ddd roxrd.z Ds,Dd
1110 sss0zz 111ddd rord.z Ds,Dd
1110 sss1zz 100ddd asld.z Ds,Dd
1110 sss1zz 101ddd lsld.z Ds,Dd
1110 sss1zz 110ddd roxld.z Ds,Dd
1110 sss1zz 111ddd rold.z Ds,Dd
1110 000011 aaaaaa asrd.w #1,a
1110 000111 aaaaaa asld.w #1,a
1110 001011 aaaaaa lsrd.w #1,a
1110 001111 aaaaaa lsld.w #1,a
1110 010011 aaaaaa roxrd.w #1,a
1110 010111 aaaaaa roxld.w #1,a
1110 011011 aaaaaa rord.w #1,a
1110 011111 aaaaaa rold.w #1,a
general subfields
zz 00=b, 01=w, 10=l
z 0=w, 1=l
kkk immediate data in addq etc.: 0==8
immediate data in movq is sign extended to 32bits
shift count also represents 1..8 (how?)
addressing modes (aaaaaa):
000 rrr Dr
001 rrr Ar
010 rrr (Ar)
011 rrr (Ar)+
100 rrr -(Ar)
101 rrr d16(Ar) dddddddd dddddddd
110 rrr d8(Ar,ix) aiiiz000 dddddddd
111 000 addr16 dddddddd dddddddd
111 001 addr32 dddddddd dddddddd ddddddddd dddddddd
111 010 d16(PC) dddddddd dddddddd
111 011 d8(PC,ix) aiiiz000 dddddddd
111 100 imm/implied
flags:
0000 t allways or bra ipv btr
0001 f never or bsr ipv bnv
0010 hi
0011 ls
0100 cc
0101 cs
0110 ne
0111 eq
1000 vc
1001 vs
1010 pl
1011 mi
1100 ge
1101 lt
1110 gt
1111 le
*end

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This subfolder contains the documents and other stuff for Motorola-Freescale 68000 CPU.
[Main Wikipedia article on 68000](https://en.wikipedia.org/wiki/Motorola_68000)
| Files | Description | Source |
| ----- | ----------- | ------ |
| 68000 opcodes.pdf | 68000 Instruction Set in detail | URL not determined |
| 68000bin.txt | 68000 instruction set in binary order | URL not determined |
| manual.pdf | | |
| 68000abc.txt | 68000 instruction set in alphabetic order | URL not determined |
| M68000PRM.pdf | 68000 Programmer's Reference Manual | Believed to be obtained from Freescale website |

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This subfolder contains the documents and other stuff for Motorola-Freescale 680x0 CPU family.
[Main Wikipedia article on this family](https://en.wikipedia.org/wiki/Motorola_68000_series)
| Subfolders | Description |
| ---------- | ----------- |
| MC68000 | 68000 manuals |
| MC68020 | 68020 manuals |
| MC68030 | 68030 manuals |
| MC68040 | 68040 manuals |
| MC68060 | 68060 manuals |
| Files | Description | Source |
| ----- | ----------- | ------ |
| 680x0bin.txt | Instruction set of the 680x0 in binary order | URL not determined |
| architecture.pdf | | |
| references.txt | | |

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This subfolder contains the documents and other stuff for National Semiconductor 32000 CPU family.
[Main Wikipedia article on NS 32000](https://en.wikipedia.org/wiki/NS320xx)
| Files | Description | Source |
| ----- | ----------- | ------ |
| NS32c032.pdf | National Semiconductor 32c032 manual | https://stuff.mit.edu/afs/sipb/contrib/doc/specs/ic/cpu/ns32c032.pdf |

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This subfolder contains the documents and other stuff for DEC PDP-11 family.
[Main Wikipedia article on DEC PDP-11](https://en.wikipedia.org/wiki/PDP-11)
| Files | Description | Source |
| ----- | ----------- | ------ |
| PDP_11_Handbook_1969.pdf | PDP-11 Handbook | URL not determined |
| The_PDP-11_FAQ.htm | PDP-11 FAQ | URL not determined |

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<!-- saved from url=(0051)http://www.village.org/pdp11/faq.pages/PDPinst.html -->
<HTML><HEAD><TITLE>The PDP-11 FAQ</TITLE>
<META http-equiv=Content-Type content="text/html; charset=windows-1252">
<META content="MSHTML 6.00.2900.3059" name=GENERATOR></HEAD>
<BODY>
<H1><A name=PDPinst>What is the PDP-11 instruction set?</A></H1>
<P>The instruction set of the PDP-11 was designed towards a clean, general,
symmetric instruction set. It can be used as a register-based, stack-based, or
memory-based machine, depending on the programmer's preferences. Interrupt
responsiveness is also important, supported with multiple interrupt levels for
real-time computing as well as allowing for a separate interrupt handler for
each device that generates interrupts. </P>
<P>Word length is 16 bits with the leftmost, most significant bit (MSB) being
bit 15. There are eight general registers of 16 bits each. Register 7 is the
program counter (PC) and, by convention, Register 6 is the stack pointer (SP).
There is also a Processor Status Register/Word (PSW) which indicates the 4
condition code bits (N, Z, V, C), the Trace Trap bit, processor interrupt
priority, and 4 bits for current and previous operating modes. Addressing on the
-11 is linear from memory address 0 through 177777. Memory management allows
access to physical memory with addresses of up to 22 bits (17777777). All I/O
devices, registers etc are addressed as if they were part of memory. These live
in the 4KW of reserved memory space at the top of the addressing range.
Additionally, on most implementations of the PDP-11 architecture, the
processor's registers are memory-mapped to the range 17777700-17777717 (there
are many control registers beyond just the general registers, the specifics vary
between implementations). Thus Register 2 (R2) has an address of 17777702. All
word memory addresses are even, except for registers. In byte operations, an
even address specifies the least-significant byte and an odd address specifies
the most-significant byte. Specifying an odd byte in a word operation will
return an odd address trap. Memory addresses from 0 to 400 octal are reserved
for various exception traps such as timeouts, reserved instructions, parity,
etc., and device interrupts. </P>
<P>Addressing for the Single Operand, Double Operand and Jump instructions is
achieved via six bits: </P><PRE> _ _ _ _ _ _
|x|x|x|_|_|_|
|Mode |Reg |
</PRE>
<P>where the modes are as follows: (Reg = Register, Def = Deferred) </P><PRE> Mode 0 Reg Direct addressing of the register
Mode 1 Reg Def Contents of Reg is the address
Mode 2 AutoIncr Contents of Reg is the address, then Reg incremented
Mode 3 AutoIncrDef Content of Reg is addr of addr, then Reg Incremented
Mode 4 AutoDecr Reg is decremented then contents is address
Mode 5 AutoDecrDef Reg is decremented then contents is addr of addr
Mode 6 Index Contents of Reg + Following word is address
Mode 7 IndexDef Contents of Reg + Following word is addr of addr
</PRE>
<P>Note that the right-most bit of the mode is an indirection bit.
<P>Although not special cases, when dealing with R7 (aka the PC), some of these
operations are called different things: </P><PRE> _ _ _ _ _ _
|x|x|x|1|1|1|
|Mode | R7 |
Mode 2 Immediate Operand follows the instruction
Mode 3 Absolute Address of Operand follows the instruction
Mode 6 Relative Instr address+4+Next word is Address
Mode 7 RelativeDef Instr address+4+Next word is Address of address
</PRE>
<P>Mainstream instructions are broken into Single operand and Double operand
instructions, which in turn can be word or byte instructions. </P>
<H2>Double Operand Instructions</H2><PRE> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|b|i|i|i|s|s|s|s|s|s|d|d|d|d|d|d|
| | | : | : |
| | Op | Source | Dest |
</PRE>
<P>Bit 15, b, generally selects between word-sized (b=0) and byte-sized (b=1)
operands. In the table below, the mnemonics and names are given in the order
b=0/b=1. </P>
<P>The double operand instructions are: </P>
<DL>
<DT>b 000 ssssss dddddd
<DD>Non-double-operand instructions.
<P></P>
<DT>b 001 ssssss dddddd -- MOV/MOVB <I>Move Word/Byte</I>
<DD>Moves a value from source to destination.
<P></P>
<DT>b 010 ssssss dddddd -- CMP/CMPB <I>Compare Word/Byte</I>
<DD>Compares values by subtracting the destination from the source, setting
the condition codes, and then discarding the result of the subtraction.
<P></P>
<DT>b 011 ssssss dddddd -- BIT/BITB <I>Bit Test Word/Byte</I>
<DD>Performs a bit-wise AND of the source and the destination, sets the
condition codes, and then discards the result of the AND.
<P></P>
<DT>b 100 ssssss dddddd -- BIC/BICB <I>Bit Clear Word/Byte</I>
<DD>For each bit set in the source, that bit is cleared in the destination.
This is accomplished by taking the ones-complement of the source and ANDing it
with the destination. The result of the AND is stored in the destination.
<P></P>
<DT>b 101 ssssss dddddd -- BIS/BISB <I>Bit Set Word/Byte</I>
<DD>For each bit set in the source, that bit is set in the destination. This
is accomplished by ORing the source and destination, and storing the result in
the destination.
<P></P>
<DT>b 110 ssssss dddddd -- ADD/SUB <I>Add/Subtract Word</I>
<DD>Adds the source and destination, storing the results in the destination.
<P>Subtracts the source from the destination, storing the results in the
destination.
<P>Note that this is a special case for b=1, in that it does not indicate that
byte-wide operands are used.
<P></P>
<DT>b 111 xxxxxx xxxxxx
<DD>Arithmetic functions not supported by all implementations of the PDP-11
architecture. </DD></DL>
<H2>Single Operand Instructions</H2><PRE> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|b|0|0|0|i|i|i|i|i|i|d|d|d|d|d|d|
| | | : | : |
| | |Instruction| Dest |
</PRE>
<P>Bit 15, b, generally selects between word-sized (b=0) and byte-sized (b=1)
operands. In the table below, the mnemonics and names are given in the order
b=0/b=1. Unless otherwise stated, the operand is read for the data to operate
on, and the result is then written over that data. </P>
<P>The single operand instructions are: </P>
<DL>
<DT>b 000 000 011 dddddd -- SWAB/BPL <I>Swap Bytes/Branch Plus</I>
<DD>Swap bytes exchanges the two bytes found in the destination, writing the
result back to it.
<P>The branch (b=1) is described in the section on branches, below.
<P>Note that SWAB is actually a bit pattern from the range reserved for
branches. This particular pattern is otherwise unused, as it would be a
modification of BR, Branch Always, which has no obvious semantics.
<P></P>
<DT>b 000 101 000 dddddd -- CLR/CLRB <I>Clear Word/Byte</I>
<DD>Sets all the bits in destination to zero.
<P></P>
<DT>b 000 101 001 dddddd -- COM/COMB <I>Complement Word/Byte</I>
<DD>Calculates the ones-complement of the operand, and stores it. The
ones-complement is formed by inverting each bit (0-&gt;1, 1-&gt;0)
independently.
<P></P>
<DT>b 000 010 010 dddddd -- INC/INCB <I>Increment Word/Byte</I>
<DD>Adds one to the destination.
<P></P>
<DT>b 000 101 011 dddddd -- DEC/DECB <I>Decrement Word/Byte</I>
<DD>Subtracts one from the destination.
<P></P>
<DT>b 000 101 100 dddddd -- NEG/NEGB <I>Negate Word/Byte</I>
<DD>Calculates the twos-complement of the operand, and stores it. The
twos-complement is formed by adding one to the ones-complement. The effect is
the same as subtracting the operand from zero.
<P></P>
<DT>b 000 101 101 dddddd -- ADC/ADCB <I>Add Carry Word/Byte</I>
<DD>Adds the current value of the carry flag to the destination. This is
useful for implementing arithmetic subroutines with more than word-sized
operands.
<P></P>
<DT>b 000 101 110 dddddd -- SBC/SBCB <I>Subtract Carry Word/Byte</I>
<DD>Subtracts the current value of the carry flag from the destination. This
is useful for implementing arithmetic subroutines with more than word-sized
operands.
<P></P>
<DT>b 000 101 111 dddddd -- TST/TSTB <I>Test Word/Byte</I>
<DD>Sets the N (negative) and Z (zero) condition codes based on the value of
the operand.
<P></P>
<DT>b 000 110 000 dddddd -- ROR/RORB <I>Rotate Right Word/Byte</I>
<DD>Rotates the bits of the operand one position to the right. The right-most
bit is placed in the carry flag, and the carry flag is copied to the left-most
bit (bit 15) of the operand.
<P></P>
<DT>b 000 110 001 dddddd -- ROL/ROLB <I>Rotate Left Word/Byte</I>
<DD>Rotates the bits of the operand one position to the left. The left-most
bit is placed in the carry flag, and the carry flag is copied to the
right-most bit (bit 0) of the operand.
<P></P>
<DT>b 000 110 010 dddddd -- ASR/ASRB <I>Arithmetic Shift Right Word/Byte</I>
<DD>Shifts the bits of the operand one position to the right. The left-most
bit is duplicated. The effect is to perform a signed division by 2.
<P></P>
<DT>b 000 110 011 dddddd -- ASL/ASLB <I>Arithmetic Shift Left Word/Byte</I>
<DD>Shifts the bits of the operand one position to the left. The right-most
bit is set to zero. The effect is to perform a signed multiplication by 2.
<P></P>
<DT>b 000 110 100 dddddd -- MARK/MTPS <I>Mark/Move To Processor Status</I>
<DD>Mark is used as part of one of the subroutine call/ return sequences. The
operand is the number of parameters.
<P>MTPS is only on LSI-11s, and is used to move a byte to the processor status
word. This is needed because the LSI-11 does not support accessing registers
via memory addresses.
<P></P>
<DT>b 000 110 101 dddddd -- MFPI/MFPD <I>Move From Prev. Instruction/Data</I>
<DD>Pushes a word onto the current R6 stack from the operand address in the
previous address space, as indicated in the PSW. On PDP-11s that do not
support separate instruction and data spaces, MFPD is treated the same as
MFPI.
<P></P>
<DT>b 000 110 110 dddddd -- MTPI/MTPD <I>Move To Previous Instruction/Data</I>
<DD>Pops a word from the current stack as indicated in the PSW to the operand
address in the previous address space, as indicated in the PSW. On PDP-11s
that do not support separate instruction and data spaces, MTPD is treated the
same as MTPI.
<P></P>
<DT>b 000 110 111 dddddd -- SXT/MFPS <I>Sign Extend/Move From Processor
Status</I>
<DD>SXT sets the destination to zero if the N (negative) flag is clear, or to
all ones if N is set. This is useful for implementing arithmetic subroutines
with more than word-sized operands.
<P>MFPS copies the processor status byte to the indicated register. This only
exists on LSI-11s, and is needed there because those systems don't support
accessing registers via memory addresses. </P></DD></DL>
<H2>Branches</H2><PRE> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|b|0|0|0|b|b|b|b|d|d|d|d|d|d|d|d|
| Branch Code | Destination |
</PRE>
<P>The destination of a branch is +127 to -128 words from the word following the
branch instruction itself. This seems slightly odd, until you realize the
sequence of events: the branch instruction is read from memory and the PC
incremented. If the branch is to be taken, the offset is then added to the
current value of the PC. Since the PC has already been incremented, the offset
is thus relative to the following word. Note that all branch instructions are
one word long. </P>
<P>The various branches test the values of specific condition codes, and if the
tests succeed, the branch is taken. The condition codes are N (negative), Z
(zero), C (carry), and V (overflow). In the table below, the branch tests are
shown as boolean expressions. `x' stands for exclusive-OR. `v' stands for
inclusive-OR. </P>
<DL compact>
<DT>0 000 000 1dd dddddd
<DD>BR: Branch Always
<DT>0 000 001 0dd dddddd
<DD>BNE: Branch if Not Equal (Z==0)
<DT>0 000 001 1dd dddddd
<DD>BEQ: Branch if EQual (Z==1)
<DT>0 000 010 0dd dddddd
<DD>BGE: Branch if Greater or Equal (NxV == 0)
<DT>0 000 010 1dd dddddd
<DD>BLT: Branch if Less Than (NxV == 1)
<DT>0 000 011 0dd dddddd
<DD>BGT: Branch if Greater Than (Zv(NxV) == 0)
<DT>0 000 011 1dd dddddd
<DD>BLE: Branch if Less or Equal (Zv(NxV) == 1)
<DT>1 000 000 0dd dddddd
<DD>BPL: Branch if PLus (N == 0)
<DT>1 000 000 1dd dddddd
<DD>BMI: Branch if MInus (N == 1)
<DT>1 000 001 0dd dddddd
<DD>BHI: Branch if HIgher (C==0 and Z==0)
<DT>1 000 001 1dd dddddd
<DD>BLOS: Branch if Lower Or Same (CvZ == 1)
<DT>1 000 010 0dd dddddd
<DD>BVC: Branch if oVerflow Clear (V == 0)
<DT>1 000 010 1dd dddddd
<DD>BVS: Branch if oVerflow set (V == 1)
<DT>1 000 011 0dd dddddd
<DD>BCC: Branch if Carry Clear (C == 0) <BR><I>also known as</I><BR>BHIS:
Branch if Higher Or Same
<DT>1 000 011 1dd dddddd
<DD>BCS: Branch if Carry Set (C == 1) <BR><I>also known as</I><BR>BLO: Branch
if Lower </DD></DL>
<H2>Condition Code Operations</H2><PRE> _ _ _ _ _ _ _ _ _ _:_ _ _:_ _ _
|0|0|0|0|0|0|0|0|1|0|1|s|N|Z|V|C|
| O p c o d e | | Mask |
</PRE>
<P>General opcode 000240x. Set/Clear corresponding bits depending on sense of
bit 04 (set=1, clear=0). Codes 240 and 260 set/clear no bits and are, thus, used
as NOP. Although specific mnemonic are provided for each flag and all flags, any
combination may actually be set or cleared at a time. </P>
<P>General mnemonics are: </P>
<DL compact>
<DT>CLx
<DD>Clear x, where x is N, Z, V, or C
<DT>SEx
<DD>Set x, where x is N, Z, V, or C
<DT>CCC
<DD>Clear all condition codes
<DT>SCC
<DD>Set all condition codes </DD></DL><BR>
<DL compact>
<DT>0 000 000 010 1s0 000
<DD>NOP/NOP: No Operation
<DT>0 000 000 010 1s0 001
<DD>SEC/CLC: Set/Clear Carry
<DT>0 000 000 010 1s0 010
<DD>SEV/CLV: Set/Clear Overflow
<DT>0 000 000 010 1s0 100
<DD>SEZ/CLZ: Set/Clear Zero
<DT>0 000 000 010 1s1 000
<DD>SEN/CLN: Set/Clear Negative
<DT>0 000 000 010 1s1 111
<DD>SCC/CCC: Set/Clear All Condition Codes </DD></DL>
<H2>Other, Miscellaneous</H2><PRE> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|0|0|0|0|1|0|0|s|s|s|d|d|d|d|d|d|
| Opcode |Stack|Destination|
</PRE>
<P>
<DL compact>
<DT>0 000 100 sss dddddd -- JSR <I>Jump to Subroutine</I>
<DD>The actual sequence of steps taken is: <PRE> MOV &lt;source&gt;,-(R6)
MOV PC,&lt;source&gt;
JMP &lt;destination&gt;
</PRE><BR>
<P>Thus, it loads the calling address into the specified source register
(after saving the original contents). It then jumps to the destination. The
fun part is (as usual with the PDP-11) that the PC is a general register, and
the description above is the result when the PC is used as the source.
</P></DD></DL><PRE> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|0|0|0|0|0|0|0|0|1|0|0|0|0|s|s|s|
| Opcode |Stack|
</PRE>
<P>
<DL compact>
<DT>0 000 000 010 000 sss -- RTS <I>ReTurn from Subroutine</I>
<DD>Undoes the effects of a JSR. For predictable results, it is suggested that
the same register should be used as was named in the corresponding JSR
instruction.
<P>The actual operations involved are: <PRE> MOV &lt;source&gt;,PC
MOV (R6)+,&lt;source&gt;
</PRE><BR>
<P>This is the reverse of JSR. Obviously, the finesse here too is that you can
use the PC, to get what people normally consider a CALL/RETURN function.
<P>Why is it done like this then? Well, consider this example: <PRE> ...
JSR R0,FOO
.WORD A
.WORD B
MOV R1,C
...
FOO: MOV @(R0)+,R1
ADD @(R0)+,R1
RTS R0
</PRE><BR>
<P>This type of parameter passing is used extensively in the PDP-8 and
PDP-10), for example. Also, the FORTRAN runtime system on the PDP-11 do it
this way. (It is fairly easy to write a compiler who generates such a calling
sequence, and then have a library of functions which expect this calling
convention.) </P></DD></DL><PRE> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|0|0|0|0|0|0|0|0|0|1|d|d|d|d|d|d|
| Opcode |Destination|
</PRE>
<P>
<DL compact>
<DT>0 000 000 001 ddd ddd -- JMP <I>JuMP</I>
<DD>Loads the destination address into the PC, thus effecting an unconditional
jump. Note that a trap will occur on some systems if an odd address is
specified. On others, the destination is silently rounded down to the
next-lower even address (i.e., the right-most bit is ignored). </DD></DL><PRE> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
|0|0|0|0|0|0|0|0|0|0|0|0|0|i|i|i|
| | | | | | Op |
</PRE>
<P>
<DL compact>
<DD>0 000 000 000 000 000 -- HALT <I>Halts the machine</I>
<DD>Ceases I/O, and gives control to the console. Operator intervention is
required to continue or restart the system.
<P></P>
<DD>0 000 000 000 000 001 -- WAIT <I>WAIT for interrupt</I>
<DD>0 000 000 000 000 010 -- RTI <I>ReTurn from Interrupt</I>
<DD>0 000 000 000 000 100 -- BPT <I>BreakPoint Trap</I>
<DD>0 000 000 000 000 101 -- RESET <I>Initializes the system</I> </DD></DL>
<P>The following opcode ranges are all unused (using three bits per digit):
<P>
<DL compact>
<DD>00 00 07 .. 00 00 77
<DD>00 02 10 .. 00 02 27
<DD>00 70 00 .. 00 77 77
<DD>07 50 40 .. 07 67 77
<DD>10 64 00 .. 10 64 77
<DD>10 67 00 .. 10 77 77 </DD></DL>
<P>Other arithmetic and floating point instructions were added to the basic set
over the years, but those listed above form the core PDP-11 instruction set.
<P>There is a comparison of PDP-11 and 80x86 floating point formats available
at: <A
href="ftp://ftp.dbit.com/pub/pdp11/info/fpp.txt">ftp://ftp.dbit.com/pub/pdp11/info/fpp.txt</A>
<HR>
<A href="http://www.village.org/pdp11/faq.html">Table of Contents</A>
</BODY></HTML>

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This repository contains the documentations for various CPUs. It may contain data sheets, programmer's references, quick cards, and the like.
| Subfolders | Description |
| ---------- | ----------- |
| 8085 | Intel 8085 |
| Alpha | Compaq Alpha |
| ARM | |
| AVR | |
| Burroughs | |
| CRIS | |
| DSP56000 | |
| ESA390 | |
| F18A | |
| H8 | |
| HD6301 | |
| IA-64 | Intel IA-64 |
| KDF9 | |
| M68000 | Motorola 680x0 CPU family |
| MARC4 | |
| MC6809 | Motorola 6809 and Hitachi 6309 |
| MCS-51 | |
| MCS6500 | |
| MIPS | |
| MN103 | |
| MSP430 | |
| NS32000 | National Semiconductor 32000 family |
| OpenRISC | |
| PDP-1 | DEC PDP-1 |
| PDP-10 | DEC PDP-10 |
| PDP-8 | DEC PDP-8 |
| PIC | |
| PowerPC | IBM PowerPC |
| PSC1000 | |
| RISC-V | |
| RTX2000 | |
| SPARC | |
| SuperH | Hitachi SuperH |
| x86-64 | |
| Xtensa | |
| Z80 | Zilog Z80 |
| zArchitecture | |

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This subfolder contains the documents and other stuff for DEC VAX family.
[Main Wikipedia article on DEC VAX](https://en.wikipedia.org/wiki/VAX)
| Files | Description | Source |
| ----- | ----------- | ------ |
| VAX_archHbkVol1_1977.pdf | VAX Architecture Handbook | URL not determined |

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Full eZ80 Opcode List
=====================
File: http://mdfs.net/Docs.Comp.eZ80.OpList - Update: 0.11
Author: J.G.Harston - Date: 15-04-1998
nn nn DD nn CB nn FD CB dd nn ED nn
-----------------------------------------------------------------------------------
00 NOP - RLC B - IN0 B,(&00)
01 LD BC,&0000 - RLC C - OUT0 (&00),B
02 LD (BC),A - RLC D - LEA BC,IX+d
03 INC BC - RLC E - LEA BC,IY+d
04 INC B - RLC H - TST A,B
05 DEC B - RLC L - -
06 LD B,&00 - RLC (HL) RLC (IY+d) -
07 RLCA LD BC,(IX+d) RLC A - LD BC,(HL)
08 EX AF,AF' - RRC B - IN0 C,(&00)
09 ADD HL,BC ADD IX,BC RRC C - OUT0 (&00),C
0A LD A,(BC) - RRC D - -
0B DEC BC - RRC E - -
0C INC C - RRC H - TST A,C
0D DEC C - RRC L - -
0E LD C,&00 - RRC (HL) RRC (IY+d) -
0F RRCA LD (IX+d),BC RRC A - LD (HL),BC
10 DJNZ dist - RL B - IN0 D,(&00)
11 LD DE,&0000 - RL C - OUT0 (&00),D
12 LD (DE),A - RL D - LEA DE,IX+d
13 INC DE - RL E - LEA DE,IY+d
14 INC D - RL H - TST A,D
15 DEC D - RL L - -
16 LD D,&00 - RL (HL) RL (IY+d) -
17 RLA LD DE,(IX+d) RL A - LD DE,(HL)
18 JR dist - RR B - IN0 E,(&00)
19 ADD HL,DE ADD IX,DE RR C - OUT0 (&00),E
1A LD A,(DE) - RR D - -
1B DEC DE - RR E - -
1C INC E - RR H - TST A,E
1D DEC E - RR L - -
1E LD E,&00 - RR (HL) RR (IY+d) -
1F RRA LD (IX+d),DE RR A - LD (HL),DE
20 JR NZ,dist - SLA B - IN0 H,(&00)
21 LD HL,&0000 LD IX,&0000 SLA C - OUT0 (&00),H
22 LD (&0000),HL LD (&0000),IX SLA D - LEA HL,IX+d
23 INC HL INC IX SLA E - LEA HL,IY+d
24 INC H INC IXH SLA H - TST A,H
25 DEC H DEC IXH SLA L - -
26 LD H,&00 LD IXH,&00 SLA (HL) SLA (IY+d) -
27 DAA LD HL,(IX+d) SLA A - LD HL,(HL)
28 JR Z,dist - SRA B - IN0 L,(&00)
29 ADD HL,HL ADD IX,IX SRA C - OUT0 (&00),L
2A LD HL,(&0000) LD IX,(&0000) SRA D - -
2B DEC HL DEC IX SRA E - -
2C INC L INC IXL SRA H - TST A,L
2D DEC L DEC IXL SRA L - -
2E LD L,&00 LD IXL,&00 SRA (HL) SRA (IY+d) -
2F CPL LD (IX+d),HL SRA A - LD (HL),HL
30 JR NC,dist - - - -
31 LD SP,&0000 LD IY,(IX+d) - - -
32 LD (&0000),A - - - LEA IX,IX+d
33 INC SP - - - LEA IY,IY+d
34 INC (HL) INC (IX+d) - - TST A,(HL)
35 DEC (HL) DEC (IX+d) - - -
36 LD (HL),&00 LD (IX+d),&00 - - LD IY,(HL)
37 SCF LD IX,(IX+d) - - LD IX,(HL)
38 JR C,dist - SRL B - IN0 A,(&00)
39 ADD HL,SP ADD IX,SP SRL C - OUT0 (&00),A
3A LD A,(&0000) - SRL D - -
3B DEC SP - SRL E - -
3C INC A - SRL H - TST A,A
3D DEC A - SRL L - -
3E LD A,&00 LD (IX+d),IY SRL (HL) SRL (IY+d) LD (HL),IY
3F CCF LD (IX+d),IX SRL A - LD (HL),IX
40 LD B,B - BIT 0,B - IN B,(BC)
41 LD B,C - BIT 0,C - OUT (BC),B
42 LD B,D - BIT 0,D - SBC HL,BC
43 LD B,E - BIT 0,E - LD (&0000),BC
44 LD B,H LD B,IXH BIT 0,H - NEG
45 LD B,L LD B,IXL BIT 0,L - RETN
46 LD B,(HL) LD B,(IX+d) BIT 0,(HL) BIT 0,(IY+d) IM 0
47 LD B,A - BIT 0,A - LD I,A
48 LD C,B - BIT 1,B - IN C,(BC)
49 LD C,C - BIT 1,C - OUT (BC),C
4A LD C,D - BIT 1,D - ADC HL,BC
4B LD C,E - BIT 1,E - LD BC,(&0000)
4C LD C,H LD C,IXH BIT 1,H - MULT BC
4D LD C,L LD C,IXL BIT 1,L - RETI
4E LD C,(HL) LD C,(IX+d) BIT 1,(HL) BIT 1,(IY+d) -
4F LD C,A - BIT 1,A - LD R,A
50 LD D,B - BIT 2,B - IN D,(BC)
51 LD D,C - BIT 2,C - OUT (BC),D
52 LD D,D - BIT 2,D - SBC HL,DE
53 LD D,E - BIT 2,E - LD (&0000),DE
54 LD D,H LD D,IXH BIT 2,H - LEA IX,IY+d
55 LD D,L LD D,IXL BIT 2,L - LEA IY,IX+d
56 LD D,(HL) LD D,(IX+d) BIT 2,(HL) BIT 2,(IY+d) IM 1
57 LD D,A - BIT 2,A - LD A,I
58 LD E,B - BIT 3,B - IN E,(BC)
59 LD E,C - BIT 3,C - OUT (BC),E
5A LD E,D - BIT 3,D - ADC HL,DE
5B LD E,E - BIT 3,E - LD DE,(&0000)
5C LD E,H LD E,IXH BIT 3,H - MULT DE
5D LD E,L LD E,IXL BIT 3,L - -
5E LD E,(HL) LD E,(IX+d) BIT 3,(HL) BIT 3,(IY+d) IM 2
5F LD E,A - BIT 3,A - LD A,R
60 LD H,B LD IXH,B BIT 4,B - IN H,(BC)
61 LD H,C LD IXH,C BIT 4,C - OUT (BC),H
62 LD H,D LD IXH,D BIT 4,D - SBC HL,HL
63 LD H,E LD IXH,E BIT 4,E - LD (&0000),HL
64 LD H,H LD IXH,IXH BIT 4,H - TST A,&00
65 LD H,L LD IXH,IXL BIT 4,L - PEA IX+d
66 LD H,(HL) LD H,(IX+d) BIT 4,(HL) BIT 4,(IY+d) PEA IY+d
67 LD H,A LD IXH,A BIT 4,A - RRD
68 LD L,B LD IXL,B BIT 5,B - IN L,(BC)
69 LD L,C LD IXL,C BIT 5,C - OUT (BC),L
6A LD L,D LD IXL,D BIT 5,D - ADC HL,HL
6B LD L,E LD IXL,E BIT 5,E - LD HL,(&0000)
6C LD L,H LD IXL,IXH BIT 5,H - MULT HL
6D LD L,L LD IXL,IXL BIT 5,L - LD MB,A
6E LD L,(HL) LD L,(IX+d) BIT 5,(HL) BIT 5,(IY+d) LD A,MB
6F LD L,A LD IXL,A BIT 5,A - RLD
70 LD (HL),B LD (IX+d),B BIT 6,B - -
71 LD (HL),C LD (IX+d),C BIT 6,C - -
72 LD (HL),D LD (IX+d),D BIT 6,D - SBC HL,SP
73 LD (HL),E LD (IX+d),E BIT 6,E - LD (&0000),SP
74 LD (HL),H LD (IX+d),H BIT 6,H - TSR (&00)
75 LD (HL),L LD (IX+d),L BIT 6,L - -
76 HALT - BIT 6,(HL) BIT 6,(IY+d) SLP
77 LD (HL),A LD (IX+d),A BIT 6,A - -
78 LD A,B - BIT 7,B - IN A,(BC)
79 LD A,C - BIT 7,C - OUT (BC),A
7A LD A,D - BIT 7,D - ADC HL,SP
7B LD A,E - BIT 7,E - LD SP,(&0000)
7C LD A,H LD A,IXH BIT 7,H - MULT SP
7D LD A,L LD A,IXL BIT 7,L - STMIX
7E LD A,(HL) LD A,(IX+d) BIT 7,(HL) BIT 7,(IY+d) RSMIX
7F LD A,A - BIT 7,A - -
80 ADD A,B - RES 0,B - -
81 ADD A,C - RES 0,C - -
82 ADD A,D - RES 0,D - INIM
83 ADD A,E - RES 0,E - OTIM
84 ADD A,H ADD A,IXH RES 0,H - INI2
85 ADD A,L ADD A,IXL RES 0,L - -
86 ADD A,(HL) ADD A,(IX+d) RES 0,(HL) RES 0,(IY+d) -
87 ADD A,A - RES 0,A - -
88 ADC A,B - RES 1,B - -
89 ADC A,C - RES 1,C - -
8A ADC A,D - RES 1,D - INDM
8B ADC A,E - RES 1,E - OTDM
8C ADC A,H ADC A,IXH RES 1,H - IND2
8D ADC A,L ADC A,IXL RES 1,L - -
8E ADC A,(HL) ADC A,(IX+d) RES 1,(HL) RES 1,(IY+d) -
8F ADC A,A - RES 1,A - -
90 SUB A,B - RES 2,B - -
91 SUB A,C - RES 2,C - -
92 SUB A,D - RES 2,D - INIMR
93 SUB A,E - RES 2,E - OTIMR
94 SUB A,H SUB A,IXH RES 2,H - INI2R
95 SUB A,L SUB A,IXL RES 2,L - -
96 SUB A,(HL) SUB A,(IX+d) RES 2,(HL) RES 2,(IY+d) -
97 SUB A,A - RES 2,A - -
98 SBC A,B - RES 3,B - -
99 SBC A,C - RES 3,C - -
9A SBC A,D - RES 3,D - INDMR
9B SBC A,E - RES 3,E - OTDMR
9C SBC A,H SBC A,IXH RES 3,H - IND2R
9D SBC A,L SBC A,IXL RES 3,L - -
9E SBC A,(HL) SBC A,(IX+d) RES 3,(HL) RES 3,(IY+d) -
9F SBC A,A - RES 3,A - -
A0 AND B - RES 4,B - LDI
A1 AND C - RES 4,C - CPI
A2 AND D - RES 4,D - INI
A3 AND E - RES 4,E - OTI
A4 AND H AND IXH RES 4,H - OTI2
A5 AND L AND IXL RES 4,L - -
A6 AND (HL) AND (IX+d) RES 4,(HL) RES 4,(IY+d) -
A7 AND A - RES 4,A - -
A8 XOR B - RES 5,B - LDD
A9 XOR C - RES 5,C - CPD
AA XOR D - RES 5,D - IND
AB XOR E - RES 5,E - OTD
AC XOR H XOR IXH RES 5,H - OTD2
AD XOR L XOR IXL RES 5,L - -
AE XOR (HL) XOR (IX+d) RES 5,(HL) RES 5,(IY+d) -
AF XOR A - RES 5,A - -
B0 OR B - RES 6,B - LDIR
B1 OR C - RES 6,C - CPIR
B2 OR D - RES 6,D - INIR
B3 OR E - RES 6,E - OTIR
B4 OR H OR IXH RES 6,H - ORI2R
B5 OR L OR IXL RES 6,L - -
B6 OR (HL) OR (IX+d) RES 6,(HL) RES 6,(IY+d) -
B7 OR A - RES 6,A - -
B8 CP B - RES 7,B - LDDR
B9 CP C - RES 7,C - CPDR
BA CP D - RES 7,D - INDR
BB CP E - RES 7,E - OTDR
BC CP H CP IXH RES 7,H - OTD2R
BD CP L CP IXL RES 7,L - -
BE CP (HL) CP (IX+d) RES 7,(HL) RES 7,(IY+d) -
BF CP A - RES 7,A - -
C0 RET NZ - SET 0,B - -
C1 POP BC - SET 0,C - -
C2 JP NZ,&0000 - SET 0,D - -
C3 JP &0000 - SET 0,E - -
C4 CALL NZ,&0000 - SET 0,H - -
C5 PUSH BC - SET 0,L - -
C6 ADD A,&00 - SET 0,(HL) SET 0,(IY+d) -
C7 RST &00 - SET 0,A - -
C8 RET Z - SET 1,B - -
C9 RET - SET 1,C - -
CA JP Z,&0000 - SET 1,D - -
CB **** CB **** **** CB **** SET 1,E - -
CC CALL Z,&0000 - SET 1,H - -
CD CALL &0000 - SET 1,L - -
CE ADC A,&00 - SET 1,(HL) SET 1,(IY+d) -
CF RST &08 - SET 1,A - -
D0 RET NC - SET 2,B - -
D1 POP DE - SET 2,C - -
D2 JP NC,&0000 - SET 2,D - -
D3 OUT (&00),A - SET 2,E - -
D4 CALL NC,&0000 - SET 2,H - -
D5 PUSH DE - SET 2,L - -
D6 SUB A,&00 - SET 2,(HL) SET 2,(IY+d) -
D7 RST &10 - SET 2,A - -
D8 RET C - SET 3,B - -
D9 EXX - SET 3,C - -
DA JP C,&0000 - SET 3,D - -
DB IN A,(&00) - SET 3,E - -
DC CALL C,&0000 - SET 3,H - -
DD **** DD **** - SET 3,L - -
DE SBC A,&00 - SET 3,(HL) SET 3,(IY+d) -
DF RST &18 - SET 3,A - -
E0 RET PO - SET 4,B - -
E1 POP HL POP IX SET 4,C - -
E2 JP PO,&0000 - SET 4,D - -
E3 EX (SP),HL EX (SP),IX SET 4,E - -
E4 CALL PO,&0000 - SET 4,H - -
E5 PUSH HL PUSH IX SET 4,L - -
E6 AND &00 - SET 4,(HL) SET 4,(IY+d) -
E7 RST &20 - SET 4,A - -
E8 RET PE - SET 5,B - -
E9 JP (HL) JP (IX) SET 5,C - -
EA JP PE,&0000 - SET 5,D - -
EB EX DE,HL - SET 5,E - -
EC CALL PE,&0000 - SET 5,H - -
ED **** ED **** - SET 5,L - -
EE XOR &00 - SET 5,(HL) SET 5,(IY+d) -
EF RST &28 - SET 5,A - -
F0 RET P - SET 6,B - -
F1 POP AF - SET 6,C - -
F2 JP P,&0000 - SET 6,D - -
F3 DI - SET 6,E - -
F4 CALL P,&0000 - SET 6,H - -
F5 PUSH AF - SET 6,L - -
F6 OR &00 - SET 6,(HL) SET 6,(IY+d) -
F7 RST &30 - SET 6,A - -
F8 RET M - SET 7,B - -
F9 LD SP,HL LD SP,IX SET 7,C - -
FA JP M,&0000 - SET 7,D - -
FB EI - SET 7,E - -
FC CALL M,&0000 - SET 7,H - -
FD **** FD **** - SET 7,L - -
FE CP &00 - SET 7,(HL) SET 7,(IY+d) -
FF RST &38 - SET 7,A - -
Notes on index registers
------------------------
Where DD and IX are mentioned, FD and IY may be substituted and vis versa.
If a DD or FD opcode prefixes an nonexistant instruction, then the DD or
FD opcode acts as a NOP and the base instruction is executed. For example,
DD FF does a RST &38.
Notes on Indexed Shift/Bit Operations
-------------------------------------
A shift or bit operation on an indexed byte in memory is done by prefixing a
CB opcode refering to (HL) with DD or FD to specify (IX+n) or (IY+n). If
the CB opcode does not refer to (HL), then the CB prefix is executed as a
NOP and the following code executed.
Notes on ED opcodes
-------------------
Opcodes 00 to 3F and C0 to FF (other than the block instructions) just
increment the R register by 2.
References
----------

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