diff --git a/MCS6500/NMOS-CMOS 6502 differences.htm b/MCS6500/NMOS-CMOS 6502 differences.htm
new file mode 100644
index 0000000..365c667
--- /dev/null
+++ b/MCS6500/NMOS-CMOS 6502 differences.htm
@@ -0,0 +1,588 @@
+
+
+
+ NMOS-CMOS 6502 differences
+
+
+
+
+home |
+the links mine |
+6502 primer |
+large math look-up tables |
+65c02 assembly structure macros |
+simple multitask |
+6502 interrupts |
+zero-overhead Forth interrupts |
+RS-232 primer |
+assembly relevant today |
+CMOS-NMOS 6502 difs |
+6502 stacks treatise |
+workbench computers |
+self-modifying code |
+65816 misunderstandings
+
+
+
+
Differences between NMOS 6502 and CMOS 65c02
+
+
On this page:
+
+
+
On certain forums, and in a recent web search, I have found that
+some 6502 enthusiasts are apparently still unaware of the CMOS 6502
+(65c02) which was out in the early 1980's and of the benefits it offers over
+the original NMOS 6502. On one forum, someone said something about the BRA (Branch Relative Always) instruction,
+and another said, "The 6502 doesn't have a BRA instruction, but
+ I think I know what you mean," thinking the first one
+was confusing it with a different processor. I've seen
+enthusiasts' web pages saying the 6502 was offered in 1MHz and 2MHz
+versions, the writers
+being unaware that all the them being made since the mid-1990's are
+guaranteed to meet the timing specifications at 14MHz or better, and
+that the
+fastest ones are put at the heart of custom ICs and are running over
+200MHz.
+
+
+
+
Hardware differences
+
+
+ - CMOS allows much higher speeds. All the 65c02's being made
+today are guaranteed to meet specs at at least 14MHz. All WDC ones
+ are
+ tested at 20MHz. 6502.org forum member "plasmo" got both a
+W65C02S and a W65C816S to run at 36MHz, 40MHz at 5.3V (see
+ here). Also, forum member "Windfall" got both
+ running at 24MHz at 3.3V, three times the speed guaranteed for that voltage by the data sheet! (See
+ here.)
+
+
- CMOS can run at lower voltages. The WDC W65C02S is spec'ed from 1.71V to 5.25V.
+
+
- CMOS requires less power, and if all loads are CMOS
+also, power is proportional to frequency, dropping to essentially zero
+when the clock is
+ stopped.
+
+
- CMOS allows the clock to be stretched or stopped
+indefinitely without losing data. WDC's allows stopping the clock
+in either
+ phase. Other brands of 65c02 could only stop when Φ2 was
+high. NMOS was not guaranteed to run reliably below 50 or 100kHz
+ depending on brand.
+
+
- CMOS allows a crystal to be hung directly on Φ0 & Φ1
+ for oscillation, or an RC hung directly on these plus Φ2, eliminating
+the
+ need for an external oscillator for some applications. (See
+ the
+ clock-generation page
+ of the 6502 primer on this site.) NMOS
+ always needed the external oscillator. (Most recently
+however, WDC has said they no longer test the timings of these three
+relative to
+ each other, and they prefer that you use an external oscillator,
+even though all the circuitry is still there, operational, for using it
+as an
+ onboard oscillator. In critical cases, a separate
+oscillator may still be preferable.)
+
+
- CMOS can pull all the way up to VDD. Output high voltage with light load may be only a few mV from VDD.
+
+
- CMOS offers better noise immunity.
+
+
- CMOS: Some manufacturers put weak pull-ups to VDD on IRQ,
+ NMI, RDY, RST,
+ SO, and on WDC's, BE (bus enable). (Since not all did, you will need to check the data
+ sheet before leaving them unconnected.)
+
+
- CMOS (WDC W65C02S and others' 65C102 and 65C112) has
+more signals, for a wider range of hardware applications: bus
+enable (BE, DIP pin 36,
+ PLCC pin 40, and PQFP pin 34), and memory lock (ML, DIP pin 5, PLCC pin 6, and PQFP pin 44), and
+ on the WDC part, vector pull (VP,
+ DIP pin 1, PLCC pin 2, and PQFP pin 40). Note that pin 1
+ of NMOS and most non-WDC CMOS µP's in the 40-pin DIP is ground
+(like pin 21); so if you want to make a board able to take all brands,
+it
+ would be good to have pin 1's function jumper-selectable.
+
+
- CMOS is available in 44-pin PLCC and PQFP, not just
+40-pin DIP. At the time of this writing (July 2015), the PQFP is
+only available from
+ WDC, not their distributors. The PQFP definitely saves a
+lot of board space.
+
+
- CMOS has stronger bus-drive capability, far stronger
+than the datasheets let on. I have done some brief tests on WDC's
+W65C816S's pin
+ drivers which I suspect are the same ones used they used on the
+W65C02S. Their behavior was pretty much symmetrical, able to pull up
+ just as hard as they can pull down, unlike TTL which
+cannot pull up as hard as down. If you had to boil my test results
+ down to
+ approximations and treat the circuits as just a resistance, the
+data pin drivers acted very roughly like a SPDT switch with 50Ω in
+series
+ with the common terminal (ie, the output); and the address bus
+pins, as a SPDT switch with 60Ω in series. The time constant of
+ 60Ω times the capacitive load of 10 CMOS loads is around 3ns,
+which is less added delay than you'll get from a bus transceiver IC.
+
+ In a separate test on WDC's W65C22S VIA (not the W65C22N) I/O pins years earlier, I found they were each able to pull to
+ within 0.8V of either rail with a 220-ohm resistor to the opposite rail, meaning a 19mA load, even pulling up,
+ and give 50mA
+ into a dead short. Rockwell's R65C22 could pull down with
+100mA into a dead short, but could not pull up as hard, not being
+symmetrical
+ like WDC's.
+
+
- WDC's CMOS parts, with the exception of the 65c22N and 65c51N,
+ have CMOS input levels, and feeding these inputs with 74LS logic
+ (which there's no reason to use anyway) is not guaranteed to
+work, since 74LS cannot pull up nearly as high as CMOS outputs can.
+
+
- According to the NMOS data sheets (we wonder if this may
+ be an error in them), the RDY input timing may vary between
+manufacturers regarding
+ which Φ2 edge it is referenced to. Some reference it to
+Φ2's rising edge, and others to its falling
+ edge. Rockwell even puts it after the rising edge which definitely looks like a mistake. All the CMOS data sheets give it as
+ a setup time before the fall of Φ2.
+
+
- Related, but regarding the WDC's VIA, the W65C22S (but not the W65C22N) commonly used with the 65C02:
+
- Its I/O pins, in the input mode, are true CMOS
+inputs. The heavy LS-type load presented by other VIAs' (even CMOS
+ ones') I/O pins
+ in input mode was a problem for some applications.
+
+
- It has bus-holding devices on the I/O pins which
+ keep the input at the last-driven logic level. If you drive it
+high or low, then
+ disconnect the drive, it will hold itself at that
+level. There is no problem with leaving unused pins unconnected
+like there is
+ with many other CMOS inputs.
+
+
- It has a totem-pole IRQ output rather than the open-drain output that others
+ have. This is addressed in the interrupts primer. It
+ may seem like an undesirable feature since you can no longer wire-OR the IRQ pins together
+ but must use an AND gate instead; but the IRQ output was made this way so the rise time
+ of the IRQ
+ input to the µP would not be limited by the bus capacitance and the
+ pull-up resistor causing it to float up too slowly for
+some situations when operating at maximum clock speeds (up to 25MHz).
+
+
+
+
+
+
Software differences
+
+
+ - CMOS has more instructions and addressing modes.
+
+
CMOS 65c02 new instructions that were not on the NMOS 6502 at all:
+
+
+
+
instruction op code
+& addr mode (in hex) description
+
+BRA rel 80 Branch Relative Always (unconditionally), range -128 to +127.
+
+PHX DA PusH X. ‾⌉
+PLX FA PulL X. | No need to go through A for these anymore.
+PHY 5A PusH Y. |
+PLY 7A PulL Y. _⌋
+
+STZ addr 9C ‾⌉
+STZ addr,X 9E | STore a Zero, regardless of what's in A, X, or Y.
+STZ ZP 64 | Processor registers are not affected by STZ.
+STZ ZP,X 74 _⌋
+
+TRB addr 1C ‾⌉ Test & Reset memory Bits with A.
+TRB ZP 14 _⌋
+
+TSB addr 0C ‾⌉ Test & Set memory Bits with A.
+TSB ZP 04 _⌋
+
+BBR ZP 0F-7F [1] Branch if specified Bit is Reset. ‾⌉ These are most useful
+BBS ZP 8F-FF [1] Branch if specified Bit is Set. | when I/O is in ZP. They
+RMB ZP 07-77 [1] Reset specified Memory Bit. | are on WDC & Rockwell but
+SMB ZP 87-F7 [1] Set specified Memory Bit. _⌋ not GTE/CMD or Synertek.
+
+STP DB SToP the processor until the next RST. ‾⌉
+ Power-supply current drops to nearly zero. | These two are
+ | on WDC only.
+WAI CB WAIt. It's like STP, but any interrupt |
+ will make it resume execution. Especially |
+ useful for superfast interrupt response, |
+ with zero latency. See interrupts primer. _⌋
+
+
+Note: [1] Only the most-significant digit of the op code changes; so for example BBR's
+op codes are 0F, 1F, 2F, 3F, 4F, 5F, 6F, and 7F, for BBR0 to BBR7. The bit number is
+specified in the op code rather than the operand. These operate in ZP only. Rockwell
+added these first, for their microcontrollers that had I/O in ZP. WDC added them in
+the early 1990's. The Aug '92 data sheet shows the W65C02S available without them, and
+the W65C02SB with them, but said eventually they would all have them, and be labeled
+W65C02S, without the B. By the July '96 data sheet, these instructions were standard
+in all of them.
+
+
+
+CMOS 65c02 instructions' addressing modes that were not on the NMOS 6502:
+instruction op code
+& addr mode (in hex) description
+
+ADC (addr) 72 ADC absolute indirect
+AND (addr) 32 AND absolute indirect
+BIT addr,X 3C BIT absolute indexed
+BIT ZP,X 34 BIT zero-page indexed
+BIT # 89 BIT immediate
+CMP (addr) D2 CMP absolute indirect
+DEC A 3A DECrement accumulator (alternate mnemonic: DEA)
+INC A 1A INCrement accumulator (alternate mnemonic: INA)
+EOR (addr) 52 EOR absolute indirect
+JMP (addr,X) 7C JMP absolute indexed indirect
+LDA (addr) B2 LDA absolute indirect
+ORA (addr) 12 ORA absolute indirect
+SBC (addr) F2 SBC absolute indirect
+STA (addr) 92 STA absolute indirect
+
+
+Appetite whetter: the 65816 adds even more instructions and
+addressing modes, filling out the table, and is able (but not required)
+to handle
+16 bits of data at a time, as well as 24-bit addresses, and has a 16-bit
+ stack pointer and more stack-addressing modes, relocatable zero page
+(so for
+example each task can have its own), and other attractions. It is
+actually easier to program than the '02 is if you're constantly
+handling 16-bit data, and is much better suited for relocatable code,
+multitasking, etc.. If it seems scary, keep in mind that all the
+new '816
+features can be used or ignored at one's leisure, and picked up little
+by little as you're ready. You can start out by initially using it
+ just
+like a 6502.
+
+
+
- On the NMOS 6502, the "illegal" op codes (see
+ this page for more explanation), performed strange operations, undocumented by
+ manufacturers, and were popular, and were used in the GEOS
+ GUI for the Commodore 64, to meet the speed and memory
+requirements to make GEOS a viable software product on that limited
+machine. The
+ CMOS 6502 does not have those, but its new instructions and
+addressing modes are more useful anyway. CMOS still leaves some op
+ codes unused,
+ but they do not crash the µP like some of the illegal op codes do
+ on NMOS.
+
+
- On the CMOS 65c02, illegal op codes
+ initially act as NOPs, but can be useful for single-cycle time delays, and more interestingly, for effectively
+ extending the processor's instruction set; for example, Jeff Laughton's
+ fast (1-cycle) 65c02 I/O methods using the illegal op codes
+ in the _3 and _B columns, his KimKlone 65c02
+ w/ pointer-arithmetic-friendly extended address space and 9-cycle ITC Forth NEXT instruction, and the memory-mapping ops
+ of the Hudson 65c02-based processor used in the
+ TurboGrafx-16 Entertainment SuperSystem. In
+ this respect, these could be considered to be combination hardware/software differences.
+
+
This table shows the number of bytes and cycles taken by the CMOS instructions:
+
+
+
+
+
+
+
+
+
+
+ | Function |
+ NMOS 6502 |
+ W65C02S |
+
+
+
+
+ | Execution of Invalid OpCodes. |
+ Some terminate only by reset.
Results are undefined. |
+ All are NOP's (reserved for future use). |
+
+
+ | OpCode |
+ Bytes |
+ Cycle |
+
+
+ | 02,22,42,62,82,C2,E2 |
+ 2 |
+ 2 |
+
+
+ | X3,0B-BB,EB,FB |
+ 1 |
+ 1 |
+
+
+ | 44 |
+ 2 |
+ 3 |
+
+
+ | 54,D4,F4 |
+ 2 |
+ 4 |
+
+
+ | 5C |
+ 3 |
+ 8 |
+
+
+ | DC,FC |
+ 3 |
+ 4 |
+
+
+
+
+ It's from the forum topic Introducing Tali Forth for the 65c02
+ (ALPHA)". Note the software ability to skip over two bytes. You can do for example:
+
+ .DB $DC ; This is the illegal op code of a 3-byte, 4-cycle NOP.
+branch_dest: LDA #71 ; Its operand will be this 2-byte, 2-cycle instruction.
+ <continue>
+
+
+ If you branch or jump to branch_dest, the LDA #71 will be executed; but if you
+ arrive there without branching, ie, from directly above it, the LDA will get skipped, and there will be no effect
+ on status bits. Actually, the LDA #71 will
+get loaded as a two-byte operand for the illegal $DC
+ instruction, and the address that operand points to will get read
+ and the data discarded, like an absolute load-and-discard instruction;
+so
+ you might need to be careful that you don't read an I/O register
+where the I/O IC's status would be changed by doing so (like the
+situation
+ with BIT addr). The danger of doing it inadvertently will be very low.
+
+
+
- CMOS corrects all the bugs and quirks of the NMOS:
+
+ - JMP(xxFF): NMOS did not increment the page when reading the second byte, so the jump was wrong.
+
- N, V, and Z flags were incorrect after decimal operation (but C was ok). (CMOS adds one cycle to fix them.)
+
- A BRK instruction that was being fetched when an interrupt hit was ignored on NMOS. (CMOS executes
+ the BRK, then takes the interrupt.)
+
- D was not cleared on RST, IRQ, or NMI. (CMOS does clear D in these situations.)
+
- RDY being negated (pulled low, as RDY is positive
+logic) during write cycle had no effect. (CMOS gives the expected
+wait state(s).)
+
- Indexing across a page boundary caused an extra read
+ of an invalid address, which could cause trouble in some
+hardware. (CMOS does an
+ extra read of the last instruction byte instead.)
+
- RMW instructions at effective address did one read
+and two writes, which could cause trouble if it's I/O. (CMOS does
+two reads and one write.)
+
+
+
+
+
+
+
+
+
Availability
+
+None of the NMOS parts have been made in many years (decades?) but
+NOS (new old stock) can sometimes be found, and some distributors like
+Jameco have
+"pulls," ie, ones that have been pulled out of circuit boards, mostly
+used. Some of the CMOS parts are also discontinued, the ones that
+come to
+mind being the GTE/CMD 65C03, '04, '05, '06, 07, '12, '13, '14, '15,
+'102, '103, '104, '105, '106, '107, '112, '115, '150, and '151, the
+Rockwell '19,
+and the WDC 65C802. WDC plans to continue making the CMOS 65C02, '816, '134 µC, '265 µC, and I/O ICs indefinitely, at least in
+DIP and PLCC and some also in PQFP, and there are many distributors selling them. We try to keep the forum sticky topic
+"65xx parts sources" up to date, so please refer there.
+
+
+
+
+
For further reading
+
+65c02 advantages (forum topic)
+A taken branch delays interrupt handling by one instruction (forum
+ topic) There seems to be a difference between NMOS and CMOS in this area as well.
+A 65C02 bug?
+ (it was a bug in the documentation, not the
+ processor) (forum topic) See Jeff's post on cycle
+timing differences between NMOS & CMOS in R-M-W instructions.
+Least Obvious Incompatibility (forum topic)
+65c02 data sheet (.pdf) from WDC
+65816 data sheet (.pdf) from WDC
+"Programming the 65816-Including the 6502, 65C02 and 65802,"
+the outstanding programming manual by David Eyes and Ron Liechty. By far the best.
+I came across this CPU World page in Feb
+2018 giving more details on the variants like 6504, 6505, 6506, 6507, etc. (not so much the NMOS-CMOS differences).
+
+
links from my links page, under "65-family processors", at http://wilsonminesco.com/links.html#65fam :
+6502 origins
+
+ 65816 origins, 6516, 65032, 65832
+65CE02 improvements over the 65c02
+6516 (Synertek) 16-bit pseudo-6502 for Atari 400/800 computers, never made it to market
+65020 double-wide 6502 proposal
+HuC6280,
+ a PC Engine using a special version of the 65c02
+(with all the modern CMOS instructions minus STP and WAI), with a memory
+ management unit (MMU). Of special interest are the instructions
+directly involved with memory mapping and moving, and a T flag, which
+when set (using SET), causes accumulator
+instructions to operate on the ZP address pointed to by X instead,
+without affecting A! It makes it like having 257 accumulators.
+6502EX (6502 extended to 32 bits)
+65Org32 developments of ideas for an all-32-bit 65816 extension (forum topic)
+
+
+
+
If you know of additional differences I should add, or see errors, please email me.
+
+
+last updated Oct 12, 2021 Garth
+Wilson email wilsonminesBdslextremeBcom (replacing the B's
+with @ and .)
+
+
+
+
\ No newline at end of file
diff --git a/MCS6500/README.md b/MCS6500/README.md
index c92abe4..48e3439 100644
--- a/MCS6500/README.md
+++ b/MCS6500/README.md
@@ -1,7 +1,7 @@
This subfolder contains the documents and other stuff for 6502 and 65816 CPU family.
-[Main Wikipedia article on this family](https://en.wikipedia.org/wiki/MOS_Technology_6502)
-[Main Wikipedia article on this family](https://en.wikipedia.org/wiki/WDC_65816/65802)
+[MOS 6502 wikipedia article](https://en.wikipedia.org/wiki/MOS_Technology_6502)
+[WDC 65816/65802 wikipedia article](https://en.wikipedia.org/wiki/WDC_65816/65802)
| Files | Description | Source |
| ----- | ----------- | ------ |
@@ -12,5 +12,8 @@ This subfolder contains the documents and other stuff for 6502 and 65816 CPU fam
| mcs6500_family_programming_manual.pdf | | |
| mos_6510_mpu.pdf | | |
| w65c816s.pdf | WDC 65C816 data sheet | Believed to be taken from http://www.6502.org |
+| wdc_w65c816s_nov_09_2018.pdf | WDC 65C816S data sheet | https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf |
| wdc_65816_programming_manual.pdf | WDC 65C816 Programming Manual | Believed to be taken from http://www.6502.org |
-| wdc_w65c02s_oct_19_2010.pdf | WDC 65C02S data sheet | Believed to be taken from http://www.6502.org |
+| wdc_w65c02s_oct_19_2010.pdf | WDC 65C02S data sheet (Oct 19 2010) | Believed to be taken from http://www.6502.org |
+| wdc_w65c02s_feb_25_2020.pdf | WDC 65C02S data sheet (Feb 25 2020) | https://www.westerndesigncenter.com/wdc/documentation/w65c02s.pdf |
+| rockwell_r65c02_r65c102_r65c112 rev6 jun_1987.pdf | Rockwell R65C02/R65C102/R65C112 data sheet | http://archive.6502.org/datasheets/rockwell_r650x_r651x.pdf |
diff --git a/MCS6500/65c02.txt b/MCS6500/Rockwell 65c02.txt
similarity index 100%
rename from MCS6500/65c02.txt
rename to MCS6500/Rockwell 65c02.txt
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diff --git a/MCS6500/WDC 65c02.txt b/MCS6500/WDC 65c02.txt
new file mode 100644
index 0000000..fec590c
--- /dev/null
+++ b/MCS6500/WDC 65c02.txt
@@ -0,0 +1,253 @@
+----------------------------------------------------------------
+| |
+| |
+| Western Design Center |
+| |
+| 666 5555555 CCCC 000 22222 |
+| 6 5 C C 0 0 2 2 |
+| 6 5 C 0 0 0 2 |
+| 666666 555555 C 0 0 0 222 |
+| 6 6 5 C 0 0 0 2 |
+| 6 6 5 C C 0 0 2 |
+| 66666 555555 CCCC 000 2222222 |
+| |
+| 65C02 CMOS MICROPROCESSOR Instruction Set Summary |
+| |
+| |
+| _________ _________ |
+| _| \__/ |_ ____ |
+| VPB |_|1 40|_| RESB <-- |
+| _| |_ |
+| --> RDY |_|2 39|_| PHI2O --> |
+| _| |_ |
+| <-- PHI1O |_|3 38|_| SOB |
+| ____ _| |_ |
+| --> IRQB |_|4 37|_| PHI2 <-- |
+| _| |_ |
+| MLB |_|5 36|_| BE |
+| ____ _| |_ |
+| --> NMIB |_|6 35|_| NC |
+| _| |_ __ |
+| --> SYNC |_|7 34|_| RWB --> |
+| _| |_ |
+| VDD |_|8 33|_| D0 <--> |
+| _| |_ |
+| <-- A0 |_|9 32|_| D1 <--> |
+| _| |_ |
+| <-- A1 |_|10 65C02 31|_| D2 <--> |
+| _| |_ |
+| <-- A2 |_|11 30|_| D3 <--> |
+| _| |_ |
+| <-- A3 |_|12 29|_| D4 <--> |
+| _| |_ |
+| <-- A4 |_|13 28|_| D5 <--> |
+| _| |_ |
+| <-- A5 |_|14 27|_| D6 <--> |
+| _| |_ |
+| <-- A6 |_|15 26|_| D7 <--> |
+| _| |_ |
+| <-- A7 |_|16 25|_| A15 --> |
+| _| |_ |
+| <-- A8 |_|17 24|_| A14 --> |
+| _| |_ |
+| <-- A9 |_|18 23|_| A13 --> |
+| _| |_ |
+| <-- A10 |_|19 22|_| A12 --> |
+| _| |_ |
+| <-- A11 |_|20 21|_| VSS |
+| |______________________| |
+| |
+| |
+|Written by Wyatt Wong |
+| |
+|Modified from |
+| 65c02.txt by Jonathan Bowen |
+| |
+|Created 10 November 2021 |
+|Updated 10 November 2021 |
+|Issue 1.0 |
+----------------------------------------------------------------
+
+----------------------------------------------------------------
+| A0-A15 | Address Bus | Pins 9-20, 22-25 |
+| BE | Bus Enable | Pin 36 |
+| D0-D7 | Data Bus | Pins 26-33 |
+| IRQ | Interrupt Request | Pin 4 |
+| MLB | Memory Lock | Pin 5 |
+| NMIB | Non-Maskable Interrupt | Pin 6 |
+| NC | No Connect | Pin 35 |
+| PHI1O | Phase 1 Out | Pin 3 |
+| PHI2 | Phase 2 In | Pin 37 |
+| PHI2O | Phase 2 Out | Pin 39 |
+| RWB | Read/Write | Pin 34 |
+| RDY | Ready | Pin 2 |
+| RESB | Reset | Pin 40 |
+| SOB | Set Overflow | Pin 38 |
+| SYNC | SYNChronize with OpCode fetch | Pin 7 |
+| VDD | Ground | Pin 8 |
+| VSS | Power | Pin 21 |
+| VPB | Vector Pull | Pin 1 |
+----------------------------------------------------------------
+
+----------------------------------------------------------------
+|Mnem. |Op|NVBDIZC|A#ZBIRX@|~|Description |Notes |
+|------+--+-------+--------+-+---------------------+-----------|
+|ADC s|6D|**---**| XxX XX|4|Add with Carry |A=A+s+C %|
+|AND s|2D|*----*-| XxX XX|4|Logical AND |A=A&s %|
+|ASL d|0E|*----**| xx |6|Arith. Shift Left |d={C,d,0}<-|
+|ASL |0A|*----**|X |2|Arith. Shift Left |A={C,d,0}<-|
+|BBRb z|0F|-------| * X |5|Branch if Bit Reset |If s=0 |
+|BBSb z|8F|-------| * X |5|Branch if Bit Set |If s=1 |
+|BCC a|90|-------| X |2|Branch if Carry Clear|If C=0(4~)%|
+|BCS a|B0|-------| X |2|Branch if Carry Set |If C=1(4~)%|
+|BEQ a|F0|-------| X |2|Branch if Equal |If Z=1(4~)%|
+|BIT s|2C|**---*-| Xxx |4|Bit Test |A&s $|
+|BMI a|30|-------| X |2|Branch if Minus |If N=1(4~)%|
+|BNE a|D0|-------| X |2|Branch if Not Equal |If Z=0(4~)%|
+|BPL a|10|-------| X |2|Branch if Plus |If N=0(4~)%|
+|BRA a|80|-------| X |2|Branch Always |PC=a (4~)%|
+|BRK |00|--+-1--| X |7|Break(-[S]={PC+2,P}) |PC=[FFFEH] |
+|BVC a|50|-------| X |2|Branch if Overflw Clr|If V=0(4~)%|
+|BVS a|70|-------| X |2|Branch if Overflw Set|If V=1(4~)%|
+|CLC |18|------0| X |2|Clear Carry flag |C=0 |
+|CLD |D8|---0---| X |2|Clear Decimal mode |D=0 |
+|CLI |58|----0--| X |2|Clear Int. disable |I=0 |
+|CLV |B8|-0-----| X |2|Clear Overflow flag |V=0 |
+|CMP s|CD|*----**| XxX XX|4|Compare |A-s |
+|CPX s|EC|*----**| X** |4|Compare index reg. |X-s |
+|CPY s|CC|*----**| X** |4|Compare index reg. |Y-s |
+|DEC d|CE|*----*-| xx |6|Decrement |d=d-1 |
+|DEC |3A|*----*-|X |6|Decrement Acc. |A=A-1 |
+|DEX |CA|*----*-| X |2|Decrement index reg. |X=X-1 |
+|DEY |88|*----*-| X |2|Decrement index reg. |Y=Y-1 |
+|EOR s|4D|*----*-| XxX XX|4|Logical Exclusive OR |A=Axs %|
+|INC d|EE|*----*-| xx |6|Increment |d=d+1 |
+|INC |1A|*----*-|X |6|Increment Acc. |A=A+1 |
+|INX |E8|*----*-| X |2|Increment index reg. |X=X+1 |
+|INY |C8|*----*-| X |2|Increment index reg. |Y=Y+1 |
+|JMP s|4C|-------| * X|3|Jump |PC=s $|
+|JSR s|20|-------| * |6|Jump to Subroutine |-[S]=PC+2=s|
+|LDA s|AD|*----*-| XxX XX|4|Load Accumulator |A=s %|
+|LDX s|AE|*----*-| Xyy |4|Load index register |X=s $%|
+|LDY s|AC|*----*-| Xxx |4|Load index register |Y=s %|
+|LSR d|4E|0----**| xx |6|Logical Shift Right |d=->{0,d,C}|
+|LSR |4A|0----**|X |2|Logical Shift Right |A=->{0,A,C}|
+|NOP |EA|-------| X |2|No Operation | |
+|ORA s|0D|*----*-| XxX XX|4|Logical Inclusive OR |A=Avs |
+|PHA |48|-------| X |3|Push Accumulator |-[S]=A |
+|PHP |08|-------| X |3|Push status register |-[S]=P |
+|PHX |DA|-------| X |2|Push index register |-[S]=X |
+|PHY |5A|-------| X |2|Push index register |-[S]=Y |
+|PLA |68|*----*-| X |4|Pull Accumulator |A=[S]+ |
+|PLP |28|*******| X |4|Pull status register |P=[S]+ |
+|PLX |FA|*----*-| X |2|Pull index register |X=[S]+ |
+|PLY |7A|*----*-| X |2|Pull index register |Y=[S]+ |
+|RMBb d|07|-------| * |5|Reset Memory Bit |d=0 |
+|ROL d|2E|*----**| xx |6|Rotate Left |d={C,d}<- |
+|ROL |2A|*----**|X |2|Rotate Left Acc. |A={C,A}<- |
+|ROR d|6E|*----**| xx |6|Rotate Right |d=->{C,d} |
+|ROR |6A|*----**|X |2|Rotate Right Acc. |A=->{C,A} |
+|RTI |40|*******| X |6|Return from Interrupt|{PC,P}=[S]+|
+|RTS |60|-------| X |6|Return from Subr. |PC={[S]+}+1|
+|SBC s|ED|*----**| XxX XX|4|Subtract with Carry |A=A-s-C %|
+|SEC |38|------1| X |2|Set Carry flag |C=1 |
+|SED |F8|---1---| X |2|Set Decimal mode |D=1 |
+|SEI |78|----1--| X |2|Set Interrupt disable|I=1 |
+|SMBb d|87|-------| * |5|Set Memory Bit |d=1 |
+|STA d|8D|-------| xX XX|4|Store Accumulator |d=A |
+|STP |DB|-------| |3|Stop the Processor | |
+|STX d|8E|-------| y* |4|Store index register |d=X |
+|STY d|8C|-------| x* |4|Store index register |d=Y |
+|STZ d|9C|-------| xx |4|Store Zero |d=0 $|
+|TAX |AA|*----*-| X |2|Transfer Accumulator |X=A |
+|TAY |A8|*----*-| X |2|Transfer Accumulator |Y=A |
+|TRB d|1C|**---*-| ** |2|Test and Reset Bits |d=~A&d |
+|TSB d|0C|**---*-| ** |2|Test and Set Bits |d=Avd |
+|TSX |BA|*----*-| X |2|Transfer Stack ptr |X=S |
+|TXA |8A|*----*-| X |2|Transfer index reg. |A=X |
+|TXS |9A|-------| X |2|Transfer index reg. |S=X |
+|TYA |98|*----*-| X |2|Transfer index reg. |A=Y |
+|WAI |CB|-------| |3|Wait for Interrupt | |
+|------+--+-------+--------+-+---------------------------------|
+| |XX|NVBDIZC|A#ZBIRX@|X|Hexadecimal opcode/no. of cycles |
+----------------------------------------------------------------
+----------------------------------------------------------------
+|Mnemonic |NVBDIZC|A#ZBIRX@|Description |
+|---------+-------+--------+-----------------------------------|
+| P |-*01+ | |Unaff/affected/reset/set/stack set |
+| N |N | |Negative status (Bit 7) |
+| V | V | |Overflow status (Bit 6) |
+| B | B | |Break command indicator (Bit 4) |
+| D | D | |Decimal mode control (Bit 3) |
+| I | I | |Interrupt disable control (Bit 2) |
+| Z | Z | |Zero status (Bit 1) |
+| C | C| |Carry status (Bit 0) |
+|------------------+--------+----------------------------------|
+| |* |Only non-indexed mode valid |
+| |x |X and non-indexed mode valid |
+| |y |Y and non-indexed mode valid |
+| |X |All modes valid |
+|-----------------+--------+-----------------------------------|
+| | |Add XXH to opcode |+XXH| |
+| | |Subtract XXH from opcode |-XXH| |
+| | |Add X to number of cycles | |+X|
+| | |Subtract X from cycles | |-X|
+|-----------------+--------+---------------------------+----+--|
+| b | |Bit number (b=0-7) |+b0H| |
+| A |A |Accumulator | | |
+| #n | # |Immediate |-0CH|-2|
+| #n | # | ditto (opcode = XDH) | X9H| 2|
+| BIT #n | # | ditto (special case) | 89H| 2|
+| nn | B |Absolute |+00H|+0|
+| nn | * |Absolute (extended mode) |+00H|+0|
+| nn,X | x |Absolute indexed (X) |+10H|+0|
+| nn,Y | y |Absolute indexed (Y) |+0CH|+0|
+| LDX nn,Y | y | ditto (special case) | BEH| 4|
+| | I |Implicit | | |
+| a | R |Relative (PC=PC+1+offset) | |+2|
+| [nn,X] | x |Indexed indirect (X) |-0CH|+2|
+| [nn],Y | y |Indirect indexed (Y) |+04H|+1|
+| [nn] | @|Absolute indirect |+05H|+1|
+| JMP [nn] | @| ditto (special case) | 6CH| 5|
+|--------------------------+-----------------------------------|
+| A |Accumulator (8-bit) |
+| P |Processor status register (8-bit) |
+| PC |Program Counter (16-bit) |
+| S |Stack pointer (9-bit, MSB=1) |
+| X |Index register X (8-bit) |
+| Y |Index register Y (8-bit) |
+|--------------------------+-----------------------------------|
+| a |Relative address (-128 to +127) |
+| b |Bit number (0 to 7) |
+| d |Destination |
+| n |8-bit expression (0 to 255) |
+| nn |16-bit expression (0 to 65535) |
+| s |Source |
+| z |Zero page, relative address (n,a) |
+|--------------------------+-----------------------------------|
+| + - |Arithmetic addition/subtraction |
+| * / |Arithmetic multiplication/division |
+| & ~ |Logical AND/NOT |
+| v x |Logical inclusive/exclusive OR |
+| <- -> |Rotate left/right |
+| [ ] |Indirect addressing |
+| [ ]+ |Post-increment indirect addressing |
+| -[ ] |Pre-decrement indirect addressing |
+| { } |Combination of operands |
+| < > |Bit number |
+| $ |Special case for addressing mode |
+| % |~s=~s+1 if crossing page boundary |
+|--------------------------+-----------------------------------|
+|0000H to 00FFH |Page 0 (see zero page addressing) |
+|0100H to 01FFH |Page 1 (stack area, 01FFH = start) |
+|XX00H to XXFFH |Page n (where n=XXH) |
+|FFFAH to FFFBH |Non maskable interrupt vector(NMI) |
+|FFFCH to FFFDH |Reset (RES) vector |
+|FFFEH to FFFFH |Interrupt Request vector (IRQ) |
+|FFFEH to FFFFH |Break command vector (see BRK) |
+----------------------------------------------------------------
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