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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<html><head>
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<meta http-equiv="content-type" content="text/html; charset=windows-1252">
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<title>NMOS-CMOS 6502 differences</title>
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<meta name="KEYWORDS" content="NMOS CMOS 6502">
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</head>
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<body>
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<small>
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<a href="http://wilsonminesco.com/">home</a> |
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<a href="http://wilsonminesco.com/links.html">the links mine</a> |
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<a href="http://wilsonminesco.com/6502primer/">6502 primer</a> |
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<a href="http://wilsonminesco.com/16bitMathTables/">large math look-up tables</a> |
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<a href="http://wilsonminesco.com/StructureMacros/">65c02 assembly structure macros</a> |
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<a href="http://wilsonminesco.com/multitask/">simple multitask</a> |
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<a href="http://wilsonminesco.com/6502interrupts/">6502 interrupts</a> |
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<a href="http://wilsonminesco.com/0-overhead_Forth_interrupts/">zero-overhead Forth interrupts</a> |
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<a href="http://wilsonminesco.com/RS-232/RS-232primer.html">RS-232 primer</a> |
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<a href="http://wilsonminesco.com/AssyDefense/">assembly relevant today</a> |
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CMOS-NMOS 6502 difs |
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<a href="http://wilsonminesco.com/stacks/">6502 stacks treatise</a> |
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<a href="http://wilsonminesco.com/BenchCPU/">workbench computers</a> |
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<a href="http://wilsonminesco.com/SelfModCode/">self-modifying code</a> |
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<a href="http://wilsonminesco.com/816myths/">65816 misunderstandings</a>
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<br>
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</small>
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<br><br><br><center><strong><big><big>Differences between NMOS 6502 and CMOS 65c02</big></big></strong></center>
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<br><br>
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<br><big><strong>On this page:</strong></big>
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<ul><li><strong><a href="#hdwr">hardware differences</a></strong>
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</li><li><strong><a href="#sw">software differences</a></strong> (and a combination hardware/software difference)
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<!--<li><strong><a href="#sh">special software/hardware combination differences </a></strong>
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<li><strong><a href="#var">processor variations</a></strong>-->
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</li><li><strong><a href="#av">availability</a></strong>
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</li><li><strong><a href="#fur">for further reading</a></strong>
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</li></ul>
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<p><br>On certain forums, and in a recent web search, I have found that
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some 6502 enthusiasts are apparently still unaware of the CMOS 6502
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(<a href="https://en.wikipedia.org/wiki/WDC_65C02" target="_blank">65c02</a>) which was out in the early 1980's and of the benefits it offers over
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the original NMOS 6502. On one forum, someone said something about the<tt> BRA </tt>(Branch Relative Always) instruction,
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and another said, "The 6502 doesn't have a<tt> BRA </tt>instruction, but
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I think I know what you mean," thinking the first one
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was confusing it with a different processor. I've seen
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enthusiasts' web pages saying the 6502 was offered in 1MHz and 2MHz
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versions, the writers
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being unaware that all the them being made since the mid-1990's are
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guaranteed to meet the timing specifications at 14MHz or better, and
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that the
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fastest ones are put at the heart of custom ICs and are running over
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200MHz.
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<br>
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<br>
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<br>
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</p><h1><a name="hdwr"></a></h1><center><big><big><strong>Hardware differences</strong></big></big></center>
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<ul>
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<li>CMOS allows much higher speeds. All the 65c02's being made
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today are guaranteed to meet specs at at least 14MHz. All WDC ones
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are
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tested at 20MHz. 6502.org forum member "plasmo" got both a
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W65C02S and a W65C816S to run at 36MHz, 40MHz at 5.3V (see
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<a href="http://forum.6502.org/viewtopic.php?p=87657#p87657" target="_blank">here</a>). Also, forum member "Windfall" got both
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running at 24MHz at 3.3V, three times the speed guaranteed for that voltage by the data sheet! (See
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<a href="http://forum.6502.org/viewtopic.php?p=50721#p50721" target="_blank">here</a>.)<p>
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</p></li><li>CMOS can run at lower voltages. The WDC W65C02S is spec'ed from 1.71V to 5.25V.<p>
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</p></li><li>CMOS requires less power, and if all loads are CMOS
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also, power is proportional to frequency, dropping to essentially zero
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when the clock is
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stopped.<p>
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</p></li><li>CMOS allows the clock to be stretched or stopped
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indefinitely without losing data. WDC's allows stopping the clock
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in either
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phase. Other brands of 65c02 could only stop when Φ2 was
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high. NMOS was not guaranteed to run reliably below 50 or 100kHz
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depending on brand.<p>
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</p></li><li>CMOS allows a crystal to be hung directly on Φ0 & Φ1
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for oscillation, or an RC hung directly on these plus Φ2, eliminating
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the
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need for an external oscillator for some applications. (See
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the
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<a href="http://wilsonminesco.com/6502primer/ClkGen.html" target="_blank">clock-generation page</a>
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of the 6502 primer on this site.) NMOS
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always needed the external oscillator. (Most recently
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however, WDC has said they no longer test the timings of these three
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relative to
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each other, and they prefer that you use an external oscillator,
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even though all the circuitry is still there, operational, for using it
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as an
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onboard oscillator. In critical cases, a separate
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oscillator may still be preferable.)<p>
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</p></li><li>CMOS can pull all the way up to V<small>DD</small>. Output high voltage with light load may be only a few mV from V<small>DD</small>.<p>
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</p></li><li>CMOS offers better noise immunity.<p>
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</p></li><li>CMOS: Some manufacturers put weak pull-ups to V<small>DD</small> on <span style="text-decoration: overline;">IRQ</span>,
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<span style="text-decoration: overline;">NMI</span>, RDY, <span style="text-decoration: overline;">RST</span>,
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<span style="text-decoration: overline;">SO</span>, and on WDC's, BE (bus enable). (Since not all did, you will need to check the data
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sheet before leaving them unconnected.)<p>
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</p></li><li>CMOS (WDC W65C02S and others' 65C102 and 65C112) has
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more signals, for a wider range of hardware applications: bus
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enable (BE, DIP pin 36,
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PLCC pin 40, and PQFP pin 34), and memory lock (<span style="text-decoration: overline;">ML</span>, DIP pin 5, PLCC pin 6, and PQFP pin 44), and
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on the WDC part, vector pull (<span style="text-decoration: overline;">VP</span>,
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DIP pin 1, PLCC pin 2, and PQFP pin 40). Note that pin 1
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of NMOS and most non-WDC CMOS <20>P's in the 40-pin DIP is ground
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(like pin 21); so if you want to make a board able to take all brands,
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it
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would be good to have pin 1's function jumper-selectable.<p>
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</p></li><li>CMOS is available in 44-pin PLCC and PQFP, not just
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40-pin DIP. At the time of this writing (July 2015), the PQFP is
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only available from
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WDC, not their distributors. The PQFP definitely saves a
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lot of board space.<p>
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</p></li><li>CMOS has stronger bus-drive capability, far stronger
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than the datasheets let on. I have done some brief tests on WDC's
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W65C816S's pin
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drivers which I suspect are the same ones used they used on the
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W65C02S. Their behavior was pretty much symmetrical, able to pull <em>up</em>
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just as hard as they can pull <em>down</em>, unlike TTL which
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cannot pull up as hard as down. If you had to boil my test results
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down to
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approximations and treat the circuits as just a resistance, the
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data pin drivers acted very roughly like a SPDT switch with 50Ω in
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series
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with the common terminal (ie, the output); and the address bus
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pins, as a SPDT switch with 60Ω in series. The time constant of
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60Ω times the capacitive load of 10 CMOS loads is around 3ns,
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which is less added delay than you'll get from a bus transceiver IC.<p>
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In a separate test on WDC's W65C<u>2</u>2<u>S</u> VIA (not the W65C22<u>N</u>) I/O pins years earlier, I found they were each able to pull to
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within 0.8V of <em>either</em> rail with a 220-ohm resistor to the opposite rail, meaning a 19mA load, even pulling <em>up</em>,
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and give 50mA
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into a dead short. Rockwell's R65C22 could pull down with
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100mA into a dead short, but could not pull up as hard, not being
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symmetrical
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like WDC's.</p><p>
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</p></li><li>WDC's CMOS parts, with the exception of the 65c22<u>N</u> and 65c51<u>N</u>,
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have CMOS input levels, and feeding these inputs with 74LS logic
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(which there's no reason to use anyway) is not guaranteed to
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work, since 74LS cannot pull up nearly as high as CMOS outputs can.<p>
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</p></li><li>According to the NMOS data sheets (we wonder if this may
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be an error in them), the RDY input timing may vary between
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manufacturers regarding
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which Φ2 edge it is referenced to. Some reference it to
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Φ2's <em>rising</em> edge, and others to its <em>falling</em>
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edge. Rockwell even puts it <em>after</em> the rising edge which definitely looks like a mistake. All the CMOS data sheets give it as
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a setup time before the <em>fall</em> of Φ2.<p>
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</p></li><li>Related, but regarding the WDC's VIA, the W65C22<u>S</u> (but not the W65C22<u>N</u>) commonly used with the 65C02:<p>
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</p><ul><li>Its I/O pins, in the input mode, are true CMOS
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inputs. The heavy LS-type load presented by other VIAs' (even CMOS
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ones') I/O pins
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in input mode was a problem for some applications.<p>
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</p></li><li>It has bus-holding devices on the I/O pins which
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keep the input at the last-driven logic level. If you drive it
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high or low, then
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disconnect the drive, it will hold itself at that
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level. There is no problem with leaving unused pins unconnected
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like there is
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with many other CMOS inputs.<p>
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</p></li><li>It has a totem-pole <span style="text-decoration: overline;">IRQ</span> output rather than the open-drain output that others
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have. This is addressed in the <a href="http://wilsonminesco.com/6502interrupts/" target="_blank">interrupts primer</a>. It
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may seem like an undesirable feature since you can no longer wire-OR the <span style="text-decoration: overline;">IRQ</span> pins together
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but must use an AND gate instead; but the <span style="text-decoration: overline;">IRQ</span> output was made this way so the rise time
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of the <span style="text-decoration: overline;">IRQ</span>
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input to the <20>P would not be limited by the bus capacitance and the
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pull-up resistor causing it to float up too slowly for
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some situations when operating at maximum clock speeds (up to 25MHz).
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</li></ul>
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</li></ul>
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<br>
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<h1><a name="sw"></a></h1><center><big><big><strong>Software differences</strong></big></big></center>
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<ul>
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<li>CMOS has more instructions and addressing modes.
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<p><strong>CMOS 65c02 new instructions that were not on the NMOS 6502 at all:</strong><font color="#004800">
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<!--<p><table cellpadding="2" cellspacing="2" border="1">
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<tr><th>instruction<br>& addr mode</th><th>op code<br>(in hex)</th><th>description</th></tr>
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<tr><td>BRA rel</td><td>80</td><td>Branch Relative Always, range -128 to +127</td></tr>
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<tr><td>PHX</td><td>DA</td><td>PusH X. No need to go through A.</td></tr>
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<tr><td>PLX</td><td>FA</td><td>PulL X. No need to go through A.</td></tr>
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<tr><td>PHY</td><td>5A</td><td>PusH Y. No need to go through A.</td></tr>
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<tr><td>PLY</td><td>7A</td><td>PulL Y. No need to go through A.</td></tr>
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<tr><td>STZ <addr></td><td>9C</td><td>STore a Zero. No need to disturb A, X, or Y.</td></tr>
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<tr><td>STZ <addr>,X</td><td>9E</td><td>STore a Zero. No need to disturb A, X, or Y</td></tr>
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<tr><td>STZ <ZP></td><td>64</td><td>STore a Zero. No need to disturb A, X, or Y</td></tr>
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<tr><td>STZ <ZP>,X</td><td>74</td><td>STore a Zero. No need to disturb A, X, or Y</td></tr>
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<tr><td>TRB <addr></td><td>1C</td><td>Test & Reset memory Bits w/ A.</td></tr>
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<tr><td>TRB <ZP></td><td>14</td><td>Test & Reset memory Bits w/ A.</td></tr>
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<tr><td>TSB <addr></td><td>0C</td><td>Test & Reset memory Bits w/ A.</td></tr>
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<tr><td>TSB <ZP></td><td>04</td><td>Test & Reset memory Bits w/ A.</td></tr>
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<tr><td>BBR <ZP></td><td>0F-7F [1]</td><td>Branch if specified Bit is Reset.</td></tr>
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<tr><td>BBS <ZP></td><td>8F-FF [1]</td><td>Branch if specified Bit is Set.</td></tr>
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<tr><td>RMB <ZP></td><td>07-77 [1]</td><td>Reset specified Memory Bit.</td></tr>
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<tr><td>SMB <ZP></td><td>87-F7 [1]</td><td>Set specified Memory Bit.</td></tr>
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<tr><td>STP</td><td>DB</td><td>SToP the processor until the next RST.<br>Power-supply current drops to nearly zero.</td></tr>
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<tr><td>WAI</td><td>CB</td><td>WAIt. It's like STP, but any interrupt will make it resume execution.<br>Especially useful for superfast interrupt response.<br>See <a href="http://wilsonminesco.com/6502interrupts/index.html#2.3" target="_blank">interrupts primer</a>.</td></tr>
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</table>-->
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</font></p><pre><font color="#004800">instruction op code
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& addr mode (in hex) description
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BRA rel 80 Branch Relative Always (unconditionally), range -128 to +127.
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PHX DA PusH X. ‾⌉
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PLX FA PulL X. | No need to go through A for these anymore.
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PHY 5A PusH Y. |
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PLY 7A PulL Y. _⌋
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STZ addr 9C ‾⌉
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STZ addr,X 9E | STore a Zero, regardless of what's in A, X, or Y.
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STZ ZP 64 | Processor registers are not affected by STZ.
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STZ ZP,X 74 _⌋
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TRB addr 1C ‾⌉ Test & Reset memory Bits with A.
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TRB ZP 14 _⌋
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TSB addr 0C ‾⌉ Test & Set memory Bits with A.
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TSB ZP 04 _⌋
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BBR ZP 0F-7F [1] Branch if specified Bit is Reset. ‾⌉ These are most useful
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BBS ZP 8F-FF [1] Branch if specified Bit is Set. | when I/O is in ZP. They
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RMB ZP 07-77 [1] Reset specified Memory Bit. | are on WDC & Rockwell but
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SMB ZP 87-F7 [1] Set specified Memory Bit. _⌋ not GTE/CMD or Synertek.
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STP DB SToP the processor until the next RST. ‾⌉
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Power-supply current drops to nearly zero. | These two are
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| on WDC only.
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WAI CB WAIt. It's like STP, but any interrupt |
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will make it resume execution. Especially |
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useful for superfast interrupt response, |
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with zero latency. See <a href="http://wilsonminesco.com/6502interrupts/index.html#2.3" target="_blank">interrupts primer</a>. _⌋
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<u>Note</u>: [1] Only the most-significant digit of the op code changes; so for example BBR's
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op codes are 0F, 1F, 2F, 3F, 4F, 5F, 6F, and 7F, for BBR0 to BBR7. The bit number is
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specified in the op code rather than the operand. These operate in ZP only. Rockwell
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added these first, for their microcontrollers that had I/O in ZP. WDC added them in
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the early 1990's. The Aug '92 data sheet shows the W65C02S available without them, and
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the W65C02S<u>B</u> <em>with</em> them, but said eventually they would <em>all</em> have them, and be labeled
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W65C02S, without the B. By the July '96 data sheet, these instructions were standard
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in all of them.
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</font></pre>
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<strong>CMOS 65c02 instructions' addressing modes that were not on the NMOS 6502:</strong><font color="#004800">
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<pre>instruction op code
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& addr mode (in hex) description
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ADC (addr) 72 ADC absolute indirect
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AND (addr) 32 AND absolute indirect
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BIT addr,X 3C BIT absolute indexed
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BIT ZP,X 34 BIT zero-page indexed
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BIT # 89 BIT immediate
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CMP (addr) D2 CMP absolute indirect
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DEC A 3A DECrement accumulator (alternate mnemonic: DEA)
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INC A 1A INCrement accumulator (alternate mnemonic: INA)
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EOR (addr) 52 EOR absolute indirect
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JMP (addr,X) 7C JMP absolute indexed indirect
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LDA (addr) B2 LDA absolute indirect
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ORA (addr) 12 ORA absolute indirect
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SBC (addr) F2 SBC absolute indirect
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STA (addr) 92 STA absolute indirect
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</pre></font>
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Appetite whetter: the 65816 adds even more instructions and
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addressing modes, filling out the table, and is able (but not required)
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to handle
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16 bits of data at a time, as well as 24-bit addresses, and has a 16-bit
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stack pointer and more stack-addressing modes, relocatable zero page
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(so for
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example each task can have its own), and other attractions. It is
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actually <em>easier</em> to program than the '02 is if you're constantly
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handling 16-bit data, and is much better suited for relocatable code,
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multitasking, etc.. If it seems scary, keep in mind that all the
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new '816
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features can be used or ignored at one's leisure, and picked up little
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by little as you're ready. You can start out by initially using it
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just
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like a 6502.<p><br>
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</p></li><li>On the NMOS 6502, the <a href="http://www.oxyron.de/html/opcodes02.html" target="_blank">"illegal" op codes</a> (see
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<a href="http://www.pagetable.com/?p=39" target="_blank">this page</a> for more explanation), performed strange operations, undocumented by
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manufacturers, and were popular, and were used in the <a href="http://en.wikipedia.org/wiki/GEOS_%288-bit_operating_system%29" target="_blank">GEOS
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GUI</a> for the Commodore 64, to meet the speed and memory
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requirements to make GEOS a viable software product on that limited
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machine. The
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CMOS 6502 does not have those, but its new instructions and
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addressing modes are more useful anyway. CMOS still leaves some op
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codes unused,
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but they do not crash the <20>P like some of the illegal op codes do
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on NMOS.<p>
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</p></li><li>On the <a href="http://laughtonelectronics.com/Arcana/KimKlone/Kimklone_opcode_mapping.html" target="_blank">CMOS 65c02, illegal op codes</a>
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initially act as<tt> NOP</tt>s, but can be useful for single-cycle time delays, and more interestingly, for effectively
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extending the processor's instruction set; for example, Jeff Laughton's
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<a href="http://wilsonminesco.com/6502primer/potpourri.html#Jeff" target="_blank">fast (1-cycle) 65c02 I/O</a> methods using the illegal op codes
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in the _3 and _B columns, his <a href="http://laughtonelectronics.com/Arcana/KimKlone/Kimklone_short_summary.html" target="_blank">KimKlone 65c02</a>
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w/ pointer-arithmetic-friendly extended address space and 9-cycle ITC Forth<tt> NEXT </tt>instruction, and the memory-mapping ops
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of the <a href="https://en.wikipedia.org/wiki/Hudson_Soft_HuC6280" target="_blank">Hudson</a> 65c02-based processor used in the
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<a href="https://en.wikipedia.org/wiki/TurboGrafx-16" target="_blank">TurboGrafx-16 Entertainment SuperSystem</a>. <strong><font color="DarkRed">In
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this respect, these could be considered to be combination hardware/software differences</font>.</strong>
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<p>This table shows the number of bytes and cycles taken by the CMOS instructions:
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</p><p>
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<!-- <img src="NMOS-CMOS%206502%20differences_files/65c02_NOPs.gif"> -->
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<style>
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._65c02_NOPs, td, th {
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border: 1px solid black;
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padding: 5px;
|
||
}
|
||
|
||
._65c02_NOPs {
|
||
border-collapse: collapse;
|
||
}
|
||
|
||
.valign {
|
||
vertical-align: top;
|
||
}
|
||
|
||
.w65c02s {
|
||
text-align: center;
|
||
}
|
||
</style>
|
||
|
||
<table class="_65c02_NOPs">
|
||
<thead>
|
||
<tr>
|
||
<th>Function</th>
|
||
<th>NMOS 6502</th>
|
||
<th colspan="3">W65C02S</th>
|
||
</tr>
|
||
</thead>
|
||
<tbody>
|
||
<tr>
|
||
<td class="valign" rowspan="8">Execution of Invalid OpCodes.</td>
|
||
<td class="valign" rowspan="8">Some terminate only by reset.<br/>Results are undefined.</td>
|
||
<td colspan="3">All are NOP's (reserved for future use).</td>
|
||
</tr>
|
||
<tr>
|
||
<td class="w65c02s">OpCode</td>
|
||
<td class="w65c02s">Bytes</td>
|
||
<td class="w65c02s">Cycle</td>
|
||
</tr>
|
||
<tr>
|
||
<td>02,22,42,62,82,C2,E2</td>
|
||
<td>2</td>
|
||
<td>2</td>
|
||
</tr>
|
||
<tr>
|
||
<td>X3,0B-BB,EB,FB</td>
|
||
<td>1</td>
|
||
<td>1</td>
|
||
</tr>
|
||
<tr>
|
||
<td>44</td>
|
||
<td>2</td>
|
||
<td>3</td>
|
||
</tr>
|
||
<tr>
|
||
<td>54,D4,F4</td>
|
||
<td>2</td>
|
||
<td>4</td>
|
||
</tr>
|
||
<tr>
|
||
<td>5C</td>
|
||
<td>3</td>
|
||
<td>8</td>
|
||
</tr>
|
||
<tr>
|
||
<td>DC,FC</td>
|
||
<td>3</td>
|
||
<td>4</td>
|
||
</tr>
|
||
</tbody>
|
||
</table>
|
||
|
||
</p><p>It's from the forum topic <a href="http://forum.6502.org/viewtopic.php?p=36187#p36187" target="_blank">Introducing Tali Forth for the 65c02
|
||
(ALPHA)</a>". Note the software ability to skip over <em>two</em> bytes. You can do for example:
|
||
</p><pre>
|
||
.DB $DC ; This is the illegal op code of a 3-byte, 4-cycle NOP.
|
||
branch_dest: LDA #71 ; Its operand will be this 2-byte, 2-cycle instruction.
|
||
<continue>
|
||
|
||
</pre>
|
||
If you branch or jump to<tt> branch_dest, </tt>the<tt> LDA #71 </tt>will be executed; but if you
|
||
arrive there without branching, ie, from directly above it, the<tt> LDA </tt>will get skipped, and there will be no effect
|
||
on status bits. Actually, the<tt> LDA #71 </tt>will
|
||
get loaded as a two-byte operand for the illegal $DC
|
||
instruction, and the address that operand points to will get read
|
||
and the data discarded, like an absolute load-and-discard instruction;
|
||
so
|
||
you might need to be careful that you don't read an I/O register
|
||
where the I/O IC's status would be changed by doing so (like the
|
||
situation
|
||
with<tt> BIT addr</tt>). The danger of doing it inadvertently will be very low.<p>
|
||
|
||
|
||
</p></li><li>CMOS corrects all the bugs and quirks of the NMOS:<!--from p.1-10 of Rockwell book.-->
|
||
<ul>
|
||
<li><tt>JMP(xxFF): </tt>NMOS did not increment the page when reading the second byte, so the jump was wrong.
|
||
</li><li>N, V, and Z flags were incorrect after decimal operation (but C was ok). (CMOS adds one cycle to fix them.)
|
||
</li><li>A<tt> BRK </tt>instruction that was being fetched when an interrupt hit was ignored on NMOS. (CMOS executes
|
||
the<tt> BRK, </tt>then takes the interrupt.)
|
||
</li><li>D was not cleared on RST, IRQ, or NMI. (CMOS does clear D in these situations.)
|
||
</li><li>RDY being negated (pulled low, as RDY is positive
|
||
logic) during write cycle had no effect. (CMOS gives the expected
|
||
wait state(s).)
|
||
</li><li>Indexing across a page boundary caused an extra read
|
||
of an invalid address, which could cause trouble in some
|
||
hardware. (CMOS does an
|
||
extra read of the last instruction byte instead.)
|
||
</li><li>RMW instructions at effective address did one read
|
||
and two writes, which could cause trouble if it's I/O. (CMOS does
|
||
two reads and one write.)
|
||
</li></ul>
|
||
</li></ul>
|
||
|
||
<!--<br>
|
||
<h1><a NAME="def"></a></h1><center><big><big><strong>Combination hardware/software differences</strong></big></big></center>
|
||
|
||
<br>
|
||
<br>
|
||
<h1><a NAME="var"></a></h1><center><big><big><strong>Processor variations</strong></big></big></center>
|
||
|
||
<p>There were many variations on the NMOS 6502 for inexpensive game machines, home computers, and other products. The following is no doubt
|
||
only a partial list.
|
||
<ul>
|
||
<li><a href="http://6502.org/documents/datasheets/mos/mos_6500_mpu_nov_1985.pdf" target="_blank">6502, 6503, 6504, 6505, 6506, 6507, 6512,
|
||
6513, 6514, 6515</a> (.pdf) eight of these being in 28-pin packages, with variations on number of address pins and which signals are
|
||
included<p>
|
||
|
||
<li><a href="http://6502.org/documents/datasheets/mos/mos_6508_mpu.pdf" target="_blank">6508</a> (.pdf) 6502 with 256 bytes of RAM onboard
|
||
in page 0 and page 1, and an 8-bit I/O port<p>
|
||
|
||
<li><a href="http://6502.org/documents/datasheets/mos/mos_6509_mpu.pdf" target="_blank">6509</a> (.pdf) 6502 with 4-bit extended address
|
||
register for 1MB address space<p>
|
||
|
||
<li><a href="http://6502.org/documents/datasheets/mos/mos_6510_mpu_nov_1982.pdf" target="_blank">6510</a> (.pdf) omits the RDY, SYNC, φ1,
|
||
<span style="text-decoration: overline;">S.O.</span>, the N.C.'s, and one of the Vss pins, and adds an 8-bit I/O port with the data register
|
||
at address 0001, and data-direction register at adddress 0000. This port was used by the Commodore 64 for memory banking. (verify
|
||
this)<p>
|
||
|
||
<li><a href="http://6502.org/documents/datasheets/mos/mos_6500-1_one-chip_microcomputer_oct_1986.pdf" target="_blank">6500/1</a> (.pdf) 6502-based
|
||
microcontroller with 2K of ROM, 64 bytes of RAM, 32 interface I/O lines, 16-bit programmable timer/counter, and 5 interrupts<p>
|
||
|
||
<li><a href="http://6502.org/documents/datasheets/rockwell/rockwell_r6501q.pdf" target="_blank">6501Q</a> (.pdf) 6502-based
|
||
(plus<tt> RMB, SMB, BBS, </tt>and<tt> BBR </tt>instructions) microcontroller in 64-pin QUIP, with
|
||
internal clock oscillator, 192 bytes of RAM, 2 16-bit counter/timers, 32 I/O lines (including 4 edge-sensitive lines and input latching
|
||
on one 8-bit port), full-duplex serial I/O, 10 interrupts, and bus expandability<p>
|
||
|
||
<li><a href="http://6502.org/documents/datasheets/rockwell/rockwell_r6511q_r6500-13.pdf" target="_blank">6500/13</a> (.pdf) 6502-based
|
||
microcontroller with the bit-manipulation instructions of the 6501Q above, 256 bytes of ROM, 192 bytes of RAM, and the I/O of the 6501Q
|
||
above. The <u>6511Q</u> (data sheet at same URL) is the same except has no ROM.<p>
|
||
|
||
<li>
|
||
</ul>
|
||
|
||
<br>
|
||
<p>Similarly, there were many variations on the CMOS 65c02:
|
||
<ul>
|
||
<li>The Jan '87 GTE (later CMD, California Micro Devices) data book shows a similar list as above, on pages 1-12 to 1-14, but in CMOS: the 65c02,
|
||
65c03, 65c04, 65c05, 65c06, 65c07, 65c12, 65c13, 65c14, 65c15, 65c102, 65c103, 65c104, 65c105, 65c106, 65c107, 65c112, and 65c115, 14 of these
|
||
being in 28-pin packages, with variations on number of address pins and which signals are included. (The GTE specifiers added other digits
|
||
so they would be for example G65SC02, G65SC03, etc., plus suffixes for version, package type, temperature range, and speed.)
|
||
|
||
<li>
|
||
|
||
<li>Today the 65c02 is going into products at a rate of over a hundred million a year, but they're almost all in custom ICs, and WDC licenses the
|
||
IP. There have been various off-the-shelf 65c02-based microcontrollers over the decades,
|
||
Renesas and Sunplus microcontrollers' processors are similar to the 65c02 but these brands are not available in small quantities.
|
||
|
||
</ul>
|
||
|
||
|
||
<p>links from http://wilsonminesco.com/links.html#65fam:<br>
|
||
<a href="http://www.archaeology.org/1107/features/mos_technology_6502_computer_chip_cpu.html" target="_blank">6502 origins</a><br>
|
||
<a href="http://homepage.mac.com/jorgechamorro/a2things/PDFs/65xxx.txt" target="_blank"> 65816 origins, 6516, 65032, 65832</a><br> (Dead link. See below.)
|
||
<a href="http://web.archive.org/web/20100331075737/http://homepage.mac.com/jorgechamorro/a2things/PDFs/65xxx.txt" target="_blank"> 65816 origins, 6516, 65032, 65832</a><br>
|
||
<a href="http://www.commodore.ca/manuals/funet/cbm/documents/chipdata/65ce02.txt" target="_blank">65CE02 improvements over the 65c02</a><br>
|
||
<a href="http://www.atariage.com/forums/topic/151182-synertec-6516-pseudo-16bit-cpu-for-a400800/" target="_blank">6516 (Synertek) 16-bit pseudo-6502</a> for Atari 400/800 computers, never made it to market<br>
|
||
<a href="http://www.ucc.gu.uwa.edu.au/~john/65020.html" target="_blank">65020 double-wide 6502 proposal</a><br>
|
||
<a href="http://www.ex6502.altervista.org/doku.php" target="_blank">6502EX (6502 extended to 32 bits)</a><br>
|
||
<a href="http://forum.6502.org/viewtopic.php?f=1&t=1419" target="_blank">65Org32 developments of ideas</a> for an all-32-bit 65816 extension (forum topic)<br>
|
||
|
||
<p>Tell briefly about R6501 (not the original 6501 that got MOS in legal trouble with Mot), R6518, R6500/11, R6500/12, R6500/15, R65F11, R65F12
|
||
|
||
|
||
<p>The <a href="http://6502.org/documents/datasheets/mos/mos_65ce02_mpu.pdf" target="_blank">65CE02</a> was a Commodore-designed enhancement to the 65C02, with most dead bus cycles eliminated (31 op codes executed in a single clock cycle), additional instructions and addressing modes (the op code table is full), 16-bit stack pointer, relocatable zero page, extra index register Z, and DMA capability. Very few were made.
|
||
|
||
<p>Tell briefly about R65C10, 65802, 65150, 65151, 65134, 65816, 65265, 65C19
|
||
-->
|
||
|
||
|
||
<br>
|
||
<br>
|
||
<h1><a name="av"></a></h1><center><big><big><strong>Availability</strong></big></big></center>
|
||
|
||
<p>None of the NMOS parts have been made in many years (decades?) but
|
||
NOS (new old stock) can sometimes be found, and some distributors like
|
||
Jameco have
|
||
"pulls," ie, ones that have been pulled out of circuit boards, mostly
|
||
used. Some of the CMOS parts are also discontinued, the ones that
|
||
come to
|
||
mind being the GTE/CMD 65C03, '04, '05, '06, 07, '12, '13, '14, '15,
|
||
'102, '103, '104, '105, '106, '107, '112, '115, '150, and '151, the
|
||
Rockwell '19,
|
||
and the WDC 65C802. <u>WDC plans to continue making the CMOS 65C02, '816, '134 <20>C, '265 <20>C, and I/O ICs indefinitely</u>, at least in
|
||
DIP and PLCC and some also in PQFP, and there are many distributors selling them. We try to keep the forum sticky topic
|
||
"<a href="http://forum.6502.org/viewtopic.php?f=1&t=1953" target="_blank">65xx parts sources</a>" up to date, so please refer there.
|
||
|
||
<br>
|
||
<br>
|
||
<br>
|
||
</p><h1><a name="fur"></a></h1><center><big><big><strong>For further reading</strong></big></big></center>
|
||
<p>
|
||
<a href="http://forum.6502.org/viewtopic.php?f=2&t=2913&p=32682#p32682" target="_blank">65c02 advantages</a> (forum topic)<br>
|
||
<a href="http://forum.6502.org/viewtopic.php?f=4&t=1634" target="_blank">A taken branch delays interrupt handling by one instruction</a> (forum
|
||
topic) There seems to be a difference between NMOS and CMOS in this area as well.<br>
|
||
<a href="http://forum.6502.org/viewtopic.php?p=38895#p38895" target="_blank">A 65C02 bug?</a>
|
||
(it was a bug in the documentation, not the
|
||
processor) (forum topic) See Jeff's post on cycle
|
||
timing differences between NMOS & CMOS in R-M-W instructions.<br>
|
||
<a href="http://forum.6502.org/viewtopic.php?f=4&t=3360" target="_blank">Least Obvious Incompatibility</a> (forum topic)<br>
|
||
<a href="http://westerndesigncenter.com/wdc/documentation/w65c02s.pdf" target="_blank">65c02 data sheet</a> (.pdf) from WDC<br>
|
||
<a href="http://westerndesigncenter.com/wdc/documentation/w65c816s.pdf" target="_blank">65816 data sheet</a> (.pdf) from WDC<br>
|
||
"<a href="http://wdc65xx.com/Programming-Manual/" target="_blank">Programming the 65816-Including the 6502, 65C02 and 65802</a>,"
|
||
the outstanding programming manual by David Eyes and Ron Liechty. By far the best.<br>
|
||
I came across <a href="http://www.cpu-world.com/info/6502/65xx_65Cxx_65SCxx_differences.html" target="_blank">this CPU World page</a> in Feb
|
||
2018 giving more details on the variants like 6504, 6505, 6506, 6507, etc. (not so much the NMOS-CMOS differences).<br>
|
||
|
||
</p><p><br>links from my links page, under "65-family processors", at http://wilsonminesco.com/links.html#65fam :<br>
|
||
<a href="http://www.archaeology.org/1107/features/mos_technology_6502_computer_chip_cpu.html" target="_blank">6502 origins</a><br>
|
||
<!--<a href="http://homepage.mac.com/jorgechamorro/a2things/PDFs/65xxx.txt" target="_blank"> 65816 origins, 6516, 65032, 65832</a><br> (Dead link. See below.)-->
|
||
<a href="http://web.archive.org/web/20100331075737/http://homepage.mac.com/jorgechamorro/a2things/PDFs/65xxx.txt" target="_blank"> 65816 origins, 6516, 65032, 65832</a><br>
|
||
<a href="http://www.commodore.ca/manuals/funet/cbm/documents/chipdata/65ce02.txt" target="_blank">65CE02 improvements over the 65c02</a><br>
|
||
<a href="http://www.atariage.com/forums/topic/151182-synertec-6516-pseudo-16bit-cpu-for-a400800/" target="_blank">6516 (Synertek) 16-bit pseudo-6502</a> for Atari 400/800 computers, never made it to market<br>
|
||
<a href="http://www.ucc.gu.uwa.edu.au/~john/65020.html" target="_blank">65020 double-wide 6502 proposal</a><br>
|
||
<a href="http://shu.emuunlim.com/download/pcedocs/pce_cpu.html" target="_blank">HuC6280</a>,
|
||
a PC Engine using a special version of the 65c02
|
||
(with all the modern CMOS instructions minus STP and WAI), with a memory
|
||
management unit (MMU). Of special interest are the instructions
|
||
directly involved with memory mapping and moving, and a T flag, which
|
||
when set (using <tt>SET</tt>), causes accumulator
|
||
instructions to operate on the ZP address pointed to by X instead,
|
||
without affecting A! It makes it like having 257 accumulators.<br>
|
||
<a href="http://www.ex6502.altervista.org/doku.php" target="_blank">6502EX (6502 extended to 32 bits)</a><br>
|
||
<a href="http://forum.6502.org/viewtopic.php?f=1&t=1419" target="_blank">65Org32 developments of ideas</a> for an all-32-bit 65816 extension (forum topic)<br>
|
||
|
||
|
||
|
||
<br><br><br>If you know of additional differences I should add, or see errors, please email me.
|
||
|
||
<br><br>
|
||
<small>last updated Oct 12, 2021 Garth
|
||
Wilson email wilsonminesBdslextremeBcom (replacing the B's
|
||
with<strong> @ </strong>and<strong> .</strong>)</small>
|
||
<br>
|
||
|
||
|
||
</p></body></html> |