23 lines
1.1 KiB
XML
23 lines
1.1 KiB
XML
<?xml version="1" encoding="UTF-8"?>
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<!DOCTYPE gowin-fpga-project>
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<Project>
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<Template>FPGA</Template>
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<Version>5</Version>
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<Device name="GW1NR-9C" pn="GW1NR-LV9QN88PC6/I5">gw1nr9c-004</Device>
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<FileList>
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<File path="src/alu.v" type="file.verilog" enable="1"/>
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<File path="src/core.v" type="file.verilog" enable="1"/>
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<File path="src/cu.v" type="file.verilog" enable="1"/>
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<File path="src/dvi_tx/dvi_tx.v" type="file.verilog" enable="1"/>
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<File path="src/gigatron.v" type="file.verilog" enable="1"/>
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<File path="src/gowin_rpll/gowin_rpll.v" type="file.verilog" enable="1"/>
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<File path="src/gowin_sp/gowin_sp.v" type="file.verilog" enable="1"/>
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<File path="src/hdmi.v" type="file.verilog" enable="1"/>
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<File path="src/per.v" type="file.verilog" enable="1"/>
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<File path="src/prg.v" type="file.verilog" enable="1"/>
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<File path="src/ram.v" type="file.verilog" enable="1"/>
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<File path="src/registers.v" type="file.verilog" enable="1"/>
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<File path="src/gigatron.cst" type="file.cst" enable="1"/>
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</FileList>
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</Project>
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