89 lines
3.9 KiB
Plaintext
89 lines
3.9 KiB
Plaintext
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The RAM & IO expansion board plugs into the 32K SRAM location and is
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controlled by executing an originally meaningless native STORE
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instruction whose bus bits obtain data from the RAM. On a normal
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Gigatron, such an instruction is illegal because attempts to read and
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write the RAM at the same time. This results in writing a random byte
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at the specified location. The expansion board detect this condition
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interprets instead the address as a 16 bits command word.
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+-----------------------+-----------------------+---------------+
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| Operation | Mode | Bus |
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|-------+-------+-------+-------+-------+-------+-------+-------+
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| IR7 | IR6 | IR5 | IR4 | IR3 | IR2 | IR1 | IR0 |
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+-----------------------+-----------------------+---------------+
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0 | | D | / / |
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1 | | X | CTRL: 01 |
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2 | / / / / / / / / / / / | Y,D | / / |
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3 | | Y,X | / / |
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4 | | / / +---------------+
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5 +-----------------------+ / / | |
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6 | CTRL: 110 | / / | / / / / / / / |
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7 +-----------------------+ Y,X++ | |
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+-----------------------+-----------------------+---------------+
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The 16 bits of the address issued by the CTRL instruction are
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interpreted as follows:
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+-------------------------+------------------------------+
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| high address byte | low address byte |
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+-------------------------+------------------------------+
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| MOSI -- -- -- -- -- -- | B1 B0 CS3 CS2 CS1 CS0 -- SCK |
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+-------------------------+------------------------------+
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MOSI: sets the state of the SPI MOSI line
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B1 B0: sets the RAM bank accessed at addresses 0x8000-0xffff
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CSx: sets the (negative) chip select signal for up to four SPI ports
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SCK: sets the state of the SPI clock line
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Notes:
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* When SCK is set, instructions that read the memory do not return
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memory values, but return a byte whose four low bits represent the
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state of the four MISO lines associated with four potential SPI
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ports. This only happens very briefly during the execution of
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SYS_SpiExchangeBytes_v4_134.
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* Although the original expansion board potentially offers four SPI
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ports, they rarely can be used simultaneously because few existing
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SPI devices tri-state their MISO line when CS is disabled. Most
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existing board only provide two SPI ports and sometimes repurpose
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CS3 and CS2 to command additional functions.
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* vCPU programs can use SYS_ExpanderControl_v4_40 to execute a CTRL
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instruction with vAC as argument. This call makes sure that the SCK
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bit remains zero and mirrors the low address word in location
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ctrlBits_v5 (0x1f8).
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* The ROM initially issues a CTRL command that sets the control bits
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to 0x7c. This means that the four SPI ports are disabled and
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that addresses 0x8000-0xffff display bank 1.
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Pointers:
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- Initial board development
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https://forum.gigatron.io/viewtopic.php?t=64&start=90
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- Proposed conventions for additional expansion board functions
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https://forum.gigatron.io/viewtopic.php?t=331
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- Hans61 recreation of the original 128K board. This board only uses
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common 74'00 chips and come in two version. The first version offers
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four SPI that cannot be plugged simultaneously like the original
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board. The improved version offers two fully functional SPI ports.
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Both are very easy to build.
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https://forum.gigatron.io/viewtopic.php?p=3694#p3694
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https://github.com/hans61/Gigatron-TTL/ ... ansion128k
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- lb3361 expansion "retro" or "dual drive" 128K board. This board
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relies on two GAL chips and offers additional features (see doc).
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https://github.com/lb3361/gigatron-lb/tree/main/extension-retro
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https://forum.gigatron.io/viewtopic.php?t=332
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