89 lines
3.8 KiB
Plaintext
89 lines
3.8 KiB
Plaintext
======================================================
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vCPU: The virtual 16-bit CPU for Gigatron applications
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======================================================
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vCPU is the interpreted 16-bit virtual processor running in the dead
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time of the video/sound loop.
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This file is an *extract* from Docs/GCL-language.txt. GCL and vCPU
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are closely tied together. For a detailed explanation of both,
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please refer to that document.
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-----------------
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Programming model
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-----------------
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vAC ACcumulator (16-bits)
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vPC Program Counter (16-bits)
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vLR Link Register (16-bits)
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vSP Stack Pointer (8-bits)
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----------------------
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vCPU instruction table
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----------------------
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Mnem. Encoding #C Description
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----- --------- -- -----------
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ST $5E DD 16 Store byte in zero page ([D]=vAC&256)
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STW $2B DD 20 Store word in zero page ([D],[D+1]=vAC&255,vAC>>8)
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STLW $EC DD 26 Store word in stack frame ([vSP+D],[vSP+D+1]=vAC&255,vAC>>8)
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LD $1A DD 18 Load byte from zero page (vAC=[D])
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LDI $59 DD 16 Load immediate small positive constant (vAC=D)
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LDWI $11 LL HH 20 Load immediate word constant (vAC=$HHLL)
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LDW $21 DD 20 Word load from zero page (vAC=[D]+256*[D+1])
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LDLW $EE DD 26 Load word from stack frame (vAC=[vSP+D]+256*[vSP+D+1])
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ADDW $99 DD 28 Word addition with zero page (vAC+=[D]+256*[D+1])
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SUBW $B8 DD 28 Word subtraction with zero page (vAC-=[D]+256*[D+1])
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ADDI $E3 DD 28 Add small positive constant (vAC+=D)
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SUBI $E6 DD 28 Subtract small positive constant (vAC-=D)
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LSLW $E9 28 Shift left ('ADDW vAC' will not work!) (vAC<<=1)
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INC $93 DD 16 Increment zero page byte ([D]++)
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ANDI $82 DD 16 Logical-AND with small constant (vAC&=D)
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ANDW $F8 DD 28 Word logical-AND with zero page (vAC&=[D]+256*[D+1])
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ORI $88 DD 14 Logical-OR with small constant (vAC|=D)
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ORW $FA DD 28 Word logical-OR with zero page (vAC|=[D]+256*[D+1])
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XORI $8C DD 14 Logical-XOR with small constant (vAC^=D)
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XORW $FC DD 26 Word logical-XOR with zero page (vAC^=[D]+256*[D+1])
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PEEK $AD 26 Read byte from memory (vAC=[vAC])
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DEEK $F6 28 Read word from memory (vAC=[vAC]+256*[vAC+1])
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POKE $F0 DD 28 Write byte in memory ([[D+1],[D]]=vAC&255)
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DOKE $F3 DD 28 Write word in memory ([[D+1],[D]],[[D+1],[D]+1]=vAC&255,vAC>>8)
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LUP $7F DD 26 ROM lookup, needs trampoline in target page (vAC=ROM[vAC+D])
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BRA $90 DD 14 Branch unconditionally (vPC=(vPC&0xff00)+D)
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BCC $35 CC DD 28 Test vAC and branch conditionally. CC can be
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EQ=$3F, NE=$72, LT=$50, GT=$4D, LE=$56, GE=$53
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CALL $CF DD 26 Goto address and remember vPC (vLR,vPC=vPC+2,[D]+256*[D+1]-2)
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RET $FF 16 Leaf return (vPC=vLR-2)
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PUSH $75 26 Push vLR on stack ([vSP-2],v[vSP-1],vSP=vLR&255,vLR>>8,vLR-2)
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POP $63 26 Pop address from stack (vLR,vSP=[vSP]+256*[vSP+1],vSP+2)
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ALLOC $DF DD 14 Create or destroy stack frame (vSP+=D)
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SYS $B4 DD 20+ Native function call using at most 2*T cycles, D=270-max(14,T)
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HALT $B4 $80 inf Halt vCPU execution
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DEF $CD DD 26 Define data or code (vAC,vPC=vPC+2,(vPC&0xff00)+D)
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----------------------------------------
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Experimental vCPU instructions in DEVROM
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----------------------------------------
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See also this thread: https://forum.gigatron.io/viewtopic.php?f=4&t=136
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Mnem. Encoding #C Description
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----- --------- -- -----------
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CALLI $85 LL HH 28 Goto immediate address and remember vPC (vLR,vPC=vPC+3,$HHLL-2)
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CMPHS $1f DD 28 Adjust high byte for signed compare (vACH=XXX)
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CMPHU $97 DD 28 Adjust high byte for unsigned compare (vACH=XXX)
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Special sequence:
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RTI $11 $00 $04 $7F DD
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48 Return from interrupt
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Changed cycle times
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-------------------
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LD $1A DD 22 (was 18)
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INC $93 DD 22 (was 16)
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ANDI $82 DD 22 (was 16)
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DEF $CD DD 24 (was 26)
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-- End of document --
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