94 lines
4.0 KiB
Plaintext
94 lines
4.0 KiB
Plaintext
; **************************************************************************************************
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; **************************************************************************************************
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; THIS WILL NOT RUN ON REAL HARDWARE UNLESS YOU BURN THE NATIVE CODE AT THE BOTTOM
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; OF THIS FILE INTO THE GIGATRONS ROM AT THE CORRECT ADDRESS, EMULATION ONLY!
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; **************************************************************************************************
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; **************************************************************************************************
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vram EQU 0x0800
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REENTER EQU 0x03CB
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sysFn EQU 0x22
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i EQU 0x30
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j EQU 0x31
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vbase EQU 0x40
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SYS_ClearRow32_56 EQU 0x2300 ; clear 32 pixels at a time, native code that is defined with either DBR or DWR is written to ROM at this address
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LDWI vram
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STW vbase ; vram base address
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LDWI SYS_ClearRow32_56 ; clears 32 row pixels at a time
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STW sysFn
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clear SYS 56
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LDWI 0x0020
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ADDW vbase
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STW vbase
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LD vbase+1
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SUBI 0x7F
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BLT clear
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LDI 0x08 ; finish off last row
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ST i
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last_row SYS 56
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LDWI 0x0020
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ADDW vbase
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STW vbase
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LD i
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SUBI 0x01
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ST i
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BGT last_row
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loop BRA loop
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; these are native code routines that are written into ROM using the DBR command, (Define Byte ROM), at the equate defined
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; above: this native code is specific to this vCPU asm module with the input registers that it accepts
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;SYS_ClearRow32_56 DBR $11 $40 $15 $41 $00 $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00
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; DBR $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00
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; DBR $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00
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; DBR $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $14 $03 $E0 $CB $00 $E4
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SYS_ClearRow32_56 .LD [0x40],X
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.LD [0x41],Y
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.LD 0x00
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.NOP ; pad instructions so odd(14 + number of instructions) = true
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.LD REENTER >>8,y
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.JMP y,REENTER
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.LD 0xE4 ; 0 - ((14 + number of instructions + 3) / 2), odd(14 + number of instructions) = true
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