406 lines
14 KiB
Plaintext
406 lines
14 KiB
Plaintext
; **************************************************************************************************
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; **************************************************************************************************
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; THIS WILL NOT RUN ON REAL HARDWARE UNLESS YOU BURN THE NATIVE CODE AT THE BOTTOM
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; OF THIS FILE INTO THE GIGATRONS ROM AT THE CORRECT ADDRESS, EMULATION ONLY!
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; **************************************************************************************************
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; **************************************************************************************************
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; game of life coded by at67, original algorithm by John Conway
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; 32X32 runs about 2 fps on a 6.25MHz Gigatron TTL
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; more optimisation: neighbour count buffer is generated from alive cells in cell buffer, pointer arithmetic with offsets,
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; a look up table to evalute neighbours count and a SYS function to plot the 2x2 pixels.
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; this world has boundaries
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vram EQU 0x0800
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buff0 EQU 0x09A0
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buff1 EQU 0x09D0
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sysFn EQU 0x22
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cells0 EQU 0x30
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cells1 EQU 0x32
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i EQU 0x34
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j EQU 0x35
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neighbours EQU 0x36
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cell EQU 0x37
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n_address EQU 0x38
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buffer0 EQU 0x3A
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buffer1 EQU 0x3C
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generation EQU 0x3E
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vbase EQU 0x40
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pixels EQU 0x42
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pattern EQU 0x44
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gliders EQU 0x46
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lut_modify EQU 0x48
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j_one EQU 0x4A
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offset0 EQU 0x4C
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offset1 EQU 0x4E
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offset2 EQU 0x50
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offset3 EQU 0x52
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offset4 EQU 0x54
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offset5 EQU 0x56
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offset6 EQU 0x58
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offset7 EQU 0x5A
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scratch EQU 0x5C
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screen_w EQU 160
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screen_h EQU 120
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bounds EQU 46 ; determines max size of world, limited by available ram in blank scanlines,
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; using bytes per cell, 1 pixel world boundary and two buffers means 46*46 is maximum size
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_startAddress_ EQU 0x0200 ; entry point for the code, if this is missing defaults to 0x0200
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_callTable_ EQU 0x007E ; call addresses are automatically stored here by the assembler, it grows downwards
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; *NOTE* gt1 spec only allows for one zero page segment, .vasm files use this for the call table
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; do *NOT* make this address higher than 0x00BE, it will conflict with future ROM loading mechanisms
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; do *NOT* define constants, (DB or DW), between 0x30 -> 0x44 and 0xc0 -> 0xFF, these addresses are
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; used by the loader and the vCPU stack, you can create variables in these areas as long as you don't
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; corrupt your nested CALL return addresses on the stack
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_singleStepWatch_ EQU neighbours ; the single step debugger watches this variable location to decide when to step,
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; choose a variable that is updated often
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SYS_DrawPixel2x2_32 EQU 0x2300 ; 2x2 pixel plot, native code that is defined with either DBR or DWR is written to ROM at this address
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SYS_ClearRow32_56 EQU 0x2400 ; clear 32 pixels at a time, native code that is defined with either DBR or DWR is written to ROM at this address
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n_lut EQU 0x60
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n_lut_cell EQU 0x62
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counts EQU 0x0300
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LDI 0x00 ; look up table that is used to evaluate neighbour counts
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ST n_lut
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ST n_lut+1
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ST n_lut+2 ; self modifying code updates this location with previous generation cell
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ST n_lut+4
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ST n_lut+5
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ST n_lut+6
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ST n_lut+7
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ST n_lut+8
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LDI 0xFF
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ST n_lut+3
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LDWI vram
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STW vbase ; vram base address
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STW pixels ; pixel address
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LDWI buff0
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STW buffer0
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LDWI buff1
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STW buffer1
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LDWI lut + 1 ; self modifying address
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STW lut_modify
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LDWI 0x0100
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STW j_one
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;clear LDI 0x00 ; clear screen and buffers
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; POKE vbase
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; LDWI 0x0001
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; ADDW vbase
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; STW vbase
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; LD vbase+1
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; SUBI 0x80
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; BLT clear
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LDWI SYS_ClearRow32_56 ; clears 32 row pixels at a time
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STW sysFn
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clear SYS 56
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LDWI 0x0020
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ADDW vbase
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STW vbase
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LD vbase+1
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SUBI 0x7F
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BLT clear
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LDI 0x08 ; finish off last row
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ST i
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last_row SYS 56
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LDWI 0x0020
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ADDW vbase
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STW vbase
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LD i
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SUBI 0x01
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ST i
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BGT last_row
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LDWI 0x09A3
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STW gliders
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LDI 0x06 ; number of gliders
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ST i
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glider LDW gliders
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STW pattern
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LDI 0xFF
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POKE pattern
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LDW j_one
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ADDW pattern
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STW pattern
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LDI 0xFF
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POKE pattern
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LDW j_one
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ADDW pattern
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STW pattern
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LDI 0xFF
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POKE pattern
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LD pattern
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SUBI 0x01
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ST pattern
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LDI 0xFF
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POKE pattern
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LDW pattern
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SUBW j_one
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STW pattern
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LD pattern
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SUBI 0x01
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ST pattern
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LDI 0xFF
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POKE pattern
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LD gliders ; gap between gliders
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ADDI 0x05
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ST gliders
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LD i
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SUBI 0x01
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ST i
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BGT glider
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LDWI 0x0001
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STW j_one
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STW generation
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LDI (screen_w - bounds*2)/0b10 ; position in screen to render life
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ST vbase
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LDI (screen_h - bounds*0q2)/0x0002 + 8 ; expressions can use equates and use the same number handling as equates
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ST vbase+1
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LDI bounds
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ST i
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ST j
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LDWI 0x0101 ; -ve
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STW offset0
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LDWI 0x0100 ; -ve
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STW offset1
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LDWI 0x00FF ; -ve
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STW offset2
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LDWI 0x0001 ; +ve
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STW offset3
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LDWI 0x0101 ; +ve
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STW offset4
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LDWI 0x0100 ; +ve
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STW offset5
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LDWI 0x00FF ; +ve
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STW offset6
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LDWI 0x0001 ; -ve
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STW offset7
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LDWI SYS_DrawPixel2x2_32
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STW sysFn
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CALL counts ; jump across a page boundary
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; counts buffer
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counts LDW i ; buffer0
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ADDW buffer0
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PEEK ; get buffer0 cell
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BEQ continue
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LDW i ; buffer1
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ADDW buffer1
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STW cells1
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SUBW offset0 ; -1, -1 neighbour
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STW n_address
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PEEK
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ADDI 0x01
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POKE n_address
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LDW cells1
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SUBW offset1 ; 0, -1 neighbour
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STW n_address
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PEEK
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ADDI 0x01
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POKE n_address
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LDW cells1
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SUBW offset2 ; 1, -1 neighbour
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STW n_address
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PEEK
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ADDI 0x01
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POKE n_address
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LDW cells1
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ADDW offset3 ; 1, 0 neighbour
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STW n_address
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PEEK
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ADDI 0x01
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POKE n_address
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LDW cells1
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ADDW offset4 ; 1, 1 neighbour
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STW n_address
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PEEK
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ADDI 0x01
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POKE n_address
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LDW cells1
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ADDW offset5 ; 0, 1 neighbour
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STW n_address
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PEEK
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ADDI 0x01
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POKE n_address
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LDW cells1
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ADDW offset6 ; -1, 1 neighbour
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STW n_address
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PEEK
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ADDI 0x01
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POKE n_address
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LDW cells1
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SUBW offset7 ; -1, 0 neighbour
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STW n_address
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PEEK
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ADDI 0x01
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POKE n_address
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continue LD i ; dec i
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SUBI 0x01
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ST i
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BGE counts
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LDI bounds
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ST i
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LD j ; dec j
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SUBI 0x01
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ST j
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BGE counts
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LDI bounds
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ST j
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generate LDW i ; buffer1
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ADDW buffer1
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STW cells1
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PEEK
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ST neighbours ; get neighbours count
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LDI 0x00
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POKE cells1 ; reset neighbours count
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LDW i ; buffer0
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ADDW buffer0
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STW cells0
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PEEK ; get cell
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ST n_lut_cell ; save cell into neighbours lut
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LD neighbours ; lut evaluates neighbours count
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ADDI n_lut
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POKE lut_modify ; lut_modify points to operand in "LD n_lut"
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lut LD n_lut ; get new cell using self modifying code
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POKE cells0 ; save new cell
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ST cell
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LDW i ; draw cell 2x2
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LSLW
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ADDW vbase
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STW pixels
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SYS 32
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LD i ; dec i
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SUBI 0x01
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ST i
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BGE generate
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LDI bounds
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ST i
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LD j ; dec j
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SUBI 0x01
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ST j
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BGE generate
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LDI bounds
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ST j
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LDW generation
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ADDW j_one
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STW generation
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BRA counts
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; these are native code routines that are written into ROM using the DBR command, (Define Byte ROM), at the equate defined
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; above: this native code is specific to this vCPU asm module with the input registers that it accepts
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;SYS_ClearRow32_56 DBR $11 $40 $15 $41 $00 $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00
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; DBR $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00
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; DBR $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00
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; DBR $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $DE $00 $14 $03 $E0 $CB $00 $E4
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;SYS_DrawPixel2x2_32 DBR $01 $37 $11 $42 $15 $43 $DE $00 $CE $00 $11 $42 $00 $01 $95 $43 $01 $37 $DE $00 $CE $00 $14 $03 $E0 $CB $00 $F0
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SYS_DrawPixel2x2_32 .LD [0x37]
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.LD [0x42],X
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.LD [0x43],Y
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.ST [Y,X++]
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.ST [Y,X]
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.LD [0x42],X
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.LD 0x01
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.ADDA [0x43],Y
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.LD [0x37]
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.ST [Y,X++]
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.ST [Y,X]
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.NOP ; pad instructions so odd(14 + number of instructions) = true
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.LD 0x03,Y
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.JMP Y,0xCB
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.LD 0xF0 ; 0 - ((14 + number of instructions + 3) / 2), odd(14 + number of instructions) = true
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SYS_ClearRow32_56 .LD [0x40],X
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.LD [0x41],Y
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.LD 0x00
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.ST [Y,X++]
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.NOP ; pad instructions so odd(14 + number of instructions) = true
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.LD 0x03,Y
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.JMP Y,0xCB
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.LD 0xE4 ; 0 - ((14 + number of instructions + 3) / 2), odd(14 + number of instructions) = true
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