47 lines
1.3 KiB
Plaintext
47 lines
1.3 KiB
Plaintext
See also:
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https://github.com/kervinck/gigatron-rom/issues/125
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https://forum.gigatron.io/viewtopic.php?f=4&t=175
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vCPU interrupts
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---------------
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vReset
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------
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TODO
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vIRQ
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----
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Vertical blank interrupt triggering each time [frameCount] wraps
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around to 0 (and the interrupt vector is non-zero).
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Interrupt vector: $1f6.$1f7
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Minimal context of vPC and vAC will be stored at $30..$33. The
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mechanism won't save any further context (vLR, vSP, sysArgs, ...)!
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Return from interrupt sequence:
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LDWI $400 ;RTI 0
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LUP 0
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The interrupt handler always starts in vCPU mode. Fast return to
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vCPU code is immediate: when possible it takes place in the same
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time slice (48 cycles).
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If we potentially interrupt non-vCPU code (v6502), the interrupt
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handler must store, in zero page ($xx), the vAC value it receives.
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The programmer can decide on the address $xx. Upon entry, vAC holds
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additional state information that allows switching back to non-vCPU.
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For future extendibility, the handler must store the whole word.
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STW $xx
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Then return from the handler with:
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LDWI $400 ;RTI $xx
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LUP $xx
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This will switch back to the interrupted interpreter. It takes
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effect in the next timeslice. The return handler waits for that.
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-- End of document --
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