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update tvp7002 driver for external sync processing

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This commit is contained in:
marqs 2023-02-13 18:51:39 +02:00
parent 76da437125
commit 02b2495221
4 changed files with 38 additions and 518 deletions
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59
software/sys_controller/tvp7002/tvp7002.c
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015-2018 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2023 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@ -65,11 +65,11 @@ static void tvp_set_clamp_alc(video_type type, alt_u8 clamp_ref_offset, alt_8 cl
alt_u8 clamp_width, alc_offset;
switch (type) {
case VIDEO_LDTV:
/*case VIDEO_LDTV:
clamp_pos += 2;
clamp_width = 6;
alc_offset = 1;
break;
break;*/
case VIDEO_HDTV:
clamp_pos += 50;
clamp_width = 32;
@ -145,24 +145,30 @@ inline void tvp_reset()
inline void tvp_disable_output()
{
alt_u8 syncproc_rst = tvp_readreg(TVP_MISCCTRL4) | (1<<7);
tvp_writereg(TVP_MISCCTRL1, 0x13);
usleep(10000);
tvp_writereg(TVP_MISCCTRL2, 0x03);
usleep(10000);
tvp_writereg(TVP_MISCCTRL4, syncproc_rst);
usleep(1000);
tvp_writereg(TVP_MISCCTRL4, syncproc_rst & 0x7F);
}
inline void tvp_enable_output()
{
usleep(10000);
tvp_writereg(TVP_MISCCTRL1, 0x11);
usleep(10000);
tvp_writereg(TVP_MISCCTRL2, 0x00);
usleep(10000);
}
inline void tvp_powerdown()
{
alt_u8 syncproc_rst = tvp_readreg(TVP_MISCCTRL4) | (1<<7);
tvp_writereg(TVP_MISCCTRL4, syncproc_rst);
usleep(1000);
tvp_writereg(TVP_MISCCTRL4, syncproc_rst & 0x7F);
usleep(1000);
tvp_writereg(TVP_MISCCTRL1, 0x13);
tvp_writereg(TVP_POWERCTRL, 0x07);
}
inline void tvp_powerup()
{
tvp_writereg(TVP_MISCCTRL1, 0x11);
tvp_writereg(TVP_POWERCTRL, 0x00);
}
inline void tvp_set_hpllcoast(alt_u8 pre, alt_u8 post)
@ -192,9 +198,6 @@ void tvp_init()
.c_gain = DEFAULT_COARSE_GAIN,
};
// disable output
tvp_disable_output();
// Set default configuration (skip those which match register reset values)
// Configure external refclk, HPLL generated pclk
@ -208,6 +211,9 @@ void tvp_init()
// NOTE: Value 1 syncs the edges!
tvp_writereg(TVP_VSOUTALIGN, 1);
// Bypass VSYNC processing
tvp_writereg(TVP_MISCCTRL4, 0x09);
// Set default CSC coeffs.
tvp_sel_csc(&csc_coeffs[0]);
@ -242,6 +248,10 @@ void tvp_init()
//set analog (coarse) gain to max recommended value (-> 91% of the ADC range with 0.7Vpp input)
//set rest of the gain digitally (fine) to utilize 100% of the range at the output (0.91*(1+(26/256)) = 1)
tvp_set_gain_offset(&def_gain_offs);
// Disable PLL and ADC but enable outputs to enable frontend mode detection
tvp_enable_output();
tvp_powerdown();
}
void tvp_set_gain_offset(color_setup_t *col) {
@ -344,17 +354,12 @@ void tvp_set_clp_lpf(alt_u8 val)
printf("CLP LPF value set to 0x%x\n", val);
}
alt_u8 tvp_set_hpll_phase(alt_u8 val, alt_u8 sample_mult)
void tvp_set_hpll_phase(alt_u8 val)
{
alt_u8 sample_sel;
alt_u8 status = tvp_readreg(TVP_HPLLPHASE) & 0x07;
sample_sel = (val*sample_mult)/32;
val = val*sample_mult % 32;
tvp_writereg(TVP_HPLLPHASE, (val<<3)|status);
printf("Phase selection: %u/%u (FPGA), %u/32 (TVP)\n", sample_sel+1, sample_mult, val+1);
return sample_sel;
printf("TVP Phase set to %u/32 (%u deg)\n", val, (val*11250)/1000);
}
void tvp_set_sog_thold(alt_u8 val)
@ -383,7 +388,7 @@ void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per
case VIDEO_PC:
tvp_writereg(TVP_MISCCTRL4, 0x0D);
break;
case VIDEO_LDTV:
//case VIDEO_LDTV:
case VIDEO_SDTV:
case VIDEO_EDTV:
case VIDEO_HDTV:
@ -412,7 +417,7 @@ void tvp_source_sel(tvp_input_t input, tvp_sync_input_t syncinput, video_format
else // RGBS
tvp_writereg(TVP_SYNCCTRL1, 0x53);
usleep(1000);
usleep(100000);
sync_status = tvp_readreg(TVP_SYNCSTAT);
if (sync_status & (1<<7))
printf("%s detected, %s polarity\n", (sync_status & (1<<3)) ? "Csync" : "Hsync", (sync_status & (1<<5)) ? "pos" : "neg");

19
software/sys_controller/tvp7002/tvp7002.h
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015-2018 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2023 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@ -26,7 +26,6 @@
#define DEFAULT_VSYNC_THOLD 0x44
#define DEFAULT_LINELEN_TOL 0x06
#define DEFAULT_SAMPLER_PHASE 0x10
#define DEFAULT_PRE_COAST 1
#define DEFAULT_POST_COAST 0
#define DEFAULT_SYNC_LPF 0
@ -74,16 +73,6 @@ typedef struct {
alt_u16 B_Pr;
} ypbpr_to_rgb_csc_t;
typedef struct {
alt_u8 r_f_off;
alt_u8 g_f_off;
alt_u8 b_f_off;
alt_u8 r_f_gain;
alt_u8 g_f_gain;
alt_u8 b_f_gain;
alt_u8 c_gain;
} __attribute__((packed)) color_setup_t;
inline alt_u32 tvp_readreg(alt_u32 regaddr);
@ -95,6 +84,10 @@ inline void tvp_disable_output();
inline void tvp_enable_output();
inline void tvp_powerdown();
inline void tvp_powerup();
inline void tvp_set_hpllcoast(alt_u8 pre, alt_u8 post);
inline void tvp_set_linelen_tol(alt_u8 val);
@ -115,7 +108,7 @@ void tvp_set_sync_lpf(alt_u8 val);
void tvp_set_clp_lpf(alt_u8 val);
alt_u8 tvp_set_hpll_phase(alt_u8 val, alt_u8 sample_mult);
void tvp_set_hpll_phase(alt_u8 val);
void tvp_set_sog_thold(alt_u8 val);

295
software/sys_controller/tvp7002/video_modes.c
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@ -1,295 +0,0 @@
//
// Copyright (C) 2015-2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
#include <stdio.h>
#include <unistd.h>
#include <string.h>
#include "system.h"
#include "av_controller.h"
#include "video_modes.h"
#define LINECNT_MAX_TOLERANCE 30
extern avmode_t cm;
const mode_data_t video_modes_default[] = VIDEO_MODES_DEF;
mode_data_t video_modes[VIDEO_MODES_CNT];
/* TODO: rewrite, check hz etc. */
alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, alt_u8 h_syncinlen)
{
alt_8 i;
alt_u8 num_modes = sizeof(video_modes)/sizeof(mode_data_t);
mode_flags valid_lm[] = { MODE_PT, (MODE_L2 | (MODE_L2<<cm.cc.l2_mode)), (MODE_L3_GEN_16_9<<cm.cc.l3_mode), (MODE_L4_GEN_4_3<<cm.cc.l4_mode), (MODE_L5_GEN_4_3<<cm.cc.l5_mode) };
mode_flags target_lm;
alt_u8 pt_only = 0;
// one for each video_group
alt_u8* group_ptr[] = { &pt_only, &cm.cc.pm_240p, &cm.cc.pm_384p, &cm.cc.pm_480i, &cm.cc.pm_480p, &cm.cc.pm_1080i };
for (i=0; i<num_modes; i++) {
switch (video_modes[i].group) {
case GROUP_384P:
//fixed Line2x/3x mode for 240x360p
valid_lm[2] = MODE_L2_240x360;
valid_lm[3] = MODE_L3_240x360;
valid_lm[4] = MODE_L3_GEN_16_9;
if (video_modes[i].v_total == 449) {
if (!strncmp(video_modes[i].name, "720x400", 7)) {
if (cm.cc.s400p_mode == 0)
continue;
} else if (!strncmp(video_modes[i].name, "640x400", 7)) {
if (cm.cc.s400p_mode == 1)
continue;
}
}
break;
case GROUP_480I:
//fixed Line3x/4x mode for 480i
valid_lm[2] = MODE_L3_GEN_16_9;
valid_lm[3] = MODE_L4_GEN_4_3;
break;
case GROUP_480P:
if (video_modes[i].vic == HDMI_480p60) {
switch (cm.cc.s480p_mode) {
case 0: // Auto
if (h_syncinlen > 82)
continue;
break;
case 1: // DTV 480p
break;
default:
continue;
}
} else if (video_modes[i].flags & MODE_L2_480x272) { // hit "480x272" on the list
switch (cm.cc.s480p_mode) {
case 3: // PSP 480x272
// force optimized Line2x mode for 480x272
valid_lm[1] = MODE_L2_480x272;
break;
default:
continue;
}
} else if (video_modes[i].vic == HDMI_640x480p60) {
switch (cm.cc.s480p_mode) {
case 0: // Auto
case 2: // VESA 640x480@60
break;
default:
continue;
}
}
break;
default:
break;
}
// Skip potentially conflicting 50Hz presets if refresh rate is much higher
if ((video_modes[i].vic == HDMI_576p50) ||
(video_modes[i].vic == HDMI_720p50) ||
(video_modes[i].vic == HDMI_1080i50) ||
(video_modes[i].vic == HDMI_1080p50))
{
if (hz >= 55)
continue;
}
target_lm = valid_lm[*group_ptr[video_modes[i].group]];
if ((target_lm & video_modes[i].flags) && (progressive == !(video_modes[i].flags & MODE_INTERLACED)) && (totlines <= (video_modes[i].v_total+LINECNT_MAX_TOLERANCE))) {
// defaults
cm.tx_pixelrep = TX_PIXELREP_DISABLE;
cm.hdmitx_pixr_ifr = 0;
cm.hdmitx_vic = HDMI_Unknown;
cm.sample_mult = 1;
cm.hsync_cut = 0;
cm.target_lm = target_lm & video_modes[i].flags; //ensure L2 mode uniqueness
switch (cm.target_lm) {
case MODE_PT:
cm.fpga_vmultmode = FPGA_V_MULTMODE_1X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
cm.hdmitx_vic = video_modes[i].vic;
// Upsample / pixel-repeat horizontal resolution of 240p/480i/384p modes to fulfill min. 25MHz TMDS clock requirement
if ((video_modes[i].group == GROUP_240P) || (video_modes[i].group == GROUP_480I) || ((video_modes[i].group == GROUP_384P) && (video_modes[i].flags & MODE_PLLDIVBY2))) {
if (cm.cc.upsample2x)
cm.sample_mult = 2;
else
cm.tx_pixelrep = TX_PIXELREP_2X;
cm.hdmitx_pixr_ifr = TX_PIXELREP_2X;
}
break;
case MODE_L2:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
// Use native 2x sampling with low-res modes when possible to minimize jitter and generate min. 25MHz input pclk for FPGA PLL
if ((!cm.cc.vga_ilace_fix) && (video_modes[i].h_total < 1400) && ((video_modes[i].group == GROUP_240P) || (video_modes[i].group == GROUP_384P) || (video_modes[i].group == GROUP_480I))) {
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED_1X;
cm.sample_mult = 2;
} else {
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
}
// Upsample / pixel-repeat horizontal resolution of 384p/480p/960i modes
if ((video_modes[i].group == GROUP_384P) || (video_modes[i].group == GROUP_480P) || ((video_modes[i].group == GROUP_1080I) && (video_modes[i].h_total < 1200))) {
if (cm.cc.upsample2x) {
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
cm.sample_mult = 2;
} else {
cm.tx_pixelrep = TX_PIXELREP_2X;
}
}
break;
case MODE_L2_512_COL:
case MODE_L2_480x272:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 2;
break;
case MODE_L2_256_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED_1X;
cm.sample_mult = 6;
break;
case MODE_L2_320_COL:
case MODE_L2_384_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED_1X;
cm.sample_mult = 4;
break;
case MODE_L2_240x360:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 5;
break;
case MODE_L3_GEN_16_9:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
// Upsample / pixel-repeat horizontal resolution of 480i mode
if (video_modes[i].group == GROUP_480I) {
if (cm.cc.upsample2x)
cm.sample_mult = 2;
else
cm.tx_pixelrep = TX_PIXELREP_2X;
}
break;
case MODE_L3_GEN_4_3:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_ASPECTFIX;
break;
case MODE_L3_512_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 2;
break;
case MODE_L3_384_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 3;
break;
case MODE_L3_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 4;
break;
case MODE_L3_256_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 5;
break;
case MODE_L3_240x360:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 7;
cm.hsync_cut = 13;
break;
case MODE_L4_GEN_4_3:
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
// Upsample / pixel-repeat horizontal resolution of 480i mode
if (video_modes[i].group == GROUP_480I) {
if (cm.cc.upsample2x)
cm.sample_mult = 2;
else
cm.tx_pixelrep = TX_PIXELREP_2X;
}
break;
case MODE_L4_512_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 2;
break;
case MODE_L4_384_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 3;
break;
case MODE_L4_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 4;
break;
case MODE_L4_256_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 5;
break;
case MODE_L5_GEN_4_3:
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
cm.hsync_cut = 120;
break;
case MODE_L5_512_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 3;
cm.hsync_cut = 40;
break;
case MODE_L5_384_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 4;
cm.hsync_cut = 30;
break;
case MODE_L5_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 5;
cm.hsync_cut = 24;
break;
case MODE_L5_256_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 6;
cm.hsync_cut = 20;
break;
default:
printf("WARNING: invalid target_lm\n");
continue;
break;
}
if (cm.hdmitx_vic == HDMI_Unknown)
cm.hdmitx_vic = cm.cc.default_vic;
return i;
}
}
return -1;
}

183
software/sys_controller/tvp7002/video_modes.h
View File

@ -1,183 +0,0 @@
//
// Copyright (C) 2015-2019 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
#ifndef VIDEO_MODES_H_
#define VIDEO_MODES_H_
#include <alt_types.h>
#include "sysconfig.h"
#include "it6613_sys.h"
#define H_TOTAL_MIN 300
#define H_TOTAL_MAX 2800
#define H_TOTAL_ADJ_MAX 19
#define H_SYNCLEN_MIN 10
#define H_SYNCLEN_MAX 255
#define H_BPORCH_MIN 1
#define H_BPORCH_MAX 255
#define H_ACTIVE_MIN 200
#define H_ACTIVE_MAX 1920
#define V_SYNCLEN_MIN 1
#define V_SYNCLEN_MAX 7
#define V_BPORCH_MIN 1
#define V_BPORCH_MAX 236 // 255 - 12 for L5FMT_1920x1080 - 7 for V_SYNCLEN_MAX
#define V_ACTIVE_MIN 160
#define V_ACTIVE_MAX 1200
typedef enum {
FORMAT_RGBS = 0,
FORMAT_RGBHV = 1,
FORMAT_RGsB = 2,
FORMAT_YPbPr = 3
} video_format;
typedef enum {
VIDEO_LDTV = (1<<0),
VIDEO_SDTV = (1<<1),
VIDEO_EDTV = (1<<2),
VIDEO_HDTV = (1<<3),
VIDEO_PC = (1<<4),
} video_type;
typedef enum {
GROUP_NONE = 0,
GROUP_240P = 1,
GROUP_384P = 2,
GROUP_480I = 3,
GROUP_480P = 4,
GROUP_1080I = 5,
} video_group;
typedef enum {
MODE_INTERLACED = (1<<0),
MODE_PLLDIVBY2 = (1<<1),
//at least one of the flags below must be set for each mode
MODE_PT = (1<<2),
MODE_L2 = (1<<3),
MODE_L2_512_COL = (1<<4),
MODE_L2_384_COL = (1<<5),
MODE_L2_320_COL = (1<<6),
MODE_L2_256_COL = (1<<7),
MODE_L2_240x360 = (1<<8),
MODE_L2_480x272 = (1<<9),
MODE_L3_GEN_16_9 = (1<<10),
MODE_L3_GEN_4_3 = (1<<11),
MODE_L3_512_COL = (1<<12),
MODE_L3_384_COL = (1<<13),
MODE_L3_320_COL = (1<<14),
MODE_L3_256_COL = (1<<15),
MODE_L3_240x360 = (1<<16),
MODE_L4_GEN_4_3 = (1<<17),
MODE_L4_512_COL = (1<<18),
MODE_L4_384_COL = (1<<19),
MODE_L4_320_COL = (1<<20),
MODE_L4_256_COL = (1<<21),
MODE_L5_GEN_4_3 = (1<<22),
MODE_L5_512_COL = (1<<23),
MODE_L5_384_COL = (1<<24),
MODE_L5_320_COL = (1<<25),
MODE_L5_256_COL = (1<<26),
} mode_flags;
typedef struct {
char name[10];
HDMI_Video_Type vic:5;
alt_u16 h_active:11;
alt_u16 v_active;
alt_u16 h_total;
alt_u8 h_total_adj:5;
alt_u16 v_total:11;
alt_u8 h_backporch;
alt_u8 v_backporch;
alt_u8 h_synclen;
alt_u8 v_synclen;
alt_u8 sampler_phase;
video_type type:5;
video_group group:3;
mode_flags flags;
} mode_data_t;
#define VIDEO_MODES_DEF { \
/* 240p modes */ \
{ "1600x240", HDMI_Unknown, 1600, 240, 2046, 0, 262, 202, 15, 150, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "1280x240", HDMI_Unknown, 1280, 240, 1560, 0, 262, 170, 15, 72, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "960x240", HDMI_Unknown, 960, 240, 1170, 0, 262, 128, 15, 54, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "512x240", HDMI_Unknown, 512, 240, 682, 0, 262, 77, 14, 50, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL) }, \
{ "384x240", HDMI_Unknown, 384, 240, 512, 0, 262, 59, 14, 37, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_L2_384_COL | MODE_L3_384_COL | MODE_L4_384_COL | MODE_L5_384_COL) }, \
{ "320x240", HDMI_Unknown, 320, 240, 426, 0, 262, 49, 14, 31, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
{ "256x240", HDMI_Unknown, 256, 240, 341, 0, 262, 39, 14, 25, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
{ "240p", HDMI_240p60, 720, 240, 858, 0, 262, 57, 15, 62, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
/* 288p modes */ \
{ "1600x240L", HDMI_Unknown, 1600, 240, 2046, 0, 312, 202, 41, 150, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "1280x288", HDMI_Unknown, 1280, 288, 1560, 0, 312, 170, 15, 72, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "960x288", HDMI_Unknown, 960, 288, 1170, 0, 312, 128, 15, 54, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "512x240LB", HDMI_Unknown, 512, 240, 682, 0, 312, 77, 41, 50, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL) }, \
{ "384x240LB", HDMI_Unknown, 384, 240, 512, 0, 312, 59, 41, 37, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_L2_384_COL | MODE_L3_384_COL | MODE_L4_384_COL | MODE_L5_384_COL) }, \
{ "320x240LB", HDMI_Unknown, 320, 240, 426, 0, 312, 49, 41, 31, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
{ "256x240LB", HDMI_Unknown, 256, 240, 341, 0, 312, 39, 41, 25, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
{ "288p", HDMI_288p50, 720, 288, 864, 0, 312, 69, 19, 63, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
/* 360p: GBI */ \
{ "480x360", HDMI_Unknown, 480, 360, 600, 0, 375, 63, 10, 38, 3, DEFAULT_SAMPLER_PHASE, VIDEO_EDTV, GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
{ "240x360", HDMI_Unknown, 256, 360, 300, 0, 375, 24, 10, 18, 3, DEFAULT_SAMPLER_PHASE, VIDEO_EDTV, GROUP_384P, (MODE_L2_240x360 | MODE_L3_240x360) }, \
/* 384p: Sega Model 2 (real vtotal=423, avoid collision with PC88/98 and VGA400p) */ \
{ "384p", HDMI_Unknown, 496, 384, 640, 0, 408, 50, 29, 62, 3, DEFAULT_SAMPLER_PHASE, VIDEO_EDTV, GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
/* 400p line3x */ \
{ "1600x400", HDMI_Unknown, 1600, 400, 2000, 0, 449, 120, 34, 240, 2, DEFAULT_SAMPLER_PHASE, VIDEO_PC, GROUP_384P, (MODE_L3_GEN_16_9) }, \
/* 720x400@70Hz, VGA Mode 3+/7+ */ \
{ "720x400", HDMI_Unknown, 720, 400, 900, 0, 449, 64, 34, 96, 2, DEFAULT_SAMPLER_PHASE, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2) }, \
/* 640x400@70Hz, VGA Mode 13h */ \
{ "640x400", HDMI_Unknown, 640, 400, 800, 0, 449, 48, 34, 96, 2, DEFAULT_SAMPLER_PHASE, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2) }, \
/* 384p: X68k @ 24kHz */ \
{ "640x384", HDMI_Unknown, 640, 384, 800, 0, 492, 48, 63, 96, 2, DEFAULT_SAMPLER_PHASE, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
/* ~525-line modes */ \
{ "480i", HDMI_480i60, 720, 240, 858, 0, 525, 57, 15, 62, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_480I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \
{ "480p", HDMI_480p60, 720, 480, 858, 0, 525, 60, 30, 62, 6, DEFAULT_SAMPLER_PHASE, VIDEO_EDTV, GROUP_480P, (MODE_PT | MODE_L2) }, \
/* 480p PSP in-game */ \
{ "480x272", HDMI_480p60_16x9, 480, 272, 858, 0, 525, 177,134, 62, 6, DEFAULT_SAMPLER_PHASE, VIDEO_EDTV, GROUP_480P, (MODE_PT | MODE_L2_480x272) }, \
{ "640x480", HDMI_640x480p60, 640, 480, 800, 0, 525, 48, 33, 96, 2, DEFAULT_SAMPLER_PHASE, VIDEO_PC, GROUP_480P, (MODE_PT | MODE_L2) }, \
/* X68k @ 31kHz */ \
{ "640x512", HDMI_Unknown, 640, 512, 800, 0, 568, 48, 28, 96, 2, DEFAULT_SAMPLER_PHASE, VIDEO_PC, GROUP_480P, (MODE_PT | MODE_L2) }, \
/* ~625-line modes */ \
{ "576i", HDMI_576i50, 720, 288, 864, 0, 625, 69, 19, 63, 3, DEFAULT_SAMPLER_PHASE, VIDEO_SDTV, GROUP_480I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \
{ "576p", HDMI_576p50, 720, 576, 864, 0, 625, 68, 39, 64, 5, DEFAULT_SAMPLER_PHASE, VIDEO_EDTV, GROUP_480P, (MODE_PT | MODE_L2) }, \
{ "800x600", HDMI_Unknown, 800, 600, 1056, 0, 628, 88, 23, 128, 4, DEFAULT_SAMPLER_PHASE, VIDEO_PC, GROUP_NONE, MODE_PT }, \
/* 720p modes */ \
{ "720p_50", HDMI_720p50, 1280, 720, 1980, 0, 750, 220, 20, 40, 5, DEFAULT_SAMPLER_PHASE, (VIDEO_HDTV | VIDEO_PC), GROUP_NONE, MODE_PT }, \
{ "720p_60", HDMI_720p60, 1280, 720, 1650, 0, 750, 220, 20, 40, 5, DEFAULT_SAMPLER_PHASE, (VIDEO_HDTV | VIDEO_PC), GROUP_NONE, MODE_PT }, \
/* VESA XGA and SXGA modes */ \
{ "1024x768", HDMI_Unknown, 1024, 768, 1344, 0, 806, 160, 29, 136, 6, DEFAULT_SAMPLER_PHASE, VIDEO_PC, GROUP_NONE, MODE_PT }, \
{ "1280x1024", HDMI_Unknown, 1280, 1024, 1688, 0, 1066, 248, 38, 112, 3, DEFAULT_SAMPLER_PHASE, VIDEO_PC, GROUP_NONE, MODE_PT }, \
/* PS2 GSM 960i mode */ \
{ "640x960i", HDMI_Unknown, 640, 480, 800, 0, 1050, 48, 33, 96, 2, DEFAULT_SAMPLER_PHASE, VIDEO_EDTV, GROUP_1080I, (MODE_PT | MODE_L2 | MODE_INTERLACED) }, \
/* 1080i/p modes */ \
{ "1080i_50", HDMI_1080i50, 1920, 540, 2640, 0, 1125, 148, 15, 44, 5, DEFAULT_SAMPLER_PHASE, (VIDEO_HDTV | VIDEO_PC), GROUP_1080I, (MODE_PT | MODE_L2 | MODE_INTERLACED) }, \
{ "1080i_60", HDMI_1080i60, 1920, 540, 2200, 0, 1125, 148, 16, 44, 5, DEFAULT_SAMPLER_PHASE, (VIDEO_HDTV | VIDEO_PC), GROUP_1080I, (MODE_PT | MODE_L2 | MODE_INTERLACED) }, \
{ "1080p_50", HDMI_1080p50, 1920, 1080, 2640, 0, 1125, 148, 36, 44, 5, DEFAULT_SAMPLER_PHASE, (VIDEO_HDTV | VIDEO_PC), GROUP_NONE, MODE_PT }, \
{ "1080p_60", HDMI_1080p60, 1920, 1080, 2200, 0, 1125, 148, 36, 44, 5, DEFAULT_SAMPLER_PHASE, (VIDEO_HDTV | VIDEO_PC), GROUP_NONE, MODE_PT }, \
/* VESA UXGA with 49 H.backporch cycles exchanged for H.synclen */ \
{ "1600x1200", HDMI_Unknown, 1600, 1200, 2160, 0, 1250, 255, 46, 241, 3, DEFAULT_SAMPLER_PHASE, VIDEO_PC, GROUP_NONE, MODE_PT }, \
}
#define VIDEO_MODES_SIZE (sizeof((mode_data_t[])VIDEO_MODES_DEF))
#define VIDEO_MODES_CNT (sizeof((mode_data_t[])VIDEO_MODES_DEF)/sizeof(mode_data_t))
alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, alt_u8 h_syncinlen);
#endif /* VIDEO_MODES_H_ */