Update to Quartus 16.1.

ip/altera_epcq_controller_mod/altera_epcq_controller_hw.tcl

@@ -34,7 +34,7 @@ package require -exact qsys 14.1
 # 
 set_module_property DESCRIPTION "This component is a serial flash controller which allows user to access Altera EPCQ devices"
 set_module_property NAME altera_epcq_controller_core
-set_module_property VERSION 15.1
+set_module_property VERSION 16.1
 set_module_property INTERNAL true
 set_module_property OPAQUE_ADDRESS_MAP true
 set_module_property AUTHOR "Altera Corporation"

ip/altera_epcq_controller_mod/altera_epcq_controller_sw.tcl

@@ -22,7 +22,7 @@ create_driver altera_epcq_controller_mod_driver
 set_sw_property hw_class_name altera_epcq_controller_mod
 
 # The version of this driver
-set_sw_property version 15.1
+set_sw_property version 14.1
 
 # This driver may be incompatible with versions of hardware less
 # than specified below. Updates to hardware and device drivers

ip/altera_epcq_controller_mod/altera_epcq_controller_wrapper_hw.tcl

@@ -20,7 +20,7 @@ package require -exact altera_terp 1.0
 # 
 set_module_property DESCRIPTION "This component is a serial flash controller which allows user to access Altera EPCQ devices"
 set_module_property NAME altera_epcq_controller_mod
-set_module_property VERSION 15.1
+set_module_property VERSION 16.1
 set_module_property INTERNAL false
 set_module_property OPAQUE_ADDRESS_MAP true
 set_module_property GROUP "Basic Functions/Configuration and Programming"

ip/altera_nios_custom_instr_endianconverter_qsys/endianconverter_qsys_hw.tcl

@@ -34,7 +34,7 @@ package require -exact sopc 10.1
 # | module altera_nios_custom_instr_endian_converter
 # | 
 set_module_property NAME altera_nios_custom_instr_endianconverter
-set_module_property VERSION "__VERSION_SHORT__"
+set_module_property VERSION 16.1
 set_module_property INTERNAL false
 set_module_property GROUP "Custom Instruction Modules"
 set_module_property AUTHOR "Altera Corporation"

ip/i2c_opencores/i2c_opencores_hw.tcl

@@ -20,7 +20,7 @@ package require -exact qsys 13.1
 # 
 set_module_property DESCRIPTION "I2C Master Peripheral from opencores.org, plus SPI master (CPOL=1, CPHA=1) functionality using the same bus."
 set_module_property NAME i2c_opencores
-set_module_property VERSION 13.0
+set_module_property VERSION 16.1
 set_module_property INTERNAL false
 set_module_property OPAQUE_ADDRESS_MAP true
 set_module_property GROUP "Interface Protocols/Serial"

ip/nios2_hw_crc/nios2_hw_crc32_hw.tcl

@@ -20,7 +20,7 @@ package require -exact qsys 15.1
 # 
 set_module_property DESCRIPTION ""
 set_module_property NAME nios2_hw_crc32
-set_module_property VERSION 1.0
+set_module_property VERSION 16.1
 set_module_property INTERNAL false
 set_module_property OPAQUE_ADDRESS_MAP true
 set_module_property GROUP "Custom Instruction Modules"

ossc.qsf

@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE15E22C8
 set_global_assignment -name TOP_LEVEL_ENTITY ossc
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03  MAY 17, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
+set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -186,7 +186,7 @@ set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
 
 set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
-set_global_assignment -name SMART_RECOMPILE OFF
+set_global_assignment -name SMART_RECOMPILE ON
 
 set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
 
@@ -217,6 +217,9 @@ set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 50%
 #set_location_assignment PLL_1 -to "scanconverter:scanconverter_inst|pll_2x:pll_linedouble|altpll:altpll_component|pll_2x_altpll:auto_generated|pll1"
 
 
+
+
+
 set_global_assignment -name VERILOG_FILE rtl/videogen.v
 set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
 set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v
@@ -229,7 +232,4 @@ set_global_assignment -name QIP_FILE rtl/pll_2x.qip
 set_global_assignment -name QIP_FILE rtl/pll_3x.qip
 set_global_assignment -name QIP_FILE rtl/pll_3x_lowfreq.qip
 set_global_assignment -name CDF_FILE output_files/Chain1.cdf
-
-
-
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

rtl/linebuf.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "15.1"
+set_global_assignment -name IP_TOOL_VERSION "16.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "linebuf.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf_inst.v"]

rtl/linebuf.v

@@ -14,22 +14,22 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+//Copyright (C) 2016  Intel Corporation. All rights reserved.
-//Your use of Altera Corporation's design tools, logic functions 
+//Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and its AMPP partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
-//to the terms and conditions of the Altera Program License 
+//to the terms and conditions of the Intel Program License 
-//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Altera MegaCore Function License Agreement, or other 
+//the Intel MegaCore Function License Agreement, or other 
 //applicable license agreement, including, without limitation, 
 //that your use is for the sole purpose of programming logic 
-//devices manufactured by Altera and sold by Altera or its 
+//devices manufactured by Intel and sold by Intel or its 
 //authorized distributors.  Please refer to the applicable 
 //agreement for further details.
 

rtl/pll_2x.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "15.1"
+set_global_assignment -name IP_TOOL_VERSION "16.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_bb.v"]

rtl/pll_2x.v

@@ -9,27 +9,27 @@
 // 			altpll
 //
 // Simulation Library Files(s):
-// 			altera_mf
+// 			
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+//Copyright (C) 2016  Intel Corporation. All rights reserved.
-//Your use of Altera Corporation's design tools, logic functions 
+//Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and its AMPP partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
-//to the terms and conditions of the Altera Program License 
+//to the terms and conditions of the Intel Program License 
-//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Altera MegaCore Function License Agreement, or other 
+//the Intel MegaCore Function License Agreement, or other 
 //applicable license agreement, including, without limitation, 
 //that your use is for the sole purpose of programming logic 
-//devices manufactured by Altera and sold by Altera or its 
+//devices manufactured by Intel and sold by Intel or its 
 //authorized distributors.  Please refer to the applicable 
 //agreement for further details.
 
@@ -317,5 +317,4 @@ endmodule
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.bsf FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_inst.v FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v TRUE
-// Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON

rtl/pll_3x.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "15.1"
+set_global_assignment -name IP_TOOL_VERSION "16.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_3x.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_3x.ppf"]

rtl/pll_3x.v

@@ -9,27 +9,27 @@
 // 			altpll
 //
 // Simulation Library Files(s):
-// 			altera_mf
+// 			
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+//Copyright (C) 2016  Intel Corporation. All rights reserved.
-//Your use of Altera Corporation's design tools, logic functions 
+//Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and its AMPP partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
-//to the terms and conditions of the Altera Program License 
+//to the terms and conditions of the Intel Program License 
-//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Altera MegaCore Function License Agreement, or other 
+//the Intel MegaCore Function License Agreement, or other 
 //applicable license agreement, including, without limitation, 
 //that your use is for the sole purpose of programming logic 
-//devices manufactured by Altera and sold by Altera or its 
+//devices manufactured by Intel and sold by Intel or its 
 //authorized distributors.  Please refer to the applicable 
 //agreement for further details.
 
@@ -345,5 +345,4 @@ endmodule
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.bsf FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_inst.v FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON

rtl/pll_3x_lowfreq.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "15.1"
+set_global_assignment -name IP_TOOL_VERSION "16.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_3x_lowfreq.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_3x_lowfreq_bb.v"]

rtl/pll_3x_lowfreq.v

@@ -9,27 +9,27 @@
 // 			altpll
 //
 // Simulation Library Files(s):
-// 			altera_mf
+// 			
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
+// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+//Copyright (C) 2016  Intel Corporation. All rights reserved.
-//Your use of Altera Corporation's design tools, logic functions 
+//Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and its AMPP partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
-//to the terms and conditions of the Altera Program License 
+//to the terms and conditions of the Intel Program License 
-//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Altera MegaCore Function License Agreement, or other 
+//the Intel MegaCore Function License Agreement, or other 
 //applicable license agreement, including, without limitation, 
 //that your use is for the sole purpose of programming logic 
-//devices manufactured by Altera and sold by Altera or its 
+//devices manufactured by Intel and sold by Intel or its 
 //authorized distributors.  Please refer to the applicable 
 //agreement for further details.
 
@@ -373,5 +373,4 @@ endmodule
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq.bsf FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq_inst.v FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq_bb.v TRUE
-// Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON

software/sys_controller/Makefile

@@ -194,7 +194,7 @@ APP_CFLAGS_UNDEFINED_SYMBOLS :=
 APP_CFLAGS_OPTIMIZATION := -Os
 APP_CFLAGS_DEBUG_LEVEL :=
 APP_CFLAGS_WARNINGS := -Wall -Wno-unused-but-set-variable -Wno-unused-variable -Wno-unused-function
-APP_CFLAGS_USER_FLAGS := -fdata-sections -ffunction-sections -fshort-enums
+APP_CFLAGS_USER_FLAGS := -fdata-sections -ffunction-sections -fshort-enums -fgnu89-inline
 
 APP_ASFLAGS_USER :=
 APP_LDFLAGS_USER := -Wl,--gc-sections

software/sys_controller_bsp/HAL/inc/sys/alt_flash.h

@@ -137,9 +137,10 @@ static __inline__ int __attribute__ ((always_inline)) alt_erase_flash_block(
   int ret_code;
   ret_code = fd->erase_block( fd, offset );
   
+/* remove dcache_flush call for FB330552  
   if(!ret_code)
       alt_dcache_flush((alt_u8*)fd->base_addr + offset, length);
-
+*/
   return ret_code;
 }
 
@@ -166,9 +167,10 @@ static __inline__ int __attribute__ ((always_inline)) alt_write_flash_block(
   int ret_code;
   ret_code = fd->write_block( fd, block_offset, data_offset, data, length );
 
+/* remove dcache_flush call for FB330552  
   if(!ret_code)
       alt_dcache_flush((alt_u8*)fd->base_addr + data_offset, length);
-
+*/
   return ret_code;
 }
 

software/sys_controller_bsp/HAL/inc/sys/alt_log_printf.h

@@ -244,7 +244,12 @@
     void alt_log_write(const void *ptr, size_t len);
     
     /* extern all global variables */
-    extern volatile alt_u32 alt_log_boot_on_flag;
+    /* CASE:368514 - The boot message flag is linked into the sdata section
+     * because if it is zero, it would otherwise be placed in the bss section.
+     * alt_log examines this variable before the BSS is cleared in the boot-up
+     * process. 
+     */
+    extern volatile alt_u32 alt_log_boot_on_flag __attribute__ ((section (".sdata")));
     extern volatile alt_u8 alt_log_write_on_flag;
     extern volatile alt_u8 alt_log_sys_clk_on_flag;
     extern volatile alt_u8 alt_log_jtag_uart_alarm_on_flag;

software/sys_controller_bsp/HAL/src/alt_exception_entry.S

@@ -193,18 +193,44 @@ alt_exception:
          * instruction that caused the exception is written in r2, which these
          * handlers will utilize.
          */
-        stw   ea,  72(sp)  /* Don't re-issue */
+        stw ea, 72(sp) /* EA is PC+4 so will skip over instruction causing exception */
-        
+
 #ifdef NIOS2_CDX_PRESENT
-        mov.n   r4, ea
+        mov.n r4, ea            /* EA contains PC+4 of instruction that caused the exception */
-        subi.n   r4, r4, 4 
+        subi.n r4, r4, 4        /* Calculate PC */
-        ldhu.n  r2, 0(r4)
+        ldhu.n r2, 0(r4)        /* Load least-significant 16 bits of instruction */
-        ldhu.n  r3, 2(r4)
+        andi r5, r2, 0x7        /* Mask off all bits except the 3 most-significant bits of OP field */
-        slli.n  r3, r3, 16
+
-        or.n    r2, r2, r3 /* Instruction that caused exception */
+        /*
-#else
+         * These instructions compare the MSB 3 bits of OP to 0x1, 0x3, and 0x5
-        ldw   r2, -4(ea)   /* Instruction that caused exception */
+         * which is where all the 16-bit instructions live.
+         */
+        subi.n r5, r5, 1
+        beqz.n r5, .Lunknown_16bit
+        subi.n r5, r5, 2
+        beqz.n r5, .Lunknown_16bit
+        subi.n r5, r5, 2
+        beqz.n r5, .Lunknown_16bit
+
+.Lunknown_32bit:
+        stw ea, 72(sp) /* EA is PC+4 so will skip over instruction causing exception */
+
+        /* Load most-significant 16 bits of instruction */
+        ldhu.n r3, 2(r4)
+        slli.n r3, r3, 16
+        or.n r2, r2, r3 /* 32-bit instruction value that caused exception */
+        br.n .Lunknown_inst_loaded
+
+.Lunknown_16bit:
+        addi.n r4, r4, 2 /* Need PC+2 to skip over instruction causing exception */
+        stw r4, 72(sp)
+
+#else /* CDX is not Enabled and all instructions are 32bits */
+        ldw r2, -4(ea) /* Instruction value that caused exception */
 #endif
+
+.Lunknown_inst_loaded:
+
         /*
          * Other exception handling code, if enabled, will be linked here.
          * This includes unimplemted (multiply/divide) instruction support

software/sys_controller_bsp/HAL/src/alt_load.c

@@ -35,17 +35,28 @@
 
 /*
  * Linker defined symbols.
+   These used to be
+ *    extern alt_u32 __flash_rwdata_start;
+ *    extern alt_u32 __ram_rwdata_start;
+ *    extern alt_u32 __ram_rwdata_end;
+ * but that results in a fatal error when compiling -mgpopt=global
+ * because gcc assumes they are normal C variables in .sdata
+ * and therefore addressable from gp using a 16-bit offset,
+ * when in fact they are special values defined by linker.x
+ * and located nowhere near .sdata. 
+ * Specifying __attribute__((section(".data"))) will force these
+ * in .data. (CASE:258384.)
  */
 
-extern alt_u32 __flash_rwdata_start; 
+extern alt_u32 __flash_rwdata_start __attribute__((section(".data")));
-extern alt_u32 __ram_rwdata_start;
+extern alt_u32 __ram_rwdata_start __attribute__((section(".data")));
-extern alt_u32 __ram_rwdata_end;
+extern alt_u32 __ram_rwdata_end __attribute__((section(".data")));
-extern alt_u32 __flash_rodata_start; 
+extern alt_u32 __flash_rodata_start __attribute__((section(".data")));
-extern alt_u32 __ram_rodata_start;
+extern alt_u32 __ram_rodata_start __attribute__((section(".data")));
-extern alt_u32 __ram_rodata_end;
+extern alt_u32 __ram_rodata_end __attribute__((section(".data")));
-extern alt_u32 __flash_exceptions_start; 
+extern alt_u32 __flash_exceptions_start __attribute__((section(".data")));  
-extern alt_u32 __ram_exceptions_start;
+extern alt_u32 __ram_exceptions_start __attribute__((section(".data")));
-extern alt_u32 __ram_exceptions_end;
+extern alt_u32 __ram_exceptions_end __attribute__((section(".data")));
 
 /*
  * alt_load() is called when the code is executing from flash. In this case

software/sys_controller_bsp/HAL/src/alt_log_printf.c

@@ -52,13 +52,13 @@ char alt_log_write_buf[ALT_LOG_WRITE_ECHO_LEN+2];
 /* global variables for all 'on' flags */
 
 /* 
- * The boot message flag is linked into the data (rwdata) section
+ * CASE:368514 - The boot message flag is linked into the sdata section
  * because if it is zero, it would otherwise be placed in the bss section.
  * alt_log examines this variable before the BSS is cleared in the boot-up
  * process.
  */
 volatile alt_u32 alt_log_boot_on_flag \
-  __attribute__ ((section (".data"))) = ALT_LOG_BOOT_ON_FLAG_SETTING;
+  __attribute__ ((section (".sdata"))) = ALT_LOG_BOOT_ON_FLAG_SETTING;
 
 volatile alt_u8 alt_log_write_on_flag = ALT_LOG_WRITE_ON_FLAG_SETTING;
 

software/sys_controller_bsp/Makefile

@@ -93,12 +93,12 @@ OBJ_DIR := ./obj
 
 # This following VERSION comment indicates the version of the tool used to 
 # generate this makefile. A makefile variable is provided for VERSION as well. 
-# ACDS_VERSION: 15.1
+# ACDS_VERSION: 16.1
-ACDS_VERSION := 15.1
+ACDS_VERSION := 16.1
 
 # This following BUILD_NUMBER comment indicates the build number of the tool 
 # used to generate this makefile. 
-# BUILD_NUMBER: 185
+# BUILD_NUMBER: 196
 
 SETTINGS_FILE := settings.bsp
 SOPC_FILE := ../../sys.sopcinfo

software/sys_controller_bsp/mem_init.mk

@@ -150,12 +150,12 @@ flash2dat_extra_args = $(mem_pad_flag) $(mem_reloc_input_flag)
 
 # This following VERSION comment indicates the version of the tool used to 
 # generate this makefile. A makefile variable is provided for VERSION as well. 
-# ACDS_VERSION: 15.1
+# ACDS_VERSION: 16.1
-ACDS_VERSION := 15.1
+ACDS_VERSION := 16.1
 
 # This following BUILD_NUMBER comment indicates the build number of the tool 
 # used to generate this makefile. 
-# BUILD_NUMBER: 185
+# BUILD_NUMBER: 196
 
 # Optimize for simulation
 SIM_OPTIMIZE ?= 0

software/sys_controller_bsp/public.mk

@@ -77,12 +77,12 @@ ALT_CPPFLAGS += -pipe
 
 # This following VERSION comment indicates the version of the tool used to 
 # generate this makefile. A makefile variable is provided for VERSION as well. 
-# ACDS_VERSION: 15.1
+# ACDS_VERSION: 16.1
-ACDS_VERSION := 15.1
+ACDS_VERSION := 16.1
 
 # This following BUILD_NUMBER comment indicates the build number of the tool 
 # used to generate this makefile. 
-# BUILD_NUMBER: 185
+# BUILD_NUMBER: 196
 
 # Qsys--generated SOPCINFO file. Required for resolving node instance ID's with 
 # design component names. 
@@ -247,6 +247,18 @@ ALT_CPPFLAGS += -DSMALL_C_LIB
 # SOPC_SYSID_FLAG in public.mk. none 
 # setting hal.enable_sopc_sysid_check is true
 
+# C/C++ compiler to generate (do not generate) GP-relative accesses. 'none' 
+# tells the compilter not to generate GP-relative accesses. 'local' will 
+# generate GP-relative accesses for small data objects that are not external, 
+# weak, or uninitialized common symbols. Also use GP-relative addressing for 
+# objects that have been explicitly placed in a small data section via a 
+# section attribute. provides the default set of debug symbols typically 
+# required to debug a typical application. 'global' is same as 'local' but also 
+# generate GP-relative accesses for small data objects that are external, weak, 
+# or common. none 
+# setting hal.make.cflags_mgpopt is -mgpopt=global
+ALT_CFLAGS += -mgpopt=global
+
 # Enable BSP generation to query if SOPC system is big endian. If true ignores 
 # export of 'ALT_CFLAGS += -meb' to public.mk if big endian system. none 
 # setting hal.make.ignore_system_derived.big_endian is false

software/sys_controller_bsp/settings.bsp

@@ -2,8 +2,8 @@
 <sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
         <BspType>hal</BspType>
         <BspVersion>default</BspVersion>
-        <BspGeneratedTimeStamp>Oct 30, 2016 9:24:15 PM</BspGeneratedTimeStamp>
+        <BspGeneratedTimeStamp>Dec 13, 2016 8:52:43 PM</BspGeneratedTimeStamp>
-        <BspGeneratedUnixTimeStamp>1477855455847</BspGeneratedUnixTimeStamp>
+        <BspGeneratedUnixTimeStamp>1481655163358</BspGeneratedUnixTimeStamp>
         <BspGeneratedLocation>./</BspGeneratedLocation>
         <BspSettingsFile>settings.bsp</BspSettingsFile>
         <SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
@@ -77,7 +77,7 @@
                 <Value>1</Value>
                 <DefaultValue>0</DefaultValue>
                 <DestinationFile>none</DestinationFile>
-                <Description>Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory.</Description>
+                <Description>Enables the alt_load() facility. The alt_load() facility copies data sections (.rodata, .rwdata, or .exceptions) from boot memory to RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory.</Description>
                 <Restrictions>This setting is typically false if an external bootloader (e.g. flash bootloader) is present.</Restrictions>
                 <Enabled>false</Enabled>
                 <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
@@ -538,6 +538,18 @@
                 <Enabled>false</Enabled>
                 <Group>none</Group>
         </Setting>
+        <Setting>
+                <SettingName>hal.make.cflags_mgpopt</SettingName>
+                <Identifier>CFLAGS_MGPOPT</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>-mgpopt=global</Value>
+                <DefaultValue>-mgpopt=global</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>C/C++ compiler to generate (do not generate) GP-relative accesses. 'none' tells the compilter not to generate GP-relative accesses. 'local' will generate GP-relative accesses for small data objects that are not external, weak, or uninitialized common symbols. Also use GP-relative addressing for objects that have been explicitly placed in a small data section via a section attribute. provides the default set of debug symbols typically required to debug a typical application. 'global' is same as 'local' but also generate GP-relative accesses for small data objects that are external, weak, or common.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
         <Setting>
                 <SettingName>hal.make.ignore_system_derived.sopc_system_id</SettingName>
                 <Identifier>none</Identifier>