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simplify timing constraints

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marqs committed 2018-03-07 09:21:19 +02:00
1 parent bd1d58660c
commit 0ab31b30b4
8 files changed
+449 -309
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software/sys_controller_bsp/settings.bsp
+2 -2
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@@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Feb 24, 2018 7:18:24 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1519492704534</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>Mar 6, 2018 11:46:21 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1520372781076</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>