adapt review comments

* automate coast enable/disable based on sync type
* move glitch filter under sync menu

software/sys_controller/av_controller.c

@@ -68,7 +68,8 @@ extern char target_profile_name[USERDATA_NAME_LEN+1];
 
 tvp_input_t target_tvp;
 tvp_sync_input_t target_tvp_sync;
-alt_u8 target_type;
+video_format target_format;
+video_type target_type;
 alt_u8 update_cur_vm;
 static alt_u8 glitch_dev_ctr;   // "Sync glitch filt": consecutive deviating status reads while locked
 
@@ -421,7 +422,7 @@ status_t get_status(tvp_sync_input_t syncinput)
             status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
         }
 
-        if (memcmp(&tc, &cm.cc, offsetof(avconfig_t, sl_mode)) || (update_cur_vm == 1) || (tc.pc_sog_coast != cm.cc.pc_sog_coast))
+        if (memcmp(&tc, &cm.cc, offsetof(avconfig_t, sl_mode)) || (update_cur_vm == 1))
             status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
 
         cm.totlines = totlines;
@@ -744,11 +745,6 @@ void program_mode()
                      (alt_8)(cm.cc.clamp_offset-SIGNED_NUMVAL_ZERO),
                      vmode_changed);
 
-    // tvp_source_setup() disables the internal coast signal for PC-type presets, which is correct for RGBHV but
-    // leaves the H-PLL exposed to vsync serration pulses on sync-on-green / composite-sync inputs. Keep coast
-    // enabled for those when the option is set (needed e.g. for 13W3 workstation displays).
-    if ((target_type & VIDEO_PC) && cm.cc.pc_sog_coast && ((target_tvp_sync <= TVP_SOG3) || (target_tvp_sync >= TVP_CS_A)))
-        tvp_set_coast_enable(1);
     set_lpf(cm.cc.video_lpf);
     set_csc(cm.cc.ypbpr_cs);
 
@@ -1070,7 +1066,6 @@ int main(int argc, char **argv, char **envp)
 {
     ths_input_t target_ths = 0;
     pcm_input_t target_pcm = 0;
-    video_format target_format = 0;
 
     status_t status;
 

software/sys_controller/ic_drivers/tvp7002/tvp7002.c

@@ -180,13 +180,6 @@ inline void tvp_set_hpllcoast(alt_u8 pre, alt_u8 post)
     tvp_writereg(TVP_HPLLPOSTCOAST, post);
 }
 
-// Enable/disable the internal H-PLL coast signal (MISCCTRL4 bit 2, "Coast Dis")
-void tvp_set_coast_enable(alt_u8 enable)
-{
-    alt_u8 val = tvp_readreg(TVP_MISCCTRL4) & 0xFB;
-    tvp_writereg(TVP_MISCCTRL4, val | (enable ? 0x00 : 0x04));
-}
-
 inline void tvp_set_linelen_tol(alt_u8 val) {
     tvp_writereg(TVP_LINELENTOL, val);
 }
@@ -402,22 +395,6 @@ void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 pixs_per_li
     // Clamp and ALC
     tvp_set_clamp_alc(type, clamp_ref_offset, clamp_user_offset, 1);
 
-    // Setup Macrovision stripper and H-PLL coast signal.
-    // Coast needs to be enabled when HSYNC is missing during VSYNC. RGBHV mode cannot use it, so turn off the internal signal for this mode.
-    // Macrovision stripper filters out glitches and serration pulses that may occur outside of sync window (HSYNC_lead +- TVP_MVSWIDTH*37ns). Enabled for all inputs.
-    switch (type) {
-    case VIDEO_PC:
-        tvp_writereg(TVP_MISCCTRL4, 0x0D);
-        break;
-    //case VIDEO_LDTV:
-    case VIDEO_SDTV:
-    case VIDEO_EDTV:
-    case VIDEO_HDTV:
-    default:
-        tvp_writereg(TVP_MISCCTRL4, 0x09);
-        break;
-    }
-
     tvp_setup_hpll(h_samplerate, pixs_per_line, refclks_per_line, plldivby2);
 }
 
@@ -465,6 +442,14 @@ void tvp_source_sel(tvp_input_t input, tvp_sync_input_t syncinput, video_format
     else
         tvp_writereg(TVP_SYNCBYPASS, 0x00);
 
+    // Setup Macrovision stripper and H-PLL coast signal.
+    // Coast needs to be enabled when HSYNC is missing during VSYNC. RGBHV mode cannot use it, so turn off the internal signal for this mode.
+    // Macrovision stripper filters out glitches and serration pulses that may occur outside of sync window (HSYNC_lead +- TVP_MVSWIDTH*37ns). Enabled for all inputs.
+    if (fmt == FORMAT_RGBHV)
+        tvp_writereg(TVP_MISCCTRL4, 0x0D);
+    else
+        tvp_writereg(TVP_MISCCTRL4, 0x09);
+
     //TODO:
     //TVP_ADCSETUP
 

software/sys_controller/ic_drivers/tvp7002/tvp7002.h

@@ -90,8 +90,6 @@ inline void tvp_powerup();
 
 inline void tvp_set_hpllcoast(alt_u8 pre, alt_u8 post);
 
-void tvp_set_coast_enable(alt_u8 enable);
-
 inline void tvp_set_linelen_tol(alt_u8 val);
 
 inline void tvp_set_ssthold(alt_u8 vsdetect_thold);

software/sys_controller/inc/avconfig.h

@@ -143,6 +143,7 @@ typedef struct {
     alt_u8 alc_v_filter;
     color_setup_t col;
     alt_u8 full_vs_bypass;
+    alt_u8 sync_glitch_filt;
 
     /* Audio settings */
     alt_u8 audio_dw_sampl;
@@ -159,8 +160,6 @@ typedef struct {
     alt_u8 full_tx_setup;
     alt_u8 av3_alt_rgb;
     avinput_t link_av;
-    alt_u8 pc_sog_coast;
-    alt_u8 sync_glitch_filt;
 } __attribute__((packed)) avconfig_t;
 
 int set_default_profile(int update_cc);

software/sys_controller/inc/firmware.h

@@ -24,7 +24,7 @@
 #include "sysconfig.h"
 
 #define FW_VER_MAJOR            1
-#define FW_VER_MINOR            22
+#define FW_VER_MINOR            23
 
 #ifdef OSDLANG_JP
 #define FW_SUFFIX              "j"

software/sys_controller/src/menu.c

@@ -189,6 +189,7 @@ MENU(menu_sync, P99_PROTECT({ \
     { "H-PLL Post-Coast",                       OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.post_coast,  OPT_NOWRAP, 0, PLL_COAST_MAX, lines_disp } } },
     { "ADC PLL BW",                             OPT_AVCONFIG_SELECTION, { .sel = { &tc.adc_pll_bw,  OPT_WRAP,   SETTING_ITEM(adc_pll_bw_desc) } } },
     { "FPGA PLL BW",                            OPT_AVCONFIG_SELECTION, { .sel = { &tc.fpga_pll_bw, OPT_WRAP,   SETTING_ITEM(fpga_pll_bw_desc) } } },
+    { "Sync glitch filt",                      OPT_AVCONFIG_SELECTION, { .sel = { &tc.sync_glitch_filt, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
 }))
 
 MENU(menu_lm, P99_PROTECT({ \
@@ -248,8 +249,6 @@ MENU(menu_compatibility, P99_PROTECT({ \
     { "Default HDMI VIC",                       OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.default_vic,     OPT_NOWRAP, 0, HDMI_1080p50, value_disp } } },
     { "Panasonic hack",                        OPT_AVCONFIG_SELECTION, { .sel = { &tc.panasonic_hack,   OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
     { "Disable PR2x",                          OPT_AVCONFIG_SELECTION, { .sel = { &tc.hdmi_pr2x_disable, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
-    { "PC SoG/CS coast",                       OPT_AVCONFIG_SELECTION, { .sel = { &tc.pc_sog_coast,     OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
-    { "Sync glitch filt",                      OPT_AVCONFIG_SELECTION, { .sel = { &tc.sync_glitch_filt, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
 }))
 
 MENU(menu_audio, P99_PROTECT({ \

software/sys_controller/src/userdata.c

@@ -144,8 +144,7 @@ const ude_item_map ude_profile_items[] = {
     UDE_ITEM(67, 120, tc.o480p_pbox),
     UDE_ITEM(68, 122, tc.hdmi_ar),
     UDE_ITEM(69, 122, tc.hdmi_pr2x_disable),
-    UDE_ITEM(70, 122, tc.pc_sog_coast),
-    UDE_ITEM(71, 122, tc.sync_glitch_filt),
+    UDE_ITEM(70, 123, tc.sync_glitch_filt),
 };
 
 int write_userdata(uint8_t entry) {