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update epcq_controller_mod to epcq_controller2

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marqs committed 2020-11-10 19:46:07 +02:00
1 parent 2a24eb8dd7
commit 238cf0b285
30 files changed
+9313 -11637
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software/sys_controller_bsp/system.h
+29 -29
View File
@@ -151,7 +151,7 @@
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_TIMER
#define __ALTERA_EPCQ_CONTROLLER_MOD
#define __ALTERA_EPCQ_CONTROLLER2
#define __ALTERA_NIOS2_GEN2
#define __ALTERA_NIOS_CUSTOM_INSTR_BITSWAP
#define __ALTERA_NIOS_CUSTOM_INSTR_ENDIANCONVERTER
@@ -196,43 +196,43 @@
/*
* epcq_controller_0_avl_csr configuration
* epcq_controller2_0_avl_csr configuration
*
*/
#define ALT_MODULE_CLASS_epcq_controller_0_avl_csr altera_epcq_controller_mod
#define EPCQ_CONTROLLER_0_AVL_CSR_BASE 0x20100
#define EPCQ_CONTROLLER_0_AVL_CSR_FLASH_TYPE "EPCS16"
#define EPCQ_CONTROLLER_0_AVL_CSR_IRQ 2
#define EPCQ_CONTROLLER_0_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
#define EPCQ_CONTROLLER_0_AVL_CSR_IS_EPCS 1
#define EPCQ_CONTROLLER_0_AVL_CSR_NAME "/dev/epcq_controller_0_avl_csr"
#define EPCQ_CONTROLLER_0_AVL_CSR_NUMBER_OF_SECTORS 32
#define EPCQ_CONTROLLER_0_AVL_CSR_PAGE_SIZE 256
#define EPCQ_CONTROLLER_0_AVL_CSR_SECTOR_SIZE 65536
#define EPCQ_CONTROLLER_0_AVL_CSR_SPAN 32
#define EPCQ_CONTROLLER_0_AVL_CSR_SUBSECTOR_SIZE 4096
#define EPCQ_CONTROLLER_0_AVL_CSR_TYPE "altera_epcq_controller_mod"
#define ALT_MODULE_CLASS_epcq_controller2_0_avl_csr altera_epcq_controller2
#define EPCQ_CONTROLLER2_0_AVL_CSR_BASE 0x20100
#define EPCQ_CONTROLLER2_0_AVL_CSR_FLASH_TYPE "EPCQ16"
#define EPCQ_CONTROLLER2_0_AVL_CSR_IRQ 2
#define EPCQ_CONTROLLER2_0_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
#define EPCQ_CONTROLLER2_0_AVL_CSR_IS_EPCS 0
#define EPCQ_CONTROLLER2_0_AVL_CSR_NAME "/dev/epcq_controller2_0_avl_csr"
#define EPCQ_CONTROLLER2_0_AVL_CSR_NUMBER_OF_SECTORS 32
#define EPCQ_CONTROLLER2_0_AVL_CSR_PAGE_SIZE 256
#define EPCQ_CONTROLLER2_0_AVL_CSR_SECTOR_SIZE 65536
#define EPCQ_CONTROLLER2_0_AVL_CSR_SPAN 64
#define EPCQ_CONTROLLER2_0_AVL_CSR_SUBSECTOR_SIZE 4096
#define EPCQ_CONTROLLER2_0_AVL_CSR_TYPE "altera_epcq_controller2"
/*
* epcq_controller_0_avl_mem configuration
* epcq_controller2_0_avl_mem configuration
*
*/
#define ALT_MODULE_CLASS_epcq_controller_0_avl_mem altera_epcq_controller_mod
#define EPCQ_CONTROLLER_0_AVL_MEM_BASE 0x800000
#define EPCQ_CONTROLLER_0_AVL_MEM_FLASH_TYPE "EPCS16"
#define EPCQ_CONTROLLER_0_AVL_MEM_IRQ -1
#define EPCQ_CONTROLLER_0_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define EPCQ_CONTROLLER_0_AVL_MEM_IS_EPCS 1
#define EPCQ_CONTROLLER_0_AVL_MEM_NAME "/dev/epcq_controller_0_avl_mem"
#define EPCQ_CONTROLLER_0_AVL_MEM_NUMBER_OF_SECTORS 32
#define EPCQ_CONTROLLER_0_AVL_MEM_PAGE_SIZE 256
#define EPCQ_CONTROLLER_0_AVL_MEM_SECTOR_SIZE 65536
#define EPCQ_CONTROLLER_0_AVL_MEM_SPAN 2097152
#define EPCQ_CONTROLLER_0_AVL_MEM_SUBSECTOR_SIZE 4096
#define EPCQ_CONTROLLER_0_AVL_MEM_TYPE "altera_epcq_controller_mod"
#define ALT_MODULE_CLASS_epcq_controller2_0_avl_mem altera_epcq_controller2
#define EPCQ_CONTROLLER2_0_AVL_MEM_BASE 0x800000
#define EPCQ_CONTROLLER2_0_AVL_MEM_FLASH_TYPE "EPCQ16"
#define EPCQ_CONTROLLER2_0_AVL_MEM_IRQ -1
#define EPCQ_CONTROLLER2_0_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define EPCQ_CONTROLLER2_0_AVL_MEM_IS_EPCS 0
#define EPCQ_CONTROLLER2_0_AVL_MEM_NAME "/dev/epcq_controller2_0_avl_mem"
#define EPCQ_CONTROLLER2_0_AVL_MEM_NUMBER_OF_SECTORS 32
#define EPCQ_CONTROLLER2_0_AVL_MEM_PAGE_SIZE 256
#define EPCQ_CONTROLLER2_0_AVL_MEM_SECTOR_SIZE 65536
#define EPCQ_CONTROLLER2_0_AVL_MEM_SPAN 2097152
#define EPCQ_CONTROLLER2_0_AVL_MEM_SUBSECTOR_SIZE 4096
#define EPCQ_CONTROLLER2_0_AVL_MEM_TYPE "altera_epcq_controller_mod"
/*