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Fix line3x 4:3 mode and VGA interlace detection

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marqs committed 2017-02-09 23:14:24 +02:00
1 parent 6e043ef577
commit 2c934c9dd0
7 files changed
+940 -927
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software/sys_controller/mem_init/sys_onchip_memory2_0.hex
+911 -911
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File diff suppressed because it is too large. Load diff
software/sys_controller/ossc/av_controller.c
+4 -4
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@@ -203,7 +203,7 @@ status_t get_status(tvp_input_t input, video_format format)
}
sync_active = tvp_check_sync(input, format);
vsyncmode = cm.sync_active ? (IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) >> 16) : 0;
vsyncmode = cm.sync_active ? ((IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) >> 16) & 0x3) : 0;
data1 = tvp_readreg(TVP_LINECNT1);
data2 = tvp_readreg(TVP_LINECNT2);
@@ -211,14 +211,14 @@ status_t get_status(tvp_input_t input, video_format format)
progressive = !!(data2 & (1<<5));
cm.macrovis = !!(data2 & (1<<6));
fpga_totlines = IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) & 0xffff;
fpga_totlines = (IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) >> 17) & 0x7ff;
// NOTE: "progressive" may not have correct value if H-PLL is not locked (!cm.sync_active)
if ((vsyncmode == 0x2) || (!cm.sync_active && (totlines < MIN_LINES_INTERLACED))) {
progressive = 1;
} else if ((vsyncmode == 0x1) && fpga_totlines > ((totlines-1)*2)) {
} else if ((vsyncmode == 0x1) && (fpga_totlines > 2*(totlines-1))) {
progressive = 0;
totlines = fpga_totlines; //ugly hack
totlines = fpga_totlines/2; //compensate skipped vsync
}
valid_linecnt = check_linecnt(progressive, totlines);
software/sys_controller_bsp/settings.bsp
+2 -2
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@@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Feb 7, 2017 10:49:51 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1486500591240</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>Feb 9, 2017 9:00:28 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1486666828834</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>