* R/G/B gain/offset controls added

* misc optimizations
This commit is contained in:
marqs committed 2016-08-20 15:54:28 +03:00
1 parent 827df7930f
commit 2dee0a2eb5
11 files changed
+956 -949

No files matched your search

+4 -1
View File
@@ -77,7 +77,10 @@ set_false_path -from pclk_3x_M1 -through $clkmuxnodes -to pclk_4x_M1
set_false_path -from [get_cells {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter:scanconverter_inst|lines_*}]
# Ignore paths from registers which are updated only at the end of hsync
set_false_path -from [get_cells {scanconverter:scanconverter_inst|vcnt_* scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx*}]
set_false_path -from [get_cells {scanconverter:scanconverter_inst|vcnt_* scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|HSYNC_start*}]
# Ignore paths to registers which do not drive critical logic
set_false_path -to [get_cells {scanconverter:scanconverter_inst|line_out_idx*}]
# Ignore following clock transfers
set_false_path -from [get_clocks pclk_2x] -to [get_clocks pclk_sdtv]