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* R/G/B gain/offset controls added
* misc optimizations
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@@ -77,7 +77,10 @@ set_false_path -from pclk_3x_M1 -through $clkmuxnodes -to pclk_4x_M1
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set_false_path -from [get_cells {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter:scanconverter_inst|lines_*}]
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# Ignore paths from registers which are updated only at the end of hsync
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set_false_path -from [get_cells {scanconverter:scanconverter_inst|vcnt_* scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx*}]
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set_false_path -from [get_cells {scanconverter:scanconverter_inst|vcnt_* scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|HSYNC_start*}]
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# Ignore paths to registers which do not drive critical logic
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set_false_path -to [get_cells {scanconverter:scanconverter_inst|line_out_idx*}]
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# Ignore following clock transfers
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set_false_path -from [get_clocks pclk_2x] -to [get_clocks pclk_sdtv]
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