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add support for v1.8 PCBs

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This commit is contained in:
marqs 2023-08-05 22:41:58 +03:00
parent a3a3304152
commit 2e1fdab16b
3 changed files with 25 additions and 22 deletions
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9
ossc.qsf
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@ -59,6 +59,8 @@ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_25 -to clk27
set_location_assignment PIN_99 -to hw_reset_n
set_location_assignment PIN_23 -to ir_rx
set_location_assignment PIN_126 -to cfg[1]
set_location_assignment PIN_127 -to cfg[0]
#============================================================
# TVP7002
@ -82,7 +84,7 @@ set_location_assignment PIN_89 -to TVP_PCLK_i
set_location_assignment PIN_76 -to TVP_B_i[0]
set_location_assignment PIN_90 -to TVP_HS_i
set_location_assignment PIN_91 -to TVP_VSYNC_i
set_location_assignment PIN_98 -to TVP_FID_i
set_location_assignment PIN_98 -to TVP_SOG_i
set_location_assignment PIN_72 -to TVP_G_i[7]
set_location_assignment PIN_71 -to TVP_G_i[6]
set_location_assignment PIN_69 -to TVP_G_i[5]
@ -124,7 +126,6 @@ set_location_assignment PIN_7 -to HDMI_TX_RD[5]
set_location_assignment PIN_10 -to HDMI_TX_RD[6]
set_location_assignment PIN_11 -to HDMI_TX_RD[7]
set_location_assignment PIN_100 -to HDMI_TX_INT_N
set_location_assignment PIN_127 -to HDMI_TX_MODE
#============================================================
# SD card
@ -140,8 +141,7 @@ set_location_assignment PIN_30 -to SD_DAT[3]
# Leds
#============================================================
set_location_assignment PIN_44 -to LED_G
#set_location_assignment PIN_46 -to LED_R
set_location_assignment PIN_46 -to TVP_HSYNC_i
set_location_assignment PIN_46 -to LED_R
#============================================================
# I2C
@ -253,4 +253,5 @@ set_global_assignment -name QIP_FILE rtl/char_array.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

4
ossc.sdc
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@ -3,7 +3,7 @@
create_clock -period 27MHz -name clk27 [get_ports clk27]
set_input_delay -clock clk27 0 [get_ports {sda scl SD_CMD SD_DAT* *ALTERA_DATA0}]
set_false_path -from [get_ports {btn* ir_rx HDMI_TX_INT_N HDMI_TX_MODE}]
set_false_path -from [get_ports {btn* cfg* ir_rx HDMI_TX_INT_N LED_R}]
set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
@ -35,7 +35,7 @@ derive_clock_uncertainty
# input delay constraints
set TVP_dmin 0
set TVP_dmax 1.5
set critinputs [get_ports {TVP_R_i* TVP_G_i* TVP_B_i* TVP_HS_i TVP_HSYNC_i TVP_VSYNC_i TVP_FID_i}]
set critinputs [get_ports {TVP_R_i* TVP_G_i* TVP_B_i* TVP_HS_i TVP_SOG_i TVP_VSYNC_i}]
foreach_in_collection c [get_clocks "pclk_tvp*"] {
set_input_delay -clock $c -min $TVP_dmin $critinputs -add_delay
set_input_delay -clock $c -max $TVP_dmax $critinputs -add_delay

34
rtl/ossc.v
View File

@ -28,15 +28,15 @@ module ossc (
input ir_rx,
input [1:0] btn,
input [1:0] cfg,
input TVP_PCLK_i,
input [7:0] TVP_R_i,
input [7:0] TVP_G_i,
input [7:0] TVP_B_i,
input TVP_HS_i,
input TVP_HSYNC_i,
input TVP_SOG_i,
input TVP_VSYNC_i,
input TVP_FID_i,
output HDMI_TX_PCLK,
output reg [7:0] HDMI_TX_RD,
@ -46,12 +46,11 @@ module ossc (
output reg HDMI_TX_HS,
output reg HDMI_TX_VS,
input HDMI_TX_INT_N,
input HDMI_TX_MODE,
output hw_reset_n,
output LED_G,
//output LED_R,
inout LED_R,
output LCD_RS,
output LCD_CS_N,
@ -107,15 +106,19 @@ reg TVP_HSYNC_sync1_reg, TVP_HSYNC_sync2_reg;
reg TVP_VSYNC_sync1_reg, TVP_VSYNC_sync2_reg;
reg [1:0] btn_L, btn_LL;
reg ir_rx_L, ir_rx_LL, HDMI_TX_INT_N_L, HDMI_TX_INT_N_LL, HDMI_TX_MODE_L, HDMI_TX_MODE_LL;
reg ir_rx_L, ir_rx_LL, HDMI_TX_INT_N_L, HDMI_TX_INT_N_LL;
reg vsync_flag_sync1_reg, vsync_flag_sync2_reg;
reg [1:0] cfg_reg;
reg cfg_stored;
wire TVP_SOG_ALT_i;
wire TVP_HSYNC_i = cfg_reg[1] ? TVP_SOG_i : TVP_SOG_ALT_i;
reg [23:0] resync_led_ctr, warn_pll_lock_lost;
reg resync_strobe_sync1_reg, resync_strobe_sync2_reg, resync_strobe_prev;
wire resync_strobe_i;
wire resync_strobe = resync_strobe_sync2_reg;
wire [31:0] controls = {ir_code_cnt, 3'b000, vsync_flag_sync2_reg, pll_activeclock, HDMI_TX_MODE_LL, btn_LL, ir_code};
wire [31:0] controls = {ir_code_cnt, 3'b000, vsync_flag_sync2_reg, pll_activeclock, cfg_reg[0], btn_LL, ir_code};
wire lt_sensor = btn_LL[1];
wire lt_trigger = DE_sc & G_sc[0];
@ -135,14 +138,9 @@ wire osd_enable = osd_enable_pre & ~lt_active;
wire [10:0] xpos_sc;
wire [10:0] ypos_sc;
`ifdef DEBUG
assign LED_R = TVP_HSYNC_i;
assign LED_G = TVP_VSYNC_i;
`else
wire resync_indicator = (warn_pll_lock_lost != 0) | (resync_led_ctr != 0);
//assign LED_R = lt_active ? lt_trig_waiting : resync_indicator;
assign LED_G = lt_active ? ~lt_sensor : (ir_code == 0) & ~resync_indicator;
`endif
wire LED_R_i = lt_active ? lt_trig_waiting : resync_indicator;
assign LED_G = lt_active ? ~lt_sensor : (ir_code == 0) & (~resync_indicator | cfg_reg[1]);
assign LCD_BL = lcd_bl_on ? (~lcd_bl_timeout | lt_active) : 1'b0;
assign HDMI_TX_PCLK = pclk_out;
@ -155,7 +153,6 @@ always @(posedge TVP_PCLK_i) begin
TVP_B <= TVP_B_i;
TVP_HS <= TVP_HS_i;
TVP_VS <= TVP_VSYNC_i;
TVP_FID <= TVP_FID_i;
// sync to pclk
TVP_SOG_sync1_reg <= TVP_HSYNC_i;
@ -222,12 +219,14 @@ begin
{btn_L, btn_LL} <= '0;
{ir_rx_L, ir_rx_LL} <= '0;
{HDMI_TX_INT_N_L, HDMI_TX_INT_N_LL} <= '0;
{HDMI_TX_MODE_L, HDMI_TX_MODE_LL} <= '0;
{cfg_stored, cfg_reg} <= '0;
end else begin
{btn_L, btn_LL} <= {btn, btn_L};
{ir_rx_L, ir_rx_LL} <= {ir_rx, ir_rx_L};
{HDMI_TX_INT_N_L, HDMI_TX_INT_N_LL} <= {HDMI_TX_INT_N, HDMI_TX_INT_N_L};
{HDMI_TX_MODE_L, HDMI_TX_MODE_LL} <= {HDMI_TX_MODE, HDMI_TX_MODE_L};
if (!cfg_stored)
cfg_reg <= cfg;
cfg_stored <= 1'b1;
end
end
@ -327,6 +326,9 @@ always @(posedge pclk_out) begin
end
// A modified <= v1.7 board uses LED_R for TVP_HSYNC input
ALT_IOBUF led_r_iobuf (.i(LED_R_i), .oe(cfg_reg[1]), .o(TVP_SOG_ALT_i), .io(LED_R));
pll_2x pll_pclk (
.areset(pll_areset),
.clkswitch(pll_clkswitch),