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sync processing and preset improvements

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* increase accurary of vblank region calculation
* increase selectable PLL coast range
* fix GBI preset H multiplication factors
* enable 1250i/50 detection
This commit is contained in:
marqs 2024-01-05 15:34:15 +02:00
parent cb8e2b807c
commit 353437ab87
6 changed files with 6588 additions and 6562 deletions
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7
rtl/tvp7002_frontend.v
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@ -122,7 +122,8 @@ wire [11:0] even_max_thold = (H_TOTAL / 12'd2) + (H_TOTAL / 12'd4);
wire [11:0] meas_h_cnt_ref = (vsync_i_type == VSYNC_SEPARATED) ? meas_h_cnt_sogref : meas_h_cnt;
wire [11:0] meas_even_min_thold = (pcnt_line / 12'd4);
wire [11:0] meas_even_max_thold = (pcnt_line / 12'd2) + (pcnt_line / 12'd4);
wire meas_vblank_region = ((pcnt_frame_ctr < (pcnt_frame/16)) | (pcnt_frame_ctr > (pcnt_frame - (pcnt_frame/16))));
wire meas_vblank_region = (pcnt_frame_ctr < 8*pcnt_line) | (pcnt_frame_ctr > (({1'b0, pcnt_frame}<<interlace_flag) - 4*pcnt_line)) |
(interlace_flag & (pcnt_frame_ctr < (pcnt_frame+8*pcnt_line)) & (pcnt_frame_ctr > (pcnt_frame - 4*pcnt_line)));
wire [11:0] glitch_filt_thold = meas_vblank_region ? (pcnt_line/4) : (pcnt_line/8);
// TODO: calculate H/V polarity independently
@ -366,8 +367,8 @@ always @(posedge CLK_MEAS_i) begin
meas_v_cnt <= meas_v_cnt + 1'b1;
end
meas_h_cnt_sogref <= meas_h_cnt;
end else if (~VSYNC_i_np & (meas_h_cnt >= pcnt_line)) begin
// hsync may be missing during vsync, force line change detect if pcnt_line is exceeded
end else if (meas_vblank_region & (meas_h_cnt >= pcnt_line)) begin
// hsync may be missing or irregular during vblank, force line change detect if pcnt_line is exceeded
meas_hl_det <= 1'b0;
meas_h_cnt <= 0;
meas_v_cnt <= meas_v_cnt + 1'b1;

13122
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
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File diff suppressed because it is too large Load Diff

2
software/sys_controller/ossc/avconfig.h
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@ -36,7 +36,7 @@
#define VSYNC_THOLD_MIN 10
#define VSYNC_THOLD_MAX 200
#define SD_SYNC_WIN_MAX 255
#define PLL_COAST_MAX 5
#define PLL_COAST_MAX 10
#define REVERSE_LPF_MAX 31
#define COARSE_GAIN_MAX 15
#define ALC_H_FILTER_MAX 7

2
software/sys_controller/ossc/firmware.h
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@ -24,7 +24,7 @@
#include "sysconfig.h"
#define FW_VER_MAJOR 1
#define FW_VER_MINOR 8
#define FW_VER_MINOR 9
#define PROFILE_VER_MAJOR 1
#define PROFILE_VER_MINOR 6

15
software/sys_controller/ossc/video_modes.c
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@ -214,7 +214,7 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
}
}
if (mindiff_lines >= 110)
if (mindiff_lines >= 130)
return -1;
mode_preset = &video_modes_plm[mindiff_id];
@ -356,7 +356,7 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
break;
case MODE_L3_240x360:
vm_conf->x_rpt = vm_conf->h_skip = 6;
vm_conf->x_rpt = vm_conf->h_skip = 7;
vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
break;
default:
@ -377,8 +377,15 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
else if (mindiff_lm & (MODE_L3_256_COL|MODE_L6_256_COL))
vm_conf->x_rpt = cc->ar_256col ? 2 : 3;
if (mindiff_lm == MODE_L3_320_COL)
vm_conf->x_rpt = 2;
if (mindiff_lm & (MODE_L3_320_COL|MODE_L2_240x360))
vm_conf->x_rpt--;
else if (mindiff_lm & MODE_L3_240x360)
vm_conf->x_rpt -= 2;
if (mindiff_lm == MODE_L2_240x360) {
vm_out->timings.h_active += 80;
vm_out->timings.h_backporch -= 40;
}
// Force TX pixel-repeat for high bandwidth modes
if (((mindiff_lm == MODE_L5_GEN_4_3) && (mode_preset->group == GROUP_288P)) || (mindiff_lm >= MODE_L6_GEN_4_3))

2
software/sys_controller/ossc/video_modes_list.c
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@ -41,7 +41,7 @@ const mode_data_t video_modes_plm_default[] = {
{ "288p", HDMI_288p50, { 720, 288, 5008, 864, 0, 312, 69, 19, 63, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_288P, (MODE_PT | MODE_L2), },
/* 360p: GBI */
{ "480x360", HDMI_Unknown, { 480, 360, 6000, 600, 0, 375, 63, 10, 38, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_384P, (MODE_PT | MODE_L2), },
{ "240x360", HDMI_Unknown, { 256, 360, 6000, 300, 0, 375, 24, 10, 18, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_384P, (MODE_L2_240x360 | MODE_L3_240x360), },
{ "240x360", HDMI_Unknown, { 240, 360, 6000, 300, 0, 375, 32, 10, 18, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_384P, (MODE_L2_240x360 | MODE_L3_240x360), },
/* 384p: Sega Model 2 */
{ "384p", HDMI_Unknown, { 496, 384, 5500, 640, 0, 423, 50, 29, 62, 3, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_384P, (MODE_PT | MODE_L2), },
/* 400p line3x */