diff --git a/ossc.qsf b/ossc.qsf
index a30e747..2289db1 100644
--- a/ossc.qsf
+++ b/ossc.qsf
@@ -230,6 +230,6 @@ set_global_assignment -name VERILOG_FILE rtl/scanconverter.v
set_global_assignment -name QIP_FILE rtl/linebuf.qip
set_global_assignment -name QIP_FILE rtl/pll_2x.qip
set_global_assignment -name QIP_FILE rtl/pll_3x.qip
-set_global_assignment -name QIP_FILE rtl/pll_3x_lowfreq.qip
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/ossc.sdc b/ossc.sdc
index 0aca1bb..963fdbd 100644
--- a/ossc.sdc
+++ b/ossc.sdc
@@ -10,35 +10,49 @@ set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
### Scanconverter clock constraints ###
create_clock -period 108MHz -name pclk_hdtv [get_ports PCLK_in]
-create_clock -period 27MHz -name pclk_ldtv_hs_M0 [get_ports PCLK_in] -add
-create_clock -period 20MHz -name pclk_ldtv_hs_M1 [get_ports PCLK_in] -add
-create_clock -period 13.5MHz -name pclk_sdtv [get_ports PCLK_in] -add
+create_clock -period 13.5MHz -name pclk_sdtv_L2 [get_ports PCLK_in] -add
+create_clock -period 27MHz -name pclk_sdtv_L3 [get_ports PCLK_in] -add
+create_clock -period 27MHz -name pclk_sdtv_L4 [get_ports PCLK_in] -add
+create_clock -period 16MHz -name pclk_sdtv_L5 [get_ports PCLK_in] -add
#derive_pll_clocks
-create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
-create_generated_clock -master_clock pclk_ldtv_hs_M0 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x_M0 {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
-create_generated_clock -master_clock pclk_ldtv_hs_M1 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x_M1 {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]} -add
-create_generated_clock -master_clock pclk_ldtv_hs_M1 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x_M1 {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
+create_generated_clock -master_clock pclk_sdtv_L2 -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
+create_generated_clock -master_clock pclk_sdtv_L3 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
+create_generated_clock -master_clock pclk_sdtv_L4 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
+create_generated_clock -master_clock pclk_sdtv_L5 -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name pclk_5x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]}
derive_clock_uncertainty
# input delay constraints
+set TVP_dmin 0
+set TVP_dmax 1.5
set critinputs [get_ports {R_in* G_in* B_in* HSYNC_in VSYNC_in FID_in}]
-set_input_delay -clock pclk_sdtv -min 0 $critinputs
-set_input_delay -clock pclk_sdtv -max 1.5 $critinputs
-set_input_delay -clock pclk_hdtv -min 0 $critinputs -add_delay
-set_input_delay -clock pclk_hdtv -max 1.5 $critinputs -add_delay
-set_input_delay -clock pclk_ldtv_hs_M0 -min 0 $critinputs -add_delay
-set_input_delay -clock pclk_ldtv_hs_M0 -max 1.5 $critinputs -add_delay
-set_input_delay -clock pclk_ldtv_hs_M1 -min 0 $critinputs -add_delay
-set_input_delay -clock pclk_ldtv_hs_M1 -max 1.5 $critinputs -add_delay
+set_input_delay -clock pclk_hdtv -min $TVP_dmin $critinputs
+set_input_delay -clock pclk_hdtv -max $TVP_dmax $critinputs
+set_input_delay -clock pclk_sdtv_L2 -min $TVP_dmin $critinputs -add_delay
+set_input_delay -clock pclk_sdtv_L2 -max $TVP_dmax $critinputs -add_delay
+set_input_delay -clock pclk_sdtv_L3 -min $TVP_dmin $critinputs -add_delay
+set_input_delay -clock pclk_sdtv_L3 -max $TVP_dmax $critinputs -add_delay
+set_input_delay -clock pclk_sdtv_L4 -min $TVP_dmin $critinputs -add_delay
+set_input_delay -clock pclk_sdtv_L4 -max $TVP_dmax $critinputs -add_delay
+set_input_delay -clock pclk_sdtv_L5 -min $TVP_dmin $critinputs -add_delay
+set_input_delay -clock pclk_sdtv_L5 -max $TVP_dmax $critinputs -add_delay
# output delay constraints (TODO: add vsync)
+set IT_Tsu 1.0
+set IT_Th -0.5
+#todo VS
set critoutputs_hdmi {HDMI_TX_RD* HDMI_TX_GD* HDMI_TX_BD* HDMI_TX_DE HDMI_TX_HS}
-set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv 0 $critoutputs_hdmi
-set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x 0 $critoutputs_hdmi -add_delay
-set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x_M0 0 $critoutputs_hdmi -add_delay
-set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_4x_M1 0 $critoutputs_hdmi -add_delay
+set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv -min $IT_Th $critoutputs_hdmi
+set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv -max $IT_Tsu $critoutputs_hdmi
+set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x -min $IT_Th $critoutputs_hdmi -add_delay
+set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x -max $IT_Tsu $critoutputs_hdmi -add_delay
+set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x -min $IT_Th $critoutputs_hdmi -add_delay
+set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x -max $IT_Tsu $critoutputs_hdmi -add_delay
+set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_4x -min $IT_Th $critoutputs_hdmi -add_delay
+set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_4x -max $IT_Tsu $critoutputs_hdmi -add_delay
+set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_5x -min $IT_Th $critoutputs_hdmi -add_delay
+set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_5x -max $IT_Tsu $critoutputs_hdmi -add_delay
set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
@@ -47,19 +61,18 @@ set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
# Set pixel clocks as exclusive clocks
set_clock_groups -exclusive \
-group {pclk_hdtv} \
--group {pclk_sdtv pclk_2x} \
--group {pclk_ldtv_hs_M0 pclk_3x_M0} \
--group {pclk_ldtv_hs_M1 pclk_3x_M1 pclk_4x_M1}
+-group {pclk_sdtv_L2 pclk_2x} \
+-group {pclk_sdtv_L3 pclk_3x} \
+-group {pclk_sdtv_L4 pclk_4x} \
+-group {pclk_sdtv_L5 pclk_5x}
# Treat CPU clock asynchronous to pixel clocks
set_clock_groups -asynchronous -group {clk27}
# Filter out impossible output mux combinations
-set clkmuxregs [get_cells {scanconverter:scanconverter_inst|R_out[*] scanconverter:scanconverter_inst|G_out[*] scanconverter:scanconverter_inst|B_out[*] scanconverter:scanconverter_inst|HSYNC_out scanconverter:scanconverter_inst|DATA_enable scanconverter:scanconverter_inst|*_pp1*}]
+set clkmuxregs [get_cells {scanconverter:scanconverter_inst|R_out* scanconverter:scanconverter_inst|G_out* scanconverter:scanconverter_inst|B_out* scanconverter:scanconverter_inst|HSYNC_out* scanconverter:scanconverter_inst|VSYNC_out* scanconverter:scanconverter_inst|DE_out* scanconverter:scanconverter_inst|*_pp1* scanconverter:scanconverter_inst|*_pp2*}]
set clkmuxnodes [get_pins {scanconverter_inst|linebuf_*|altsyncram_*|auto_generated|ram_*|portbaddr*}]
-set_false_path -from [get_clocks {pclk_ldtv* pclk_sdtv}] -through $clkmuxregs
-set_false_path -from pclk_3x_M1 -through [remove_from_collection $clkmuxregs {scanconverter:scanconverter_inst|DATA_enable_pp1* scanconverter:scanconverter_inst|HSYNC_pp1*}] -to pclk_4x_M1
-set_false_path -from pclk_3x_M1 -through $clkmuxnodes -to pclk_4x_M1
+set_false_path -from [get_clocks {pclk_sdtv_L2 pclk_sdtv_L3 pclk_sdtv_L4 pclk_sdtv_L5}] -through $clkmuxregs
# Ignore paths from registers which are updated only at the end of vsync
set_false_path -from [get_cells {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter:scanconverter_inst|lines_*}]
@@ -71,9 +84,10 @@ set_false_path -from [get_cells {scanconverter:scanconverter_inst|vcnt_* scancon
set_false_path -to [get_cells {scanconverter:scanconverter_inst|line_out_idx*}]
# Ignore following clock transfers
-set_false_path -from [get_clocks pclk_2x] -to [get_clocks pclk_sdtv]
-set_false_path -from [get_clocks pclk_3x_M*] -to [get_clocks {pclk_ldtv_hs_M*}]
-set_false_path -from [get_clocks pclk_4x_M1] -to [get_clocks {pclk_ldtv_hs_M1 pclk_3x_M1}]
+set_false_path -from [get_clocks pclk_2x] -to [get_clocks pclk_sdtv_L2]
+set_false_path -from [get_clocks pclk_3x] -to [get_clocks {pclk_sdtv_L3}]
+set_false_path -from [get_clocks pclk_4x] -to [get_clocks {pclk_sdtv_L4}]
+set_false_path -from [get_clocks pclk_5x] -to [get_clocks {pclk_sdtv_L5}]
### JTAG Signal Constraints ###
diff --git a/rtl/ossc.v b/rtl/ossc.v
index 9d7d537..e9111f0 100644
--- a/rtl/ossc.v
+++ b/rtl/ossc.v
@@ -55,8 +55,8 @@ module ossc (
wire [7:0] sys_ctrl;
wire h_unstable;
-wire [2:0] pclk_lock;
-wire [2:0] pll_lock_lost;
+wire [1:0] pclk_lock;
+wire [1:0] pll_lock_lost;
wire [31:0] h_info, h_info2, v_info;
wire [10:0] lines_out;
wire [1:0] fpga_vsyncgen;
@@ -68,13 +68,13 @@ wire [7:0] R_out, G_out, B_out;
wire HSYNC_out;
wire VSYNC_out;
wire PCLK_out;
-wire DATA_enable;
+wire DE_out;
wire [7:0] R_out_videogen, G_out_videogen, B_out_videogen;
wire HSYNC_out_videogen;
wire VSYNC_out_videogen;
wire PCLK_out_videogen;
-wire DATA_enable_videogen;
+wire DE_out_videogen;
reg [3:0] cpu_reset_ctr;
@@ -155,7 +155,7 @@ assign reset_n = sys_ctrl[0]; //HDMI_TX_RST_N in v1.2 PCB
assign LED_R = HSYNC_in_L;
assign LED_G = VSYNC_in_L;
`else
-assign LED_R = videogen_sel ? 1'b0 : ((pll_lock_lost != 3'b000)|h_unstable);
+assign LED_R = videogen_sel ? 1'b0 : ((pll_lock_lost != 2'h0)|h_unstable);
assign LED_G = (ir_code == 0);
`endif
@@ -173,15 +173,17 @@ assign HDMI_TX_BD = videogen_sel ? B_out_videogen : B_out;
assign HDMI_TX_HS = videogen_sel ? HSYNC_out_videogen : HSYNC_out;
assign HDMI_TX_VS = videogen_sel ? VSYNC_out_videogen : VSYNC_out;
assign HDMI_TX_PCLK = videogen_sel ? PCLK_out_videogen : PCLK_out;
-assign HDMI_TX_DE = videogen_sel ? DATA_enable_videogen : DATA_enable;
+assign HDMI_TX_DE = videogen_sel ? DE_out_videogen : DE_out;
`else
+wire videogen_sel;
+assign videogen_sel = 1'b0;
assign HDMI_TX_RD = R_out;
assign HDMI_TX_GD = G_out;
assign HDMI_TX_BD = B_out;
assign HDMI_TX_HS = HSYNC_out;
assign HDMI_TX_VS = VSYNC_out;
assign HDMI_TX_PCLK = PCLK_out;
-assign HDMI_TX_DE = DATA_enable;
+assign HDMI_TX_DE = DE_out;
`endif
sys sys_inst(
@@ -219,7 +221,7 @@ scanconverter scanconverter_inst (
.HSYNC_out (HSYNC_out),
.VSYNC_out (VSYNC_out),
.PCLK_out (PCLK_out),
- .DATA_enable (DATA_enable),
+ .DE_out (DE_out),
.h_unstable (h_unstable),
.fpga_vsyncgen (fpga_vsyncgen),
.pclk_lock (pclk_lock),
@@ -246,7 +248,7 @@ videogen vg0 (
.HSYNC_out (HSYNC_out_videogen),
.VSYNC_out (VSYNC_out_videogen),
.PCLK_out (PCLK_out_videogen),
- .ENABLE_out (DATA_enable_videogen)
+ .ENABLE_out (DE_out_videogen)
);
`endif
diff --git a/rtl/pll_2x.ppf b/rtl/pll_2x.ppf
index 9736c2c..b8d8bc6 100644
--- a/rtl/pll_2x.ppf
+++ b/rtl/pll_2x.ppf
@@ -5,6 +5,7 @@
+
diff --git a/rtl/pll_2x.v b/rtl/pll_2x.v
index 9df1f52..6b63144 100644
--- a/rtl/pll_2x.v
+++ b/rtl/pll_2x.v
@@ -9,7 +9,7 @@
// altpll
//
// Simulation Library Files(s):
-//
+// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
@@ -41,11 +41,13 @@ module pll_2x (
areset,
inclk0,
c0,
+ c1,
locked);
input areset;
input inclk0;
output c0;
+ output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
@@ -56,19 +58,21 @@ module pll_2x (
`endif
wire [4:0] sub_wire0;
- wire sub_wire2;
- wire [0:0] sub_wire5 = 1'h0;
+ wire sub_wire3;
+ wire [0:0] sub_wire6 = 1'h0;
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
- wire locked = sub_wire2;
- wire sub_wire3 = inclk0;
- wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+ wire c1 = sub_wire2;
+ wire locked = sub_wire3;
+ wire sub_wire4 = inclk0;
+ wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.areset (areset),
- .inclk (sub_wire4),
+ .inclk (sub_wire5),
.clk (sub_wire0),
- .locked (sub_wire2),
+ .locked (sub_wire3),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
@@ -108,6 +112,10 @@ module pll_2x (
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk1_divide_by = 1,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 5,
+ altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 74074,
altpll_component.intended_device_family = "Cyclone IV E",
@@ -141,7 +149,7 @@ module pll_2x (
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
- altpll_component.port_clk1 = "PORT_UNUSED",
+ altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
@@ -182,8 +190,11 @@ endmodule
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "27.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "67.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -204,18 +215,26 @@ endmodule
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -238,11 +257,14 @@ endmodule
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
@@ -251,6 +273,10 @@ endmodule
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "74074"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
@@ -283,7 +309,7 @@ endmodule
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -303,12 +329,14 @@ endmodule
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.ppf TRUE
@@ -317,4 +345,5 @@ endmodule
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/rtl/pll_3x_lowfreq.ppf b/rtl/pll_3x_lowfreq.ppf
deleted file mode 100644
index 1d235e3..0000000
--- a/rtl/pll_3x_lowfreq.ppf
+++ /dev/null
@@ -1,13 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/rtl/pll_3x_lowfreq.qip b/rtl/pll_3x_lowfreq.qip
deleted file mode 100644
index a8c93f1..0000000
--- a/rtl/pll_3x_lowfreq.qip
+++ /dev/null
@@ -1,6 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "16.1"
-set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_3x_lowfreq.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_3x_lowfreq_bb.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_3x_lowfreq.ppf"]
diff --git a/rtl/pll_3x_lowfreq.v b/rtl/pll_3x_lowfreq.v
deleted file mode 100644
index 41d5547..0000000
--- a/rtl/pll_3x_lowfreq.v
+++ /dev/null
@@ -1,376 +0,0 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll
-
-// ============================================================
-// File Name: pll_3x_lowfreq.v
-// Megafunction Name(s):
-// altpll
-//
-// Simulation Library Files(s):
-//
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2016 Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Intel Program License
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel MegaCore Function License Agreement, or other
-//applicable license agreement, including, without limitation,
-//that your use is for the sole purpose of programming logic
-//devices manufactured by Intel and sold by Intel or its
-//authorized distributors. Please refer to the applicable
-//agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module pll_3x_lowfreq (
- areset,
- inclk0,
- c0,
- c1,
- c2,
- locked);
-
- input areset;
- input inclk0;
- output c0;
- output c1;
- output c2;
- output locked;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
- tri0 areset;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
- wire [4:0] sub_wire0;
- wire sub_wire4;
- wire [0:0] sub_wire7 = 1'h0;
- wire [2:2] sub_wire3 = sub_wire0[2:2];
- wire [1:1] sub_wire2 = sub_wire0[1:1];
- wire [0:0] sub_wire1 = sub_wire0[0:0];
- wire c0 = sub_wire1;
- wire c1 = sub_wire2;
- wire c2 = sub_wire3;
- wire locked = sub_wire4;
- wire sub_wire5 = inclk0;
- wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
-
- altpll altpll_component (
- .areset (areset),
- .inclk (sub_wire6),
- .clk (sub_wire0),
- .locked (sub_wire4),
- .activeclock (),
- .clkbad (),
- .clkena ({6{1'b1}}),
- .clkloss (),
- .clkswitch (1'b0),
- .configupdate (1'b0),
- .enable0 (),
- .enable1 (),
- .extclk (),
- .extclkena ({4{1'b1}}),
- .fbin (1'b1),
- .fbmimicbidir (),
- .fbout (),
- .fref (),
- .icdrclk (),
- .pfdena (1'b1),
- .phasecounterselect ({4{1'b1}}),
- .phasedone (),
- .phasestep (1'b1),
- .phaseupdown (1'b1),
- .pllena (1'b1),
- .scanaclr (1'b0),
- .scanclk (1'b0),
- .scanclkena (1'b1),
- .scandata (1'b0),
- .scandataout (),
- .scandone (),
- .scanread (1'b0),
- .scanwrite (1'b0),
- .sclkout0 (),
- .sclkout1 (),
- .vcooverrange (),
- .vcounderrange ());
- defparam
- altpll_component.bandwidth_type = "HIGH",
- altpll_component.clk0_divide_by = 1,
- altpll_component.clk0_duty_cycle = 50,
- altpll_component.clk0_multiply_by = 3,
- altpll_component.clk0_phase_shift = "0",
- altpll_component.clk1_divide_by = 1,
- altpll_component.clk1_duty_cycle = 50,
- altpll_component.clk1_multiply_by = 12,
- altpll_component.clk1_phase_shift = "0",
- altpll_component.clk2_divide_by = 1,
- altpll_component.clk2_duty_cycle = 50,
- altpll_component.clk2_multiply_by = 15,
- altpll_component.clk2_phase_shift = "0",
- altpll_component.compensate_clock = "CLK0",
- altpll_component.inclk0_input_frequency = 149253,
- altpll_component.intended_device_family = "Cyclone IV E",
- altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_3x_lowfreq",
- altpll_component.lpm_type = "altpll",
- altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
- altpll_component.pll_type = "AUTO",
- altpll_component.port_activeclock = "PORT_UNUSED",
- altpll_component.port_areset = "PORT_USED",
- altpll_component.port_clkbad0 = "PORT_UNUSED",
- altpll_component.port_clkbad1 = "PORT_UNUSED",
- altpll_component.port_clkloss = "PORT_UNUSED",
- altpll_component.port_clkswitch = "PORT_UNUSED",
- altpll_component.port_configupdate = "PORT_UNUSED",
- altpll_component.port_fbin = "PORT_UNUSED",
- altpll_component.port_inclk0 = "PORT_USED",
- altpll_component.port_inclk1 = "PORT_UNUSED",
- altpll_component.port_locked = "PORT_USED",
- altpll_component.port_pfdena = "PORT_UNUSED",
- altpll_component.port_phasecounterselect = "PORT_UNUSED",
- altpll_component.port_phasedone = "PORT_UNUSED",
- altpll_component.port_phasestep = "PORT_UNUSED",
- altpll_component.port_phaseupdown = "PORT_UNUSED",
- altpll_component.port_pllena = "PORT_UNUSED",
- altpll_component.port_scanaclr = "PORT_UNUSED",
- altpll_component.port_scanclk = "PORT_UNUSED",
- altpll_component.port_scanclkena = "PORT_UNUSED",
- altpll_component.port_scandata = "PORT_UNUSED",
- altpll_component.port_scandataout = "PORT_UNUSED",
- altpll_component.port_scandone = "PORT_UNUSED",
- altpll_component.port_scanread = "PORT_UNUSED",
- altpll_component.port_scanwrite = "PORT_UNUSED",
- altpll_component.port_clk0 = "PORT_USED",
- altpll_component.port_clk1 = "PORT_USED",
- altpll_component.port_clk2 = "PORT_USED",
- altpll_component.port_clk3 = "PORT_UNUSED",
- altpll_component.port_clk4 = "PORT_UNUSED",
- altpll_component.port_clk5 = "PORT_UNUSED",
- altpll_component.port_clkena0 = "PORT_UNUSED",
- altpll_component.port_clkena1 = "PORT_UNUSED",
- altpll_component.port_clkena2 = "PORT_UNUSED",
- altpll_component.port_clkena3 = "PORT_UNUSED",
- altpll_component.port_clkena4 = "PORT_UNUSED",
- altpll_component.port_clkena5 = "PORT_UNUSED",
- altpll_component.port_extclk0 = "PORT_UNUSED",
- altpll_component.port_extclk1 = "PORT_UNUSED",
- altpll_component.port_extclk2 = "PORT_UNUSED",
- altpll_component.port_extclk3 = "PORT_UNUSED",
- altpll_component.self_reset_on_loss_lock = "OFF",
- altpll_component.width_clock = 5;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.100000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "80.400002"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "100.500000"
-// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "6.700"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "3"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "12"
-// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "15"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_2x.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "15"
-// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "149253"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq_bb.v TRUE
-// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/rtl/scanconverter.v b/rtl/scanconverter.v
index b708391..c9897b9 100644
--- a/rtl/scanconverter.v
+++ b/rtl/scanconverter.v
@@ -71,15 +71,15 @@ module scanconverter (
output reg HSYNC_out,
output reg VSYNC_out,
output PCLK_out,
- output reg DATA_enable,
+ output reg DE_out,
output h_unstable,
output reg [1:0] fpga_vsyncgen,
- output [2:0] pclk_lock,
- output [2:0] pll_lock_lost,
+ output [1:0] pclk_lock,
+ output [1:0] pll_lock_lost,
output [10:0] lines_out
);
-wire pclk_1x, pclk_2x, pclk_3x, pclk_4x;
+wire pclk_1x, pclk_2x, pclk_3x, pclk_4x, pclk_5x;
wire linebuf_rdclock;
wire pclk_act;
@@ -88,26 +88,25 @@ wire [1:0] slid_act;
wire pclk_2x_lock, pclk_3x_lock;
wire HSYNC_act, VSYNC_act;
-reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_4x, HSYNC_pp1;
-reg VSYNC_1x, VSYNC_2x, VSYNC_pp1;
+reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_4x, HSYNC_5x, HSYNC_pp1, HSYNC_pp2;
+reg VSYNC_1x, VSYNC_2x, VSYNC_pp1, VSYNC_pp2;
reg [11:0] HSYNC_start;
reg FID_1x, FID_prev;
-wire DATA_enable_act;
-reg DATA_enable_pp1;
+wire DE_act;
+reg DE_pp1, DE_pp2;
wire [11:0] linebuf_hoffset; //Offset for line (max. 2047 pixels), MSB indicates which line is read/written
wire [11:0] hcnt_act;
-reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_4x_aspfix, hcnt_3x_opt, hcnt_4x_opt;
+reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_5x, hcnt_4x_aspfix, hcnt_3x_opt, hcnt_4x_opt, hcnt_5x_opt;
-reg [2:0] hcnt_3x_opt_ctr, hcnt_4x_opt_ctr;
+reg [2:0] hcnt_3x_opt_ctr, hcnt_4x_opt_ctr, hcnt_5x_opt_ctr;
wire [10:0] vcnt_act;
-reg [10:0] vcnt_1x, vcnt_1x_tvp, vcnt_2x, lines_1x, lines_2x; //max. 2047
+reg [10:0] vcnt_1x, vcnt_1x_tvp, vcnt_2x, vcnt_4x, vcnt_5x, vcnt_3x_ref, vcnt_4x_ref, vcnt_5x_ref, lines_1x, lines_2x, lines_4x, lines_5x; //max. 2047
reg [9:0] vcnt_3x, lines_3x; //max. 1023
-reg [10:0] vcnt_4x, lines_4x; //max. 2047
reg h_enable_3x_prev4x;
@@ -117,16 +116,22 @@ reg [1:0] pclk_3x_cnt;
reg pclk_1x_prev4x;
reg [1:0] pclk_4x_cnt;
+reg pclk_1x_prev5x;
+reg pclk_1x_prevprev5x;
+reg [2:0] pclk_5x_cnt;
+
// Data enable
reg h_enable_1x, v_enable_1x;
reg h_enable_2x, v_enable_2x;
reg h_enable_3x, v_enable_3x;
reg h_enable_4x, v_enable_4x;
+reg h_enable_5x, v_enable_5x;
reg prev_hs, prev_vs;
reg [11:0] hmax[0:1];
reg line_idx;
reg [1:0] line_out_idx_2x, line_out_idx_3x, line_out_idx_4x;
+reg [2:0] line_out_idx_5x;
reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x;
@@ -148,12 +153,13 @@ reg [2:0] H_OPT_SAMPLE_MULT;
reg [2:0] H_OPT_SAMPLE_SEL;
//8 bits per component -> 16.7M colors
-reg [7:0] R_1x, G_1x, B_1x, R_pp1, G_pp1, B_pp1;
+reg [7:0] R_1x, G_1x, B_1x, R_pp1, G_pp1, B_pp1, R_pp2, G_pp2, B_pp2;
wire [7:0] R_lbuf, G_lbuf, B_lbuf;
wire [7:0] R_act, G_act, B_act;
assign pclk_1x = PCLK_in;
-assign pclk_lock = {pclk_2x_lock, pclk_3x_lock, 1'b0};
+assign PCLK_out = pclk_act;
+assign pclk_lock = {pclk_2x_lock, pclk_3x_lock};
//Scanline generation
function [7:0] apply_scanlines;
@@ -198,14 +204,8 @@ function [7:0] apply_mask;
//Mux for active data selection
//
-//Possible clock transfers:
-//
-// L3_MODE1: pclk_3x -> pclk_4x
-// L3_MODE2: pclk_3x_h1x -> pclk_3x_h4x
-// L3_MODE3: pclk_3x_h1x -> pclk_3x_h5x
-//
//List of critical signals:
-// DATA_enable_act, HSYNC_act
+// [RGB]_act, DE_act, HSYNC_act, VSYNC_act
//
//Non-critical signals and inactive clock combinations filtered out in SDC
always @(*)
@@ -215,8 +215,7 @@ begin
R_act = R_1x;
G_act = G_1x;
B_act = B_1x;
- DATA_enable_act = (h_enable_1x & v_enable_1x);
- PCLK_out = pclk_1x;
+ DE_act = (h_enable_1x & v_enable_1x);
HSYNC_act = HSYNC_1x;
VSYNC_act = VSYNC_1x;
lines_out = lines_1x;
@@ -231,8 +230,7 @@ begin
R_act = R_lbuf;
G_act = G_lbuf;
B_act = B_lbuf;
- DATA_enable_act = (h_enable_2x & v_enable_2x);
- PCLK_out = pclk_2x;
+ DE_act = (h_enable_2x & v_enable_2x);
HSYNC_act = HSYNC_2x;
VSYNC_act = VSYNC_2x;
lines_out = lines_2x;
@@ -249,34 +247,30 @@ begin
B_act = B_lbuf;
HSYNC_act = HSYNC_3x;
VSYNC_act = VSYNC_1x;
- DATA_enable_act = (h_enable_3x & v_enable_3x);
+ DE_act = (h_enable_3x & v_enable_3x);
lines_out = {1'b0, lines_3x};
slid_act = line_out_idx_3x;
- vcnt_act = vcnt_3x/2'h3; //divider generated
+ vcnt_act = vcnt_3x_ref;
case (H_MULTMODE)
`H_MULTMODE_FULLWIDTH: begin
- PCLK_out = pclk_3x;
linebuf_rdclock = pclk_3x;
linebuf_hoffset = hcnt_3x;
pclk_act = pclk_3x;
hcnt_act = hcnt_3x;
end
`H_MULTMODE_ASPECTFIX: begin
- PCLK_out = pclk_4x;
linebuf_rdclock = pclk_4x;
linebuf_hoffset = hcnt_4x_aspfix;
pclk_act = pclk_4x;
hcnt_act = hcnt_4x_aspfix;
end
`H_MULTMODE_OPTIMIZED: begin
- PCLK_out = pclk_3x;
linebuf_rdclock = pclk_3x;
linebuf_hoffset = hcnt_3x_opt;
pclk_act = pclk_3x;
hcnt_act = hcnt_3x;
end
default: begin
- PCLK_out = pclk_3x;
linebuf_rdclock = pclk_3x;
linebuf_hoffset = hcnt_3x;
pclk_act = pclk_3x;
@@ -290,11 +284,10 @@ begin
B_act = B_lbuf;
HSYNC_act = HSYNC_4x;
VSYNC_act = VSYNC_1x;
- DATA_enable_act = (h_enable_4x & v_enable_4x);
+ DE_act = (h_enable_4x & v_enable_4x);
lines_out = lines_4x;
slid_act = line_out_idx_4x;
- vcnt_act = vcnt_4x/4;
- PCLK_out = pclk_4x;
+ vcnt_act = vcnt_4x_ref;
linebuf_rdclock = pclk_4x;
pclk_act = pclk_4x;
hcnt_act = hcnt_4x;
@@ -310,12 +303,36 @@ begin
end
endcase
end
+ `V_MULTMODE_5X: begin
+ R_act = R_lbuf;
+ G_act = G_lbuf;
+ B_act = B_lbuf;
+ HSYNC_act = HSYNC_5x;
+ VSYNC_act = VSYNC_1x;
+ DE_act = (h_enable_5x & v_enable_5x);
+ lines_out = lines_5x;
+ slid_act = line_out_idx_5x;
+ vcnt_act = vcnt_5x_ref;
+ linebuf_rdclock = pclk_5x;
+ pclk_act = pclk_5x;
+ hcnt_act = hcnt_5x;
+ case (H_MULTMODE)
+ `H_MULTMODE_FULLWIDTH: begin
+ linebuf_hoffset = hcnt_5x;
+ end
+ `H_MULTMODE_OPTIMIZED: begin
+ linebuf_hoffset = hcnt_5x_opt;
+ end
+ default: begin
+ linebuf_hoffset = hcnt_5x;
+ end
+ endcase
+ end
default: begin
R_act = R_1x;
G_act = G_1x;
B_act = B_1x;
- DATA_enable_act = (h_enable_1x & v_enable_1x);
- PCLK_out = pclk_1x;
+ DE_act = (h_enable_1x & v_enable_1x);
HSYNC_act = HSYNC_1x;
VSYNC_act = VSYNC_1x;
lines_out = lines_1x;
@@ -330,29 +347,21 @@ begin
end
pll_2x pll_linedouble (
- .areset ( (V_MULTMODE != `V_MULTMODE_2X) ),
+ .areset ( (V_MULTMODE != `V_MULTMODE_2X) & (V_MULTMODE != `V_MULTMODE_5X) ),
.inclk0 ( PCLK_in ),
.c0 ( pclk_2x ),
+ .c1 ( pclk_5x ),
.locked ( pclk_2x_lock )
);
pll_3x pll_linetriple (
.areset ( (V_MULTMODE != `V_MULTMODE_3X) & (V_MULTMODE != `V_MULTMODE_4X) ),
.inclk0 ( PCLK_in ),
- .c0 ( pclk_3x ), // sampling clock for 240p: 1280 or 960 samples & MODE0: 1280 output pixels from 1280 input samples (16:9)
- .c1 ( pclk_4x ), // MODE1: 1280 output pixels from 960 input samples (960 drawn -> 4:3 aspect)
+ .c0 ( pclk_3x ),
+ .c1 ( pclk_4x ),
.locked ( pclk_3x_lock )
);
-/*pll_3x_lowfreq pll_linetriple_lowfreq (
- .areset ( (H_LINEMULT != `LINEMULT_TRIPLE) | ~H_L3MODE[1]),
- .inclk0 ( PCLK_in ),
- .c0 ( pclk_3x_h1x ), // sampling clock for 240p: 320 or 256 samples
- .c1 ( pclk_3x_h4x ), // MODE2: 1280 output pixels from 320 input samples (960 drawn -> 4:3 aspect)
- .c2 ( pclk_3x_h5x ), // MODE3: 1280 output pixels from 256 input samples (1024 drawn -> 5:4 aspect)
- .locked ( pclk_3x_lowfreq_lock )
-);*/
-
//TODO: add secondary buffers for interlaced signals with alternative field order
linebuf linebuf_rgb (
.data ( {R_1x, G_1x, B_1x} ),
@@ -374,29 +383,42 @@ begin
B_pp1 <= 8'h00;
HSYNC_pp1 <= 1'b0;
VSYNC_pp1 <= 1'b0;
- DATA_enable_pp1 <= 1'b0;
+ DE_pp1 <= 1'b0;
+ R_pp2 <= 8'h00;
+ G_pp2 <= 8'h00;
+ B_pp2 <= 8'h00;
+ HSYNC_pp2 <= 1'b0;
+ VSYNC_pp2 <= 1'b0;
+ DE_pp2 <= 1'b0;
R_out <= 8'h00;
G_out <= 8'h00;
G_out <= 8'h00;
HSYNC_out <= 1'b0;
VSYNC_out <= 1'b0;
- DATA_enable <= 1'b0;
+ DE_out <= 1'b0;
end
else
begin
- R_pp1 <= apply_scanlines(V_SCANLINEMODE, R_act, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
- G_pp1 <= apply_scanlines(V_SCANLINEMODE, G_act, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
- B_pp1 <= apply_scanlines(V_SCANLINEMODE, B_act, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
+ R_pp1 <= R_act;
+ G_pp1 <= G_act;
+ B_pp1 <= B_act;
HSYNC_pp1 <= HSYNC_act;
VSYNC_pp1 <= VSYNC_act;
- DATA_enable_pp1 <= DATA_enable_act;
+ DE_pp1 <= DE_act;
- R_out <= apply_mask(1, R_pp1, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
- G_out <= apply_mask(1, G_pp1, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
- B_out <= apply_mask(1, B_pp1, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
- HSYNC_out <= HSYNC_pp1;
- VSYNC_out <= VSYNC_pp1;
- DATA_enable <= DATA_enable_pp1;
+ R_pp2 <= apply_scanlines(V_SCANLINEMODE, R_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
+ G_pp2 <= apply_scanlines(V_SCANLINEMODE, G_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
+ B_pp2 <= apply_scanlines(V_SCANLINEMODE, B_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
+ HSYNC_pp2 <= HSYNC_act;
+ VSYNC_pp2 <= VSYNC_act;
+ DE_pp2 <= DE_act;
+
+ R_out <= apply_mask(1, R_pp2, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
+ G_out <= apply_mask(1, G_pp2, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
+ B_out <= apply_mask(1, B_pp2, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
+ HSYNC_out <= HSYNC_pp2;
+ VSYNC_out <= VSYNC_pp2;
+ DE_out <= DE_pp2;
end
end
@@ -416,12 +438,12 @@ begin
else if (warn_h_unstable != 0)
warn_h_unstable <= warn_h_unstable + 1'b1;
- if ((V_MULTMODE == `V_MULTMODE_2X) & ~pclk_2x_lock)
+ if (((V_MULTMODE == `V_MULTMODE_2X) | (V_MULTMODE == `V_MULTMODE_5X)) & ~pclk_2x_lock)
warn_pll_lock_lost <= 1;
else if (warn_pll_lock_lost != 0)
warn_pll_lock_lost <= warn_pll_lock_lost + 1'b1;
- if ((V_MULTMODE == `V_MULTMODE_3X) & ~pclk_3x_lock)
+ if (((V_MULTMODE == `V_MULTMODE_3X) | (V_MULTMODE == `V_MULTMODE_4X)) & ~pclk_3x_lock)
warn_pll_lock_lost_3x <= 1;
else if (warn_pll_lock_lost_3x != 0)
warn_pll_lock_lost_3x <= warn_pll_lock_lost_3x + 1'b1;
@@ -429,7 +451,7 @@ begin
end
assign h_unstable = (warn_h_unstable != 0);
-assign pll_lock_lost = {(warn_pll_lock_lost != 0), (warn_pll_lock_lost_3x != 0), 1'b0};
+assign pll_lock_lost = {(warn_pll_lock_lost != 0), (warn_pll_lock_lost_3x != 0)};
//Buffer the inputs using input pixel clock and generate 1x signals
always @(posedge pclk_1x or negedge reset_n)
@@ -569,7 +591,7 @@ begin
end
else
begin
- if ((pclk_1x == 1'b0) & `HSYNC_TRAILING_EDGE) //sync with posedge of pclk_1x
+ if ((pclk_1x == 1'b0) & `HSYNC_TRAILING_EDGE) //aligned with posedge of pclk_1x
begin
hcnt_2x <= 0;
line_out_idx_2x <= 0;
@@ -582,9 +604,6 @@ begin
else
hcnt_2x <= hcnt_2x + 1'b1;
- if (hcnt_2x == 0)
- vcnt_2x <= vcnt_2x + 1'b1;
-
if ((pclk_1x == 1'b0) & (fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] == 1'b1))
begin
if (`VSYNC_TRAILING_EDGE)
@@ -595,11 +614,13 @@ begin
lines_2x <= vcnt_2x;
end
end
- else if ((pclk_1x == 1'b0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //sync with posedge of pclk_1x
+ else if ((pclk_1x == 1'b0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //aligned with posedge of pclk_1x
begin
vcnt_2x <= 0;
lines_2x <= vcnt_2x;
end
+ else if (hcnt_2x == hmax[~line_idx])
+ vcnt_2x <= vcnt_2x + 1'b1;
if (pclk_1x == 1'b0)
begin
@@ -610,19 +631,19 @@ begin
end
HSYNC_2x <= ~(hcnt_2x >= HSYNC_start);
- //TODO: VSYNC_2x
+
h_enable_2x <= ((hcnt_2x >= H_BACKPORCH) & (hcnt_2x < H_BACKPORCH + H_ACTIVE));
v_enable_2x <= ((vcnt_2x >= (V_BACKPORCH<<1)) & (vcnt_2x < ((V_BACKPORCH + V_ACTIVE)<<1)));
end
end
-//Generate 3x signals for linetriple M0
always @(posedge pclk_3x or negedge reset_n)
begin
if (!reset_n)
begin
hcnt_3x <= 0;
vcnt_3x <= 0;
+ vcnt_3x_ref <= 0;
lines_3x <= 0;
HSYNC_3x <= 0;
h_enable_3x <= 0;
@@ -635,7 +656,7 @@ begin
end
else
begin
- if ((pclk_3x_cnt == 0) & `HSYNC_TRAILING_EDGE) //sync with posedge of pclk_1x
+ if ((pclk_3x_cnt == 0) & `HSYNC_TRAILING_EDGE) //aligned with posedge of pclk_1x
begin
hcnt_3x <= 0;
line_out_idx_3x <= 0;
@@ -664,21 +685,25 @@ begin
end
end
- if (hcnt_3x == 0)
- vcnt_3x <= vcnt_3x + 1'b1;
-
- if ((pclk_3x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //sync with posedge of pclk_1x
+ if ((pclk_3x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //aligned with posedge of pclk_1x
begin
vcnt_3x <= 0;
+ vcnt_3x_ref <= 0;
lines_3x <= vcnt_3x;
end
+ else if (hcnt_3x == hmax[~line_idx])
+ begin
+ vcnt_3x <= vcnt_3x + 1'b1;
+ if (line_out_idx_3x == 2)
+ vcnt_3x_ref <= vcnt_3x_ref + 1'b1;
+ end
HSYNC_3x <= ~(hcnt_3x >= HSYNC_start);
//TODO: VSYNC_3x
h_enable_3x <= ((hcnt_3x >= H_BACKPORCH) & (hcnt_3x < H_BACKPORCH + H_ACTIVE));
- v_enable_3x <= ((vcnt_3x >= (3*V_BACKPORCH)) & (vcnt_3x < (3*(V_BACKPORCH + V_ACTIVE)))); //multiplier generated!!!
+ v_enable_3x <= ((vcnt_3x_ref >= V_BACKPORCH) & (vcnt_3x_ref < V_BACKPORCH + V_ACTIVE));
- //read pclk_1x to examine when edges are synced (pclk_1x=1 @ 120deg & pclk_1x=0 @ 240deg)
+ //track pclk_3x alignment to pclk_1x rising edge (pclk_1x=1 @ 120deg & pclk_1x=0 @ 240deg)
if (((pclk_1x_prev3x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_3x_cnt == 2'h2))
pclk_3x_cnt <= 0;
else
@@ -688,7 +713,6 @@ begin
end
end
-//Generate 4x signals for linetriple M1
always @(posedge pclk_4x or negedge reset_n)
begin
if (!reset_n)
@@ -697,6 +721,7 @@ begin
h_enable_3x_prev4x <= 0;
hcnt_4x <= 0;
vcnt_4x <= 0;
+ vcnt_4x_ref <= 0;
lines_4x <= 0;
HSYNC_4x <= 0;
h_enable_4x <= 0;
@@ -718,7 +743,7 @@ begin
h_enable_3x_prev4x <= h_enable_3x;
- if ((pclk_4x_cnt == 0) & `HSYNC_TRAILING_EDGE) //sync with posedge of pclk_1x
+ if ((pclk_4x_cnt == 0) & `HSYNC_TRAILING_EDGE) //aligned with posedge of pclk_1x
begin
hcnt_4x <= 0;
line_out_idx_4x <= 0;
@@ -747,21 +772,25 @@ begin
end
end
- if (hcnt_4x == 0)
- vcnt_4x <= vcnt_4x + 1'b1;
-
- if ((pclk_4x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //sync with posedge of pclk_1x
+ if ((pclk_4x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //aligned with posedge of pclk_1x
begin
vcnt_4x <= 0;
+ vcnt_4x_ref <= 0;
lines_4x <= vcnt_4x;
end
+ else if (hcnt_4x == hmax[~line_idx])
+ begin
+ vcnt_4x <= vcnt_4x + 1'b1;
+ if (line_out_idx_4x == 3)
+ vcnt_4x_ref <= vcnt_4x_ref + 1'b1;
+ end
HSYNC_4x <= ~(hcnt_4x >= HSYNC_start);
//TODO: VSYNC_4x
h_enable_4x <= ((hcnt_4x >= H_BACKPORCH) & (hcnt_4x < H_BACKPORCH + H_ACTIVE));
- v_enable_4x <= ((vcnt_4x >= (4*V_BACKPORCH)) & (vcnt_4x < (4*(V_BACKPORCH + V_ACTIVE))));
+ v_enable_4x <= ((vcnt_4x_ref >= V_BACKPORCH) & (vcnt_4x_ref < V_BACKPORCH + V_ACTIVE));
- //read pclk_1x to examine when edges are synced (pclk_1x=1 @ 180deg & pclk_1x=0 @ 270deg)
+ //track pclk_4x alignment to pclk_1x rising edge (pclk_1x=1 @ 180deg & pclk_1x=0 @ 270deg)
if (((pclk_1x_prev4x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_4x_cnt == 2'h3))
pclk_4x_cnt <= 0;
else
@@ -771,5 +800,82 @@ begin
end
end
+always @(posedge pclk_5x or negedge reset_n)
+begin
+ if (!reset_n)
+ begin
+ hcnt_5x <= 0;
+ vcnt_5x <= 0;
+ vcnt_5x_ref <= 0;
+ lines_5x <= 0;
+ HSYNC_5x <= 0;
+ h_enable_5x <= 0;
+ v_enable_5x <= 0;
+ pclk_5x_cnt <= 0;
+ pclk_1x_prev5x <= 0;
+ pclk_1x_prevprev5x <= 0;
+ line_out_idx_5x <= 0;
+ hcnt_5x_opt <= 0;
+ hcnt_5x_opt_ctr <= 0;
+ end
+ else
+ begin
+ if ((pclk_5x_cnt == 0) & `HSYNC_TRAILING_EDGE) //aligned with posedge of pclk_1x
+ begin
+ hcnt_5x <= 0;
+ line_out_idx_5x <= 0;
+ hcnt_5x_opt <= H_OPT_SAMPLE_SEL;
+ hcnt_5x_opt_ctr <= 0;
+ end
+ else if (hcnt_5x == hmax[~line_idx]) //line_idx_prev?
+ begin
+ hcnt_5x <= 0;
+ line_out_idx_5x <= line_out_idx_5x + 1'b1;
+ hcnt_5x_opt <= H_OPT_SAMPLE_SEL;
+ hcnt_5x_opt_ctr <= 0;
+ end
+ else
+ begin
+ hcnt_5x <= hcnt_5x + 1'b1;
+ if (hcnt_5x >= H_OPT_STARTOFF)
+ begin
+ if (hcnt_5x_opt_ctr == H_OPT_SCALE-1'b1)
+ begin
+ hcnt_5x_opt <= hcnt_5x_opt + H_OPT_SAMPLE_MULT;
+ hcnt_5x_opt_ctr <= 0;
+ end
+ else
+ hcnt_5x_opt_ctr <= hcnt_5x_opt_ctr + 1'b1;
+ end
+ end
+
+ if ((pclk_5x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //aligned with posedge of pclk_1x
+ begin
+ vcnt_5x <= 0;
+ vcnt_5x_ref <= 0;
+ lines_5x <= vcnt_5x;
+ end
+ else if (hcnt_5x == hmax[~line_idx])
+ begin
+ vcnt_5x <= vcnt_5x + 1'b1;
+ if (line_out_idx_5x == 4)
+ vcnt_5x_ref <= vcnt_5x_ref + 1'b1;
+ end
+
+ HSYNC_5x <= ~(hcnt_5x >= HSYNC_start);
+ //TODO: VSYNC_5x
+ h_enable_5x <= ((hcnt_5x >= H_BACKPORCH-96) & (hcnt_5x < H_BACKPORCH + H_ACTIVE + 96));
+ v_enable_5x <= ((vcnt_5x_ref >= V_BACKPORCH) & (vcnt_5x_ref < V_BACKPORCH + V_ACTIVE));
+
+ //track pclk_5x alignment to pclk_1x rising edge (pclk_1x=1 @ 144deg & pclk_1x=0 @ 216deg & pclk_1x=0 @ 288deg)
+ if (((pclk_1x_prevprev5x == 1'b1) & (pclk_1x_prev5x == 1'b0)) | (pclk_5x_cnt == 3'h4))
+ pclk_5x_cnt <= 0;
+ else
+ pclk_5x_cnt <= pclk_5x_cnt + 1'b1;
+
+ pclk_1x_prev5x <= pclk_1x;
+ pclk_1x_prevprev5x <= pclk_1x_prev5x;
+ end
+end
endmodule
diff --git a/software/sys_controller/mem_init/sys_onchip_memory2_0.hex b/software/sys_controller/mem_init/sys_onchip_memory2_0.hex
index e2deb3c..c2ed017 100644
--- a/software/sys_controller/mem_init/sys_onchip_memory2_0.hex
+++ b/software/sys_controller/mem_init/sys_onchip_memory2_0.hex
@@ -1,7 +1,7 @@
:020000020000FC
:2000000000402074084008140800683A0000000000000000000000000000000000000000FE
-:2000080006C02074DEE8001406802074D6BE85140080207410A06C1400C0207418E1731445
-:2000100010C00326100000151080010410FFFD360815CC800815DA80003FFF06DEFFFB04DB
+:2000080006C02074DEE8001406802074D6BE84140080207410A0701400C0207418E1851430
+:2000100010C00326100000151080010410FFFD360815C8000815D600003FFF06DEFFFB04E3
:2000180000BFE084D880000500800084D880004500800344D8800085DFC0041529403FCCD7
:200020000080004428800426008000842880041E008014040000030600800C040000010624
:2000280000800404D88000C5D88000C331803FCC10800094D88000C5300002260080080417
@@ -10,20 +10,20 @@
:20004000D8000205D8000245D8000285D80002C5D8000305D8000345D8000385D80003C5A4
:2000480008104640DFC00417DEC00504F800283ADEFFFC04DC000015040020B484041804F5
:20005000DC80021504801304DC400115900B883A2023883A000D883A8009883ADFC003151D
-:200058000816514089403FCC8009883A000D883A0816578004400044900B883A8009883AC6
-:20006000880D883A08165140880B883A8009883ADFC00317DC800217DC400117DC00001785
-:20006800DEC00404081654C1DEFFFC04DC000015040020B484041804DC800215DC400115B0
-:200070002025883A2823883A8009883A000D883A01401304DFC003150816514091403FCCA8
-:200078008009883A000D883A081657800180004489403FCC8009883ADFC00317DC80021747
-:20008000DC400117DC000017DEC0040408165781DEFFFF0421003FCCDFC0001508101300B2
+:2000580008164CC089403FCC8009883A000D883A0816530004400044900B883A8009883ACF
+:20006000880D883A08164CC0880B883A8009883ADFC00317DC800217DC400117DC0000170A
+:20006800DEC0040408165041DEFFFC04DC000015040020B484041804DC800215DC40011534
+:200070002025883A2823883A8009883A000D883A01401304DFC0031508164CC091403FCC2D
+:200078008009883A000D883A081653000180004489403FCC8009883ADFC00317DC800217CB
+:20008000DC400117DC000017DEC0040408165301DEFFFF0421003FCCDFC000150810130036
:20008800DFC00017DEC00104F800283ADEFFFF0429403FCC21003FCCDFC0001508101A80BF
:200090000005883ADFC00017DEC00104F800283ADEFFFB04DCC00315DC800215DC400115A1
:20009800DC000015DFC004152825883A3027883A2023883A2821883A8485C83A14C0060E74
:2000A0008140000389003FCC8400004408101A808C400044003FF8060005883ADFC00417A0
:2000A800DCC00317DC800217DC400117DC000017DEC00504F800283ADEFFFF040140FA04C6
-:2000B000DFC0001508153FC01009883ADFC00017DEC001040815DD41DEFFFF04000B883A44
+:2000B000DFC0001508153B401009883ADFC00017DEC001040815D8C1DEFFFF04000B883A4D
:2000B800010003C4DFC00015081022C0000B883A01001844DFC00017DEC00104081022C134
-:2000C000DEFFFD04DC000015040020B4842080048140008301000144DFC00215DC400115DF
+:2000C000DEFFFD04DC000015040020B4842084048140008301000144DFC00215DC400115DB
:2000C800081022C0808000838100030300FFFEC41004D1FA20C6703A044001041085883A44
:2000D0001085883A1884B03A01400F448809883A80800305081022C00100004408102B8042
:2000D8008809883A01400744081022C001400C0401001844081022C001402C84010002444F
@@ -47,7 +47,7 @@
:20016800010003C4DFC00215DC400115081022C0044030448809883A0810210084003FCCFA
:20017000800AC03A10803F8C8809883A114AB03A081022C0014000C401003184DFC002178B
:20017800DC400117DC000017DEC00304081022C1DEFFF904DCC00315DC800215DC4001156D
-:200180002025883A2823883A010001040140074404C020B49CE08004DD000415DC0000153A
+:200180002025883A2823883A010001040140074404C020B49CE08404DD000415DC00001536
:20018800DFC006153821883ADD4005153029883A081022C098C0030381C0004C00BFFF4449
:200190001884703A39CF883A11CEB03A99C00305988003171080008C10000226010000444A
:200198000810590001001C049C0000C308102100108000CC8D4000CC00C00044100B883A47
@@ -66,11 +66,11 @@
:20020000081021001140054C01000104081022C00400190401000384081021001080040C81
:200208001000321E0100004408102B8080BFFFC41021883A10BFFFCC103FF61E00002B064B
:20021000053FE8048C400C0C008008048880081E018000C4D16000C401001CC408102500A8
-:200218000140207401800484295CED840000090600800C0488800B1E018000C4D16000C4E8
-:2002200001001CC4081025000140207401800484295CE48401001D8408102500040000846E
+:200218000140207401800484295CEB840000090600800C0488800B1E018000C4D16000C4EA
+:2002200001001CC4081025000140207401800484295CE28401001D84081025000400008470
:20022800003FA306008004048880081E018000C4D160000401001CC40810250001402074AB
-:2002300001800484295CE004003FF206018000C4D160000401001CC4081025000140207498
-:2002380001800484295CE904003FEA06000B883A01000304081022C0014010040100034490
+:2002300001800484295CDE04003FF206018000C4D160000401001CC408102500014020749A
+:2002380001800484295CE704003FEA06000B883A01000304081022C0014010040100034492
:20024000081022C00140004401000384081022C0000B883A01000384081022C008102D8089
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:20025000DEC00704F800283ADEFFFD04DC0000152021883A01001644DC400115DFC0021576
@@ -78,851 +78,851 @@
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diff --git a/software/sys_controller/ossc/av_controller.c b/software/sys_controller/ossc/av_controller.c
index 0843413..e9f197f 100644
--- a/software/sys_controller/ossc/av_controller.c
+++ b/software/sys_controller/ossc/av_controller.c
@@ -388,6 +388,7 @@ void set_videoinfo()
switch (cm.target_lm) {
case MODE_L3_320_COL:
+ case MODE_L5_256_COL:
h_opt_scale = 3;
break;
case MODE_L3_256_COL:
diff --git a/software/sys_controller/ossc/avconfig.c b/software/sys_controller/ossc/avconfig.c
index 83be8d3..5c2c1c5 100644
--- a/software/sys_controller/ossc/avconfig.c
+++ b/software/sys_controller/ossc/avconfig.c
@@ -42,7 +42,6 @@ avconfig_t tc;
// Default configuration
const avconfig_t tc_default = {
.l3_mode = 1,
- .l5_mode = 1,
.pm_240p = 1,
.pm_384p = 1,
.pm_480i = 1,
diff --git a/software/sys_controller/ossc/menu.c b/software/sys_controller/ossc/menu.c
index d956150..9c2f076 100644
--- a/software/sys_controller/ossc/menu.c
+++ b/software/sys_controller/ossc/menu.c
@@ -50,7 +50,8 @@ static const char *s480p_mode_desc[] = { LNG("Auto","ｼﾞﾄﾞｳ"), "DTV 480
static const char *sync_lpf_desc[] = { LNG("Off","ｵﾌ"), LNG("33MHz (min)","33MHz (ｻｲｼｮｳ)"), LNG("10MHz (med)","10MHz (ﾁｭｳｲ)"), LNG("2.5MHz (max)","2.5MHz (ｻｲﾀﾞｲ)") };
static const char *l3_mode_desc[] = { LNG("Generic 16:9","ﾊﾝﾖｳ 16:9"), LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷ."), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") };
static const char *l4_mode_desc[] = { LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷ."), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") };
-static const char *pm_240p_desc[] = { "Passthru", "Line2x", "Line3x", "Line4x" };
+static const char *l5_mode_desc[] = { LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") };
+static const char *pm_240p_desc[] = { "Passthru", "Line2x", "Line3x", "Line4x", "Line5x" };
static const char *pm_384p_desc[] = { "Passthru", "Line2x" };
static const char *pm_480i_desc[] = { "Passthru", "Line2x" };
static const char *pm_480p_desc[] = { "Passthru", "Line2x" };
@@ -112,7 +113,7 @@ MENU(menu_output, P99_PROTECT({ \
{ "480p/576p proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480p, OPT_WRAP, SETTING_ITEM(pm_480p_desc) } } },
{ "Line3x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l3_mode, OPT_WRAP, SETTING_ITEM(l3_mode_desc) } } },
{ "Line4x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l4_mode, OPT_WRAP, SETTING_ITEM(l4_mode_desc) } } },
- { "Line5x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l5_mode, OPT_WRAP, SETTING_ITEM(l3_mode_desc) } } },
+ { "Line5x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l5_mode, OPT_WRAP, SETTING_ITEM(l5_mode_desc) } } },
{ "256x240 L3_Hmult", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.l3m3_hmult, OPT_NOWRAP, 1, 5, value_disp } } },
{ LNG("TX mode","TXﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.tx_mode, OPT_WRAP, SETTING_ITEM(tx_mode_desc) } } },
{ LNG("Initial input","ｼｮｷﾆｭｳﾘｮｸ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.def_input, OPT_WRAP, SETTING_ITEM(avinput_str) } } },
diff --git a/software/sys_controller/tvp7002/video_modes.c b/software/sys_controller/tvp7002/video_modes.c
index ffced2c..ce19cba 100644
--- a/software/sys_controller/tvp7002/video_modes.c
+++ b/software/sys_controller/tvp7002/video_modes.c
@@ -36,7 +36,7 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
alt_8 i;
alt_u8 num_modes = sizeof(video_modes)/sizeof(mode_data_t);
video_type mode_type;
- mode_flags valid_lm[] = { MODE_PT, MODE_L2, (MODE_L3_GEN_16_9<
hal
default
- Jan 23, 2017 11:53:50 PM
- 1485208430382
+ Jan 29, 2017 12:54:52 PM
+ 1485687292131
./
settings.bsp
../../sys.sopcinfo
diff --git a/sys.sopcinfo b/sys.sopcinfo
index 5f610e7..f1d6991 100644
--- a/sys.sopcinfo
+++ b/sys.sopcinfo
@@ -1,11 +1,11 @@
-
+
java.lang.Integer
- 1485208293
+ 1485687165
false
true
false