RomanRom2/ossc
1
0
Fork 0
mirror of https://github.com/marqs85/ossc synced 2026-02-20 13:31:53 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity

update flash imem addr for 2nd firmware

Browse Source
This commit is contained in:
marqs 2026-02-05 21:44:15 +02:00
parent bb4932fc28
commit 3d5e849fcd
6 changed files with 8 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
ossc.cof
View File

@ -7,6 +7,7 @@
<width>1</width> <width>1</width>
<mode>7</mode> <mode>7</mode>
<sof_data> <sof_data>
<start_address>00080000</start_address>
<user_name>Page_0</user_name> <user_name>Page_0</user_name>
<page_flags>1</page_flags> <page_flags>1</page_flags>
<bit0> <bit0>

2
rtl/ossc.v
View File

@ -377,7 +377,7 @@ sys sys_inst(
.reset_po_reset_n (po_reset_n), .reset_po_reset_n (po_reset_n),
.ibex_0_ndm_ndmreset_o (ndmreset_req), .ibex_0_ndm_ndmreset_o (ndmreset_req),
.ibex_0_ndm_ndmreset_ack_i (ndmreset_ack), .ibex_0_ndm_ndmreset_ack_i (ndmreset_ack),
.ibex_0_config_boot_addr_i (32'h02050000), .ibex_0_config_boot_addr_i (32'h020D0000),
.ibex_0_config_core_sleep_o (), .ibex_0_config_core_sleep_o (),
.master_0_master_reset_reset (jtagm_reset_req), .master_0_master_reset_reset (jtagm_reset_req),
.i2c_opencores_0_export_scl_pad_io (scl), .i2c_opencores_0_export_scl_pad_io (scl),

2
scripts/rv-reprogram.tcl
View File

@ -1,6 +1,6 @@
# flash details # flash details
set flash_base 0x02000000 set flash_base 0x02000000
set flash_imem_offset 0x00050000 set flash_imem_offset 0x000D0000
set flash_imem_base [format 0x%.8x [expr $flash_base + $flash_imem_offset]] set flash_imem_base [format 0x%.8x [expr $flash_base + $flash_imem_offset]]
set flash_secsize 65536 set flash_secsize 65536

4
software/sys_controller/Makefile
View File

@ -1150,8 +1150,8 @@ src/userdata_sjis.c: src/userdata.c
iconv -f UTF-8 -t SHIFT-JIS src/userdata.c > src/userdata_sjis.c iconv -f UTF-8 -t SHIFT-JIS src/userdata.c > src/userdata_sjis.c
mem_init/flash.hex: sys_controller.elf mem_init/flash.hex: sys_controller.elf
$(RV_OBJCOPY) --change-addresses -0x02050000 -O binary --gap-fill 0 $< mem_init/flash.bin $(RV_OBJCOPY) --change-addresses -0x020D0000 -O binary --gap-fill 0 $< mem_init/flash.bin
$(RV_OBJCOPY) --change-addresses -0x02050000 -O ihex --gap-fill 0 $< mem_init/flash.hex $(RV_OBJCOPY) --change-addresses -0x020D0000 -O ihex --gap-fill 0 $< mem_init/flash.hex
mkdir -p mem_init/chunks mkdir -p mem_init/chunks
rm -f mem_init/chunks/* rm -f mem_init/chunks/*
split -d -b 1024 -a 4 mem_init/flash.bin mem_init/chunks/flash. split -d -b 1024 -a 4 mem_init/flash.bin mem_init/chunks/flash.

2
software/sys_controller/link.common.ld
View File

@ -8,7 +8,7 @@ __DYNAMIC = 0;
Last 16 flash sectors reserved for userdata (16x 64KB). */ Last 16 flash sectors reserved for userdata (16x 64KB). */
MEMORY MEMORY
{ {
flash_imem : ORIGIN = 0x02050000, LENGTH = 196608 flash_imem : ORIGIN = 0x020D0000, LENGTH = 196608
dataram : ORIGIN = 0x00010000, LENGTH = 16384 dataram : ORIGIN = 0x00010000, LENGTH = 16384
} }

2
tools/create_fw_img.c
View File

@ -161,7 +161,7 @@ int main(int argc, char **argv)
return -1; return -1;
} }
snprintf(hdr.fw_key, FW_KEY_SIZE+1, "OSSC"); snprintf(hdr.fw_key, FW_KEY_SIZE+1, "OSS2");
hdr.version_major = (uint8_t)fw_version_major; hdr.version_major = (uint8_t)fw_version_major;
hdr.version_minor = (uint8_t)fw_version_minor; hdr.version_minor = (uint8_t)fw_version_minor;
snprintf(hdr.version_suffix, FW_SUFFIX_MAX_SIZE, legacy_mode ? ((argc == 4) ? argv[3] : "") : ((argc == 6) ? argv[5] : "")); snprintf(hdr.version_suffix, FW_SUFFIX_MAX_SIZE, legacy_mode ? ((argc == 4) ? argv[3] : "") : ((argc == 6) ? argv[5] : ""));