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scanlines generation via multiplication

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borti4938 2018-02-09 12:44:55 +01:00
parent 9a2c9bb020
commit 5249d313d8
8 changed files with 290 additions and 45 deletions
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5
ip/lpm_mult_4_sl/lpm_mult_4_sl.qip Normal file
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@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_sl.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_sl_bb.v"]

116
ip/lpm_mult_4_sl/lpm_mult_4_sl.v Normal file
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@ -0,0 +1,116 @@
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: lpm_mult_4_sl.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module lpm_mult_4_sl (
clock,
dataa,
datab,
result);
input clock;
input [7:0] dataa;
input [3:0] datab;
output [7:0] result;
wire [7:0] sub_wire0;
wire [7:0] result = sub_wire0[7:0];
lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 8,
lpm_mult_component.lpm_widthb = 4,
lpm_mult_component.lpm_widthp = 8;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "0"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "8"
// Retrieval info: PRIVATE: WidthB NUMERIC "4"
// Retrieval info: PRIVATE: WidthP NUMERIC "8"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "8"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
// Retrieval info: USED_PORT: datab 0 0 4 0 INPUT NODEFVAL "datab[3..0]"
// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
// Retrieval info: CONNECT: @datab 0 0 4 0 datab 0 0 4 0
// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl_bb.v TRUE
// Retrieval info: LIB_FILE: lpm

89
ip/lpm_mult_4_sl/lpm_mult_4_sl_bb.v Normal file
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@ -0,0 +1,89 @@
// megafunction wizard: %LPM_MULT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: lpm_mult_4_sl.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
module lpm_mult_4_sl (
clock,
dataa,
datab,
result);
input clock;
input [7:0] dataa;
input [3:0] datab;
output [7:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "0"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "8"
// Retrieval info: PRIVATE: WidthB NUMERIC "4"
// Retrieval info: PRIVATE: WidthP NUMERIC "8"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "8"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
// Retrieval info: USED_PORT: datab 0 0 4 0 INPUT NODEFVAL "datab[3..0]"
// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
// Retrieval info: CONNECT: @datab 0 0 4 0 datab 0 0 4 0
// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_sl_bb.v TRUE
// Retrieval info: LIB_FILE: lpm

3
ossc.qsf
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@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE15E22C8
set_global_assignment -name TOP_LEVEL_ENTITY ossc
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03 MAY 17, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@ -243,4 +243,5 @@ set_global_assignment -name QIP_FILE rtl/pll_2x.qip
set_global_assignment -name QIP_FILE rtl/pll_3x.qip
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
set_global_assignment -name QIP_FILE ip/lpm_mult_4_sl/lpm_mult_4_sl.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

107
rtl/scanconverter.v
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@ -97,16 +97,16 @@ wire linebuf_rdclock;
wire [7:0] R_act, G_act, B_act;
wire [7:0] R_lbuf, G_lbuf, B_lbuf;
reg [7:0] R_in_L, G_in_L, B_in_L, R_in_LL, G_in_LL, B_in_LL, R_1x, G_1x, B_1x;
reg [7:0] R_pp3, G_pp3, B_pp3, R_pp4, G_pp4, B_pp4, R_pp5, G_pp5, B_pp5, R_pp6, G_pp6, B_pp6;
reg [7:0] R_pp3, G_pp3, B_pp3, R_pp4, G_pp4, B_pp4, R_pp5, G_pp5, B_pp5, R_pp6, G_pp6, B_pp6, R_pp7, G_pp7, B_pp7;
reg [7:0] R_prev_pp2, G_prev_pp2, B_prev_pp2, R_prev_pp3, G_prev_pp3, B_prev_pp3, R_prev_pp4, G_prev_pp4, B_prev_pp4;
reg signed [14:0] R_diff_pp3, G_diff_pp3, B_diff_pp3, R_diff_pp4, G_diff_pp4, B_diff_pp4;
//H+V syncs + data enable signals&registers
wire HSYNC_act, VSYNC_act, DE_act;
reg HSYNC_in_L, VSYNC_in_L;
reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_4x, HSYNC_5x, HSYNC_pp1, HSYNC_pp2, HSYNC_pp3, HSYNC_pp4, HSYNC_pp5, HSYNC_pp6;
reg VSYNC_1x, VSYNC_2x, VSYNC_3x, VSYNC_4x, VSYNC_5x, VSYNC_pp1, VSYNC_pp2, VSYNC_pp3, VSYNC_pp4, VSYNC_pp5, VSYNC_pp6;
reg DE_1x, DE_2x, DE_3x, DE_4x, DE_5x, DE_pp1, DE_pp2, DE_pp3, DE_pp4, DE_pp5, DE_pp6, DE_3x_prev4x;
reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_4x, HSYNC_5x, HSYNC_pp1, HSYNC_pp2, HSYNC_pp3, HSYNC_pp4, HSYNC_pp5, HSYNC_pp6, HSYNC_pp7;
reg VSYNC_1x, VSYNC_2x, VSYNC_3x, VSYNC_4x, VSYNC_5x, VSYNC_pp1, VSYNC_pp2, VSYNC_pp3, VSYNC_pp4, VSYNC_pp5, VSYNC_pp6, VSYNC_pp7;
reg DE_1x, DE_2x, DE_3x, DE_4x, DE_5x, DE_pp1, DE_pp2, DE_pp3, DE_pp4, DE_pp5, DE_pp6, DE_pp7, DE_3x_prev4x;
//registers indicating line/frame change and field type
reg FID_cur, FID_prev, FID_1x;
@ -128,8 +128,8 @@ reg line_idx;
reg [1:0] line_out_idx_2x, line_out_idx_3x, line_out_idx_4x;
reg [2:0] line_out_idx_5x;
reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x;
reg border_enable_pp1, border_enable_pp2, border_enable_pp3, border_enable_pp4, border_enable_pp5, border_enable_pp6;
reg lt_box_enable_pp1, lt_box_enable_pp2, lt_box_enable_pp3, lt_box_enable_pp4, lt_box_enable_pp5, lt_box_enable_pp6;
reg border_enable_pp1, border_enable_pp2, border_enable_pp3, border_enable_pp4, border_enable_pp5, border_enable_pp6, border_enable_pp7;
reg lt_box_enable_pp1, lt_box_enable_pp2, lt_box_enable_pp3, lt_box_enable_pp4, lt_box_enable_pp5, lt_box_enable_pp6, lt_box_enable_pp7;
wire rlpf_trigger_act;
reg rlpf_trigger_pp1;
@ -161,7 +161,9 @@ reg [2:0] H_OPT_SAMPLE_MULT;
reg [2:0] H_OPT_SAMPLE_SEL;
reg [9:0] H_L5BORDER;
reg [3:0] X_MASK_BR;
reg [7:0] X_SCANLINESTR;
reg X_SCANLINESTR_METHOD;
reg [7:0] X_SCANLINESTR_SUB;
reg [3:0] X_SCANLINESTR_MULT;
reg [5:0] X_REV_LPF_STR;
reg X_REV_LPF_ENABLE;
@ -176,25 +178,32 @@ assign PCLK_out = pclk_act;
assign pclk_lock = {pclk_2x_lock, pclk_3x_lock};
//Scanline generation
function [7:0] apply_scanlines;
input [1:0] mode;
input [7:0] data;
input [7:0] str;
input [4:0] mask;
input [2:0] line_id;
input [2:0] col_id;
input fid;
begin
if ((mode == `SCANLINES_H) && (mask & (5'h1<<line_id)))
apply_scanlines = (data > str) ? (data-str) : 8'h00;
else if ((mode == `SCANLINES_V) && (5'h0 == col_id))
apply_scanlines = (data > str) ? (data-str) : 8'h00;
else if ((mode == `SCANLINES_ALT) && (mask & (5'h1<<(line_id^fid))))
apply_scanlines = (data > str) ? (data-str) : 8'h00;
else
apply_scanlines = data;
end
endfunction
wire [7:0] R_sl_mult, G_sl_mult, B_sl_mult;
lpm_mult_4_sl R_sl_mult_u
(
.clock(pclk_act),
.dataa(R_pp5),
.datab(X_SCANLINESTR_MULT),
.result(R_sl_mult)
);
lpm_mult_4_sl G_sl_mult_u
(
.clock(pclk_act),
.dataa(G_pp5),
.datab(X_SCANLINESTR_MULT),
.result(G_sl_mult)
);
lpm_mult_4_sl B_sl_mult_u
(
.clock(pclk_act),
.dataa(B_pp5),
.datab(X_SCANLINESTR_MULT),
.result(B_sl_mult)
);
reg [7:0] R_sl_sub, G_sl_sub, B_sl_sub;
reg draw_sl;
//LT box / border generation
function [7:0] apply_mask;
@ -435,6 +444,7 @@ linebuf linebuf_rgb (
// line_id, col_id: 0 cycles
// HSYNC, VSYNC, DE: 1 cycle
// RGB: 2 cycles
always @(posedge pclk_act)
begin
line_id_pp1 <= line_id_act;
@ -504,21 +514,37 @@ begin
border_enable_pp5 <= border_enable_pp4;
lt_box_enable_pp5 <= lt_box_enable_pp4;
R_pp6 <= apply_scanlines(V_SCANLINEMODE, R_pp5, X_SCANLINESTR, V_SCANLINEID, line_id_pp5, col_id_pp5, FID_1x);
G_pp6 <= apply_scanlines(V_SCANLINEMODE, G_pp5, X_SCANLINESTR, V_SCANLINEID, line_id_pp5, col_id_pp5, FID_1x);
B_pp6 <= apply_scanlines(V_SCANLINEMODE, B_pp5, X_SCANLINESTR, V_SCANLINEID, line_id_pp5, col_id_pp5, FID_1x);
R_pp6 <= R_pp5;
G_pp6 <= G_pp5;
B_pp6 <= B_pp5;
// R_sl_mult, G_sl_mult and B_sl_mult are registered output of IP blocks (line 182-203)
R_sl_sub <= (R_pp5 > X_SCANLINESTR_SUB) ? (R_pp5-X_SCANLINESTR_SUB) : 8'h00;
G_sl_sub <= (G_pp5 > X_SCANLINESTR_SUB) ? (G_pp5-X_SCANLINESTR_SUB) : 8'h00;
B_sl_sub <= (B_pp5 > X_SCANLINESTR_SUB) ? (B_pp5-X_SCANLINESTR_SUB) : 8'h00;
draw_sl <= |{(V_SCANLINEMODE == `SCANLINES_H) && (V_SCANLINEID & (5'h1<<line_id_pp5)),
(V_SCANLINEMODE == `SCANLINES_V) && (5'h0 == col_id_pp5),
(V_SCANLINEMODE == `SCANLINES_ALT) && (V_SCANLINEID & (5'h1<<(line_id_pp5^FID_1x)))};
HSYNC_pp6 <= HSYNC_pp5;
VSYNC_pp6 <= VSYNC_pp5;
DE_pp6 <= DE_pp5;
border_enable_pp6 <= border_enable_pp5;
lt_box_enable_pp6 <= lt_box_enable_pp5;
R_out <= apply_mask(lt_active, lt_box_enable_pp6, border_enable_pp6, R_pp6, X_MASK_BR);
G_out <= apply_mask(lt_active, lt_box_enable_pp6, border_enable_pp6, G_pp6, X_MASK_BR);
B_out <= apply_mask(lt_active, lt_box_enable_pp6, border_enable_pp6, B_pp6, X_MASK_BR);
HSYNC_out <= HSYNC_pp6;
VSYNC_out <= VSYNC_pp6;
DE_out <= DE_pp6;
R_pp7 <= draw_sl ? (X_SCANLINESTR_METHOD ? R_sl_sub : R_sl_mult) : R_pp6;
G_pp7 <= draw_sl ? (X_SCANLINESTR_METHOD ? G_sl_sub : G_sl_mult) : G_pp6;
B_pp7 <= draw_sl ? (X_SCANLINESTR_METHOD ? B_sl_sub : B_sl_mult) : B_pp6;
HSYNC_pp7 <= HSYNC_pp6;
VSYNC_pp7 <= VSYNC_pp6;
DE_pp7 <= DE_pp6;
border_enable_pp7 <= border_enable_pp6;
lt_box_enable_pp7 <= lt_box_enable_pp6;
R_out <= apply_mask(lt_active, lt_box_enable_pp7, border_enable_pp7, R_pp7, X_MASK_BR);
G_out <= apply_mask(lt_active, lt_box_enable_pp7, border_enable_pp7, G_pp7, X_MASK_BR);
B_out <= apply_mask(lt_active, lt_box_enable_pp7, border_enable_pp7, B_pp7, X_MASK_BR);
HSYNC_out <= HSYNC_pp7;
VSYNC_out <= VSYNC_pp7;
DE_out <= DE_pp7;
end
//Generate a warning signal from horizontal instability or PLL sync loss
@ -688,11 +714,14 @@ begin
H_OPT_SAMPLE_MULT <= h_info2[12:10];
H_OPT_STARTOFF <= h_info2[9:0];
X_REV_LPF_ENABLE <= (extra_info[12:8] != 5'b00000);
X_REV_LPF_STR <= (extra_info[12:8] + 6'd16);
X_REV_LPF_ENABLE <= (extra_info[13:9] != 5'b00000);
X_REV_LPF_STR <= (extra_info[13:9] + 6'd16);
X_MASK_BR <= extra_info[7:4];
X_SCANLINESTR <= ((extra_info[3:0]+8'h01)<<4)-1'b1;
X_MASK_BR <= extra_info[8:5];
X_SCANLINESTR_METHOD <= extra_info[4];
X_SCANLINESTR_SUB <= ((extra_info[3:0]+8'h01)<<4)-1'b1;
X_SCANLINESTR_MULT <= ~extra_info[3:0];
end
R_in_L <= R_in;

12
software/sys_controller/ossc/av_controller.c
View File

@ -301,6 +301,7 @@ status_t get_status(tvp_input_t input, video_format format)
if ((tc.sl_mode != cm.cc.sl_mode) ||
(tc.sl_type != cm.cc.sl_type) ||
(tc.sl_method != cm.cc.sl_method) ||
(tc.sl_str != cm.cc.sl_str) ||
(tc.sl_id != cm.cc.sl_id) ||
(tc.h_mask != cm.cc.h_mask) ||
@ -365,8 +366,8 @@ status_t get_status(tvp_input_t input, video_format format)
// v_info: [31:29] [28:27] [26] [25:20] [19:17] [16:11] [10:0]
// | V_MULTMODE[2:0] | V_SCANLINEMODE[1:0] | V_SCANLINEID | V_MASK[5:0] | V_SYNCLEN[2:0] | V_BACKPORCH[5:0] | V_ACTIVE[10:0] |
//
// extra: [31:13] [12:8] [7:4] [3:0]
// | | X_REV_LPF_STR | H_MASK_BR[3:0] | H_SCANLINESTR[3:0] |
// extra: [31:14] [13:9] [8:5] [4] [3:0]
// | | X_REV_LPF_STR | H_MASK_BR[3:0] | H_SCANLINESTR_TYPE | H_SCANLINESTR[3:0] |
//
void set_videoinfo()
{
@ -461,9 +462,10 @@ void set_videoinfo()
(video_modes[cm.id].v_synclen<<17) |
(v_backporch<<11) |
v_active);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_6_BASE, (cm.cc.reverse_lpf<<8) |
(cm.cc.mask_br<<4) |
cm.cc.sl_str);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_6_BASE, (cm.cc.reverse_lpf<<9) |
(cm.cc.mask_br<<5) |
(cm.cc.sl_method << 4) |
cm.cc.sl_str);
}
// Configure TVP7002 and scan converter logic based on the video mode

1
software/sys_controller/ossc/avconfig.h
View File

@ -45,6 +45,7 @@
typedef struct {
alt_u8 sl_mode;
alt_u8 sl_type;
alt_u8 sl_method;
alt_u8 sl_str;
alt_u8 sl_id;
alt_u8 linemult_target;

2
software/sys_controller/ossc/menu.c
View File

@ -60,6 +60,7 @@ static const char *pm_1080i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Li
static const char *ar_256col_desc[] = { "4:3", "8:7" };
static const char *tx_mode_desc[] = { "HDMI", "DVI" };
static const char *sl_mode_desc[] = { LNG("Off","ｵﾌ"), LNG("Auto","ｵｰﾄ"), LNG("Manual","ｶｽﾀﾑ") };
static const char *sl_method_desc[] = { LNG("Multiplication","Multiplication"), LNG("Subtraction","Subtraction") };
static const char *sl_type_desc[] = { LNG("Horizontal","ﾖｺ"), LNG("Vertical","ﾀﾃ"), LNG("Alternating","ｺｳｺﾞ") };
static const char *sl_id_desc[] = { LNG("Top","ｳｴ"), LNG("Bottom","ｼﾀ") };
static const char *audio_dw_sampl_desc[] = { LNG("Off (fs = 96kHz)","ｵﾌ (fs = 96kHz)"), "2x (fs = 48kHz)" };
@ -139,6 +140,7 @@ MENU(menu_output, P99_PROTECT({ \
MENU(menu_postproc, P99_PROTECT({ \
{ LNG("Scanlines","ｽｷｬﾝﾗｲﾝ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.sl_mode, OPT_WRAP, SETTING_ITEM(sl_mode_desc) } } },
{ LNG("Scanline str.","ｽｷｬﾝﾗｲﾝﾂﾖｻ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.sl_str, OPT_NOWRAP, 0, SCANLINESTR_MAX, sl_str_disp } } },
{ LNG("Scanline method","Scanline method"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.sl_method, OPT_WRAP, SETTING_ITEM(sl_method_desc) } } },
{ LNG("Scanline type","ｽｷｬﾝﾗｲﾝﾙｲ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.sl_type, OPT_WRAP, SETTING_ITEM(sl_type_desc) } } },
{ LNG("Scanline alignm.","ｽｷｬﾝﾗｲﾝﾎﾟｼﾞｼｮﾝ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.sl_id, OPT_WRAP, SETTING_ITEM(sl_id_desc) } } },
{ LNG("Horizontal mask","ｽｲﾍｲﾏｽｸ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.h_mask, OPT_NOWRAP, 0, HV_MASK_MAX, pixels_disp } } },