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Improve input mode handling

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* New options and better compatibility for Line5x
* Add support for 960i and 1080i
* Make TVP HPLL2x option user-selectable
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marqs committed 2017-02-07 23:04:30 +02:00
1 parent 3b19b2843c
commit 6e043ef577
17 files changed
+1264 -1145
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ossc.sdc
+2 -2
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@@ -10,10 +10,10 @@ set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
### Scanconverter clock constraints ###
create_clock -period 108MHz -name pclk_hdtv [get_ports PCLK_in]
create_clock -period 13.5MHz -name pclk_sdtv_L2 [get_ports PCLK_in] -add
create_clock -period 27MHz -name pclk_sdtv_L2 [get_ports PCLK_in] -add
create_clock -period 27MHz -name pclk_sdtv_L3 [get_ports PCLK_in] -add
create_clock -period 27MHz -name pclk_sdtv_L4 [get_ports PCLK_in] -add
create_clock -period 16MHz -name pclk_sdtv_L5 [get_ports PCLK_in] -add
create_clock -period 27MHz -name pclk_sdtv_L5 [get_ports PCLK_in] -add
#derive_pll_clocks
create_generated_clock -master_clock pclk_sdtv_L2 -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}