RomanRom2/ossc
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* L3 optimized mode scanlines fixed

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* Advanced timing tweaker implemented
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marqs committed 2016-08-16 22:45:23 +03:00
1 parent a488422089
commit 827df7930f
13 files changed
+1058 -892
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ossc.sdc
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@@ -77,7 +77,7 @@ set_false_path -from pclk_3x_M1 -through $clkmuxnodes -to pclk_4x_M1
set_false_path -from [get_cells {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter:scanconverter_inst|lines_*}]
# Ignore paths from registers which are updated only at the end of hsync
set_false_path -from [get_cells {scanconverter:scanconverter_inst|vcnt_* scanconverter:scanconverter_inst|line_idx}]
set_false_path -from [get_cells {scanconverter:scanconverter_inst|vcnt_* scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx*}]
# Ignore following clock transfers
set_false_path -from [get_clocks pclk_2x] -to [get_clocks pclk_sdtv]