RomanRom2/ossc
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mirror of https://github.com/marqs85/ossc synced 2026-11-01 20:57:10 +03:00
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* L3 optimized mode scanlines fixed

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* Advanced timing tweaker implemented
This commit is contained in:
marqs committed 2016-08-16 22:45:23 +03:00
1 parent a488422089
commit 827df7930f
13 files changed
+1058 -892
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rtl/ossc.v
+26 -1
View File
@@ -18,6 +18,7 @@
//
//`define DEBUG
//`define INPUTLATCH
`define VIDEOGEN
module ossc (
@@ -83,6 +84,21 @@ wire [7:0] lcd_ctrl;
reg [3:0] reset_n_ctr;
reg reset_n_reg = 1'b1;
`ifdef INPUTLATCH
reg HSYNC_in_l, VSYNC_in_l, FID_in_l;
reg [7:0] R_in_l, G_in_l, B_in_l;
always @(posedge PCLK_in)
begin
HSYNC_in_l <= HSYNC_in;
VSYNC_in_l <= VSYNC_in;
FID_in_l <= FID_in;
R_in_l <= R_in;
G_in_l <= G_in;
B_in_l <= B_in;
end
`endif
`ifdef DEBUG
assign LED_R = HSYNC_in;
assign LED_G = VSYNC_in;
@@ -149,13 +165,22 @@ sys sys_inst(
scanconverter scanconverter_inst (
.reset_n (reset_n),
.PCLK_in (PCLK_in),
`ifdef INPUTLATCH
.HSYNC_in (HSYNC_in_l),
.VSYNC_in (VSYNC_in_l),
.FID_in (FID_in_l),
.R_in (R_in_l),
.G_in (G_in_l),
.B_in (B_in_l),
`else
.HSYNC_in (HSYNC_in),
.VSYNC_in (VSYNC_in),
.PCLK_in (PCLK_in),
.FID_in (FID_in),
.R_in (R_in),
.G_in (G_in),
.B_in (B_in),
`endif
.h_info (h_info),
.v_info (v_info),
.R_out (R_out),
rtl/scanconverter.v
+14 -5
View File
@@ -120,7 +120,7 @@ reg h_enable_3x, h_enable_3x_h1x, v_enable_3x, v_enable_3x_h1x;
reg prev_hs, prev_vs;
reg [11:0] hmax[0:1];
reg line_idx;
reg [1:0] line_out_idx_2x, line_out_idx_3x;
reg [1:0] line_out_idx_2x, line_out_idx_3x, line_out_idx_3x_h1x;
reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x, warn_pll_lock_lost_3x_lowfreq;
@@ -141,7 +141,6 @@ reg [7:0] R_1x, G_1x, B_1x, R_pp1, G_pp1, B_pp1;
wire [7:0] R_lbuf, G_lbuf, B_lbuf;
wire [7:0] R_act, G_act, B_act;
assign pclk_1x = PCLK_in;
assign pclk_lock = {pclk_2x_lock, pclk_3x_lock, pclk_3x_lowfreq_lock};
@@ -246,7 +245,6 @@ begin
G_act = G_lbuf;
B_act = B_lbuf;
VSYNC_act = VSYNC_1x;
slid_act = line_out_idx_3x;
case (H_L3MODE)
`LINETRIPLE_M0: begin
DATA_enable_act = (h_enable_3x & v_enable_3x);
@@ -256,6 +254,7 @@ begin
linebuf_rdclock = pclk_3x;
linebuf_hoffset = hcnt_3x;
pclk_act = pclk_3x;
slid_act = line_out_idx_3x;
hcnt_act = hcnt_3x;
vcnt_act = vcnt_3x/2'h3; //divider generated
end
@@ -267,6 +266,7 @@ begin
linebuf_rdclock = pclk_4x;
linebuf_hoffset = hcnt_4x;
pclk_act = pclk_4x;
slid_act = line_out_idx_3x;
hcnt_act = hcnt_4x;
vcnt_act = vcnt_3x/2'h3; //divider generated
end
@@ -278,6 +278,7 @@ begin
linebuf_rdclock = pclk_3x_h4x;
linebuf_hoffset = hcnt_3x_h4x;
pclk_act = pclk_3x_h4x;
slid_act = line_out_idx_3x_h1x;
hcnt_act = hcnt_3x_h4x;
vcnt_act = vcnt_3x_h1x/2'h3; //divider generated
end
@@ -289,6 +290,7 @@ begin
linebuf_rdclock = pclk_3x_h5x;
linebuf_hoffset = hcnt_3x_h5x;
pclk_act = pclk_3x_h5x;
slid_act = line_out_idx_3x_h1x;
hcnt_act = hcnt_3x_h5x;
vcnt_act = vcnt_3x_h1x/2'h3; //divider generated
end
@@ -682,13 +684,20 @@ begin
v_enable_3x_h1x <= 0;
pclk_3x_h1x_cnt <= 0;
pclk_1x_prev3x_h1x <= 0;
line_out_idx_3x_h1x <= 0;
end
else
begin
if ((pclk_3x_h1x_cnt == 0) & `HSYNC_TRAILING_EDGE) //sync with posedge of pclk_1x
hcnt_3x_h1x <= 0;
begin
hcnt_3x_h1x <= 0;
line_out_idx_3x_h1x <= 0;
end
else if (hcnt_3x_h1x == hmax[~line_idx]) //line_idx_prev?
hcnt_3x_h1x <= 0;
begin
hcnt_3x_h1x <= 0;
line_out_idx_3x_h1x <= line_out_idx_3x_h1x + 1'b1;
end
else
hcnt_3x_h1x <= hcnt_3x_h1x + 1'b1;