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optimize away one pp stage and unify code formatting
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@@ -73,7 +73,7 @@ set_clock_groups -asynchronous -group \
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{pclk_5x_source pclk_5x pclk_5x_postmux pclk_5x_out}
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# Ignore paths from registers which are updated only at leading edge of vsync
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set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|FID_1x}]
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set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|LT_POS_* scanconverter_inst|FID_1x}]
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# Ignore paths from registers which are updated only at leading edge of hsync
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set_false_path -from [get_registers {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|hmax*}]
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