RomanRom2/ossc
1
0
Fork 0
mirror of https://github.com/marqs85/ossc synced 2025-10-25 21:16:03 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity

optimize away one pp stage and unify code formatting

Browse Source
This commit is contained in:
marqs 2018-03-12 01:24:17 +02:00
parent 77d122940b
commit 9ad696dbc3
8 changed files with 1304 additions and 1299 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
ossc.qsf
View File

@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE15E22C8
set_global_assignment -name TOP_LEVEL_ENTITY ossc
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03 MAY 17, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Lite Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@ -224,7 +224,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name SEED 16
set_global_assignment -name SEED 3
set_global_assignment -name VERILOG_FILE rtl/videogen.v

2
ossc.sdc
View File

@ -73,7 +73,7 @@ set_clock_groups -asynchronous -group \
{pclk_5x_source pclk_5x pclk_5x_postmux pclk_5x_out}
# Ignore paths from registers which are updated only at leading edge of vsync
set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|FID_1x}]
set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|LT_POS_* scanconverter_inst|FID_1x}]
# Ignore paths from registers which are updated only at leading edge of hsync
set_false_path -from [get_registers {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|hmax*}]

69
rtl/scanconverter.v
View File

@ -70,11 +70,11 @@
`define PP_RLPF_PL_START 3 // minimum 2
`define PP_RLPF_PL_LENGTH 3 // counted from aquisition
`define PP_SLGEN_PL_LENGTH 5
`define PP_LT_BORDER_GEN_LENGTH 2
`define PP_LT_BORDER_GEN_LENGTH 1 // lt_box / border_mask gen
`define PP_RLPF_PL_END (`PP_RLPF_PL_START+`PP_RLPF_PL_LENGTH)
`define PP_SLGEN_PL_END (`PP_RLPF_PL_END+`PP_SLGEN_PL_LENGTH)
`define PP_PIPELINE_LENGTH (`PP_SLGEN_PL_END+`PP_LT_BORDER_GEN_LENGTH)
`define PP_PIPELINE_LENGTH (`PP_SLGEN_PL_END+`PP_LT_BORDER_GEN_LENGTH-1'b1)
module scanconverter (
input reset_n,
@ -146,17 +146,17 @@ reg [2:0] line_out_idx_5x;
reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x;
// post-processing pipeline
reg HSYNC_pp[1:`PP_PIPELINE_LENGTH-1] /* synthesis ramstyle = "logic" */;
reg VSYNC_pp[1:`PP_PIPELINE_LENGTH-1] /* synthesis ramstyle = "logic" */;
reg DE_pp[1:`PP_PIPELINE_LENGTH-1] /* synthesis ramstyle = "logic" */;
reg [7:0] R_pp[3:`PP_PIPELINE_LENGTH-1], G_pp[3:`PP_PIPELINE_LENGTH-1], B_pp[3:`PP_PIPELINE_LENGTH-1] /* synthesis ramstyle = "logic" */;
reg HSYNC_pp[1:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */;
reg VSYNC_pp[1:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */;
reg DE_pp[1:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */;
reg [7:0] R_pp[3:`PP_PIPELINE_LENGTH], G_pp[3:`PP_PIPELINE_LENGTH], B_pp[3:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */;
reg [11:0] hcnt_pp /* synthesis ramstyle = "logic" */;
reg [10:0] vcnt_pp /* synthesis ramstyle = "logic" */;
reg rlpf_trigger_r[1:`PP_RLPF_PL_START-1] /* synthesis ramstyle = "logic" */;
reg [7:0] R_prev_pp[`PP_RLPF_PL_START:`PP_RLPF_PL_END-1], G_prev_pp[`PP_RLPF_PL_START:`PP_RLPF_PL_END-1], B_prev_pp[`PP_RLPF_PL_START:`PP_RLPF_PL_END-1] /* synthesis ramstyle = "logic" */;
reg [2:0] line_id_pp[1:`PP_SLGEN_PL_END-2], col_id_pp[1:`PP_SLGEN_PL_END-2] /* synthesis ramstyle = "logic" */;
reg border_enable_pp[2:`PP_PIPELINE_LENGTH-2] /* synthesis ramstyle = "logic" */;
reg lt_box_enable_pp[2:`PP_PIPELINE_LENGTH-1] /* synthesis ramstyle = "logic" */;
reg border_enable_pp[2:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */;
reg lt_box_enable_pp[2:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */;
//helper registers for sampling at synchronized clock edges
reg pclk_1x_prev3x;
@ -328,7 +328,7 @@ function [7:0] apply_reverse_lpf;
result = {3'b0,data_prev} + ~diff[14:4]; // allow for a small error to reduce adder length
apply_reverse_lpf = result[10] ? 8'h00 : |result[9:8] ? 8'hFF : result[7:0];
end
endfunction
endfunction
//Mux for active data selection
@ -509,7 +509,16 @@ mux5 mux5_inst (
// line_id, col_id: 0 cycles
// HSYNC, VSYNC, DE: 1 cycle
// RGB: 2 cycles
//
// Pipeline structure
// | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
// |-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
// | LBUF | LBUF | | | | | | | | | |
// | | | RLPF | RLPF | RLPF | | | | | | |
// | | | | Y | Y | | | | | | |
// | | | | | | SLG | SLG | SLG | SLG | SLG | |
// | | | | | | | | | | | MASK |
// | | | | | | | | | | | LTBOX |
integer pp_idx;
always @(posedge pclk_act)
begin
@ -523,7 +532,7 @@ begin
hcnt_pp <= hcnt_act;
vcnt_pp <= vcnt_act;
border_enable_pp[2] <= ((hcnt_pp < H_AVIDMASK_START) | (hcnt_pp >= H_AVIDMASK_STOP) | (vcnt_pp < V_AVIDMASK_START) | (vcnt_pp >= V_AVIDMASK_STOP));
for(pp_idx = 3; pp_idx <= `PP_PIPELINE_LENGTH-2; pp_idx = pp_idx+1) begin
for(pp_idx = 3; pp_idx <= `PP_PIPELINE_LENGTH; pp_idx = pp_idx+1) begin
border_enable_pp[pp_idx] <= border_enable_pp[pp_idx-1];
end
@ -541,35 +550,34 @@ begin
lt_box_enable_pp[2] <= ((hcnt_pp >= LT_POS_BOTTOMRIGHT_H_START) && (vcnt_pp >= LT_POS_BOTTOMRIGHT_V_START)) ? 1'b1 : 1'b0;
end
endcase
for(pp_idx = 3; pp_idx <= `PP_PIPELINE_LENGTH-1; pp_idx = pp_idx+1) begin
for(pp_idx = 3; pp_idx <= `PP_PIPELINE_LENGTH; pp_idx = pp_idx+1) begin
lt_box_enable_pp[pp_idx] <= lt_box_enable_pp[pp_idx-1];
end
HSYNC_pp[2] <= HSYNC_act;
VSYNC_pp[2] <= VSYNC_act;
DE_pp[2] <= DE_act;
for(pp_idx = 3; pp_idx <= `PP_PIPELINE_LENGTH-1; pp_idx = pp_idx+1) begin
for(pp_idx = 3; pp_idx <= `PP_PIPELINE_LENGTH; pp_idx = pp_idx+1) begin
HSYNC_pp[pp_idx] <= HSYNC_pp[pp_idx-1];
VSYNC_pp[pp_idx] <= VSYNC_pp[pp_idx-1];
DE_pp[pp_idx] <= DE_pp[pp_idx-1];
end
HSYNC_out <= HSYNC_pp[`PP_PIPELINE_LENGTH-1];
VSYNC_out <= VSYNC_pp[`PP_PIPELINE_LENGTH-1];
DE_out <= DE_pp[`PP_PIPELINE_LENGTH-1];
HSYNC_out <= HSYNC_pp[`PP_PIPELINE_LENGTH];
VSYNC_out <= VSYNC_pp[`PP_PIPELINE_LENGTH];
DE_out <= DE_pp[`PP_PIPELINE_LENGTH];
// get RGB and delay it
R_pp[3] <= R_act;
G_pp[3] <= G_act;
B_pp[3] <= B_act;
for(pp_idx = 4; pp_idx <= `PP_PIPELINE_LENGTH-1; pp_idx = pp_idx + 1) begin
for(pp_idx = 4; pp_idx <= `PP_PIPELINE_LENGTH; pp_idx = pp_idx + 1) begin
R_pp[pp_idx] <= R_pp[pp_idx-1];
G_pp[pp_idx] <= G_pp[pp_idx-1];
B_pp[pp_idx] <= B_pp[pp_idx-1];
end
R_out <= R_pp[`PP_PIPELINE_LENGTH-1];
G_out <= G_pp[`PP_PIPELINE_LENGTH-1];
B_out <= B_pp[`PP_PIPELINE_LENGTH-1];
R_out <= R_pp[`PP_PIPELINE_LENGTH];
G_out <= G_pp[`PP_PIPELINE_LENGTH];
B_out <= B_pp[`PP_PIPELINE_LENGTH];
// reverse LPF ...
rlpf_trigger_r[1] <= rlpf_trigger_act;
@ -652,18 +660,15 @@ begin
B_pp[`PP_SLGEN_PL_END] <= X_SCANLINE_METHOD ? B_sl_sub : B_sl_mult;
end
// apply mask (border generation)
if (border_enable_pp[`PP_PIPELINE_LENGTH-2]) begin
R_pp[`PP_PIPELINE_LENGTH-1] <= {2{X_MASK_BR}};
G_pp[`PP_PIPELINE_LENGTH-1] <= {2{X_MASK_BR}};
B_pp[`PP_PIPELINE_LENGTH-1] <= {2{X_MASK_BR}};
end
// apply LT box
// apply LT box / mask
if (lt_active) begin
R_out <= {8{lt_box_enable_pp[`PP_PIPELINE_LENGTH-1]}};
G_out <= {8{lt_box_enable_pp[`PP_PIPELINE_LENGTH-1]}};
B_out <= {8{lt_box_enable_pp[`PP_PIPELINE_LENGTH-1]}};
R_out <= {8{lt_box_enable_pp[`PP_PIPELINE_LENGTH]}};
G_out <= {8{lt_box_enable_pp[`PP_PIPELINE_LENGTH]}};
B_out <= {8{lt_box_enable_pp[`PP_PIPELINE_LENGTH]}};
end else if (border_enable_pp[`PP_PIPELINE_LENGTH-1]) begin
R_out <= {2{X_MASK_BR}};
G_out <= {2{X_MASK_BR}};
B_out <= {2{X_MASK_BR}};
end
end

2318
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
View File

File diff suppressed because it is too large Load Diff

4
software/sys_controller/ossc/av_controller.c
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015-2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2018 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@ -777,7 +777,7 @@ int main()
printf("### DIY VIDEO DIGITIZER / SCANCONVERTER INIT OK ###\n\n");
sniprintf(row1, LCD_ROW_LEN+1, "OSSC fw. %u.%.2u" FW_SUFFIX1 FW_SUFFIX2, FW_VER_MAJOR, FW_VER_MINOR);
#ifndef DEBUG
strncpy(row2, "2014-2017 marqs", LCD_ROW_LEN+1);
strncpy(row2, "2014-2018 marqs", LCD_ROW_LEN+1);
#else
strncpy(row2, "** DEBUG BUILD *", LCD_ROW_LEN+1);
#endif

2
software/sys_controller/ossc/avconfig.h
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015-2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2018 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//

4
software/sys_controller_bsp/settings.bsp
View File

@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Mar 6, 2018 11:46:21 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1520372781076</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>Mar 12, 2018 12:02:20 AM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1520805740902</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>

4
sys.sopcinfo
View File

@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
<!-- Format version 17.1 590 (Future versions may contain additional information.) -->
<!-- 2018.03.06.23:39:06 -->
<!-- 2018.03.12.00:00:04 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1520372346</value>
<value>1520805604</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>