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optimize clock network

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* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl
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marqs committed 2019-10-06 23:54:32 +03:00
1 parent d1fd30019f
commit 9d496383c3
28 files changed
+8520 -7310
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rtl/pll_2x.ppf
+8
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@@ -3,10 +3,18 @@
<pinplan intended_family="Cyclone IV E" variation_name="pll_2x" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="clkswitch" direction="input" scope="external" />
<pin name="configupdate" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="inclk1" direction="input" scope="external" source="clock" />
<pin name="scanclk" direction="input" scope="external" source="clock" />
<pin name="scanclkena" direction="input" scope="external" />
<pin name="scandata" direction="input" scope="external" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
<pin name="scandataout" direction="output" scope="external" />
<pin name="scandone" direction="output" scope="external" />
</global>
</pinplan>