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optimize clock network

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* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl
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marqs committed 2019-10-06 23:54:32 +03:00
1 parent d1fd30019f
commit 9d496383c3
28 files changed
+8520 -7310
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software/sys_controller_bsp/drivers/inc/pll_reconfig_regs.h
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../../../../ip/pll_reconfig/inc/pll_reconfig_regs.h