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https://github.com/marqs85/ossc
synced 2026-10-30 11:47:26 +03:00
bump sys_ctrl register to 32bit
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@@ -43,7 +43,7 @@ extern avmode_t cm;
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extern avconfig_t tc;
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extern avinput_t target_input;
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extern alt_u8 menu_active;
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extern alt_u16 sys_ctrl;
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extern alt_u32 sys_ctrl;
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extern alt_u16 tc_sampler_phase;
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extern alt_u8 profile_sel, profile_sel_menu;
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extern alt_u8 lcd_bl_timeout;
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@@ -182,7 +182,7 @@ int parse_control()
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sniprintf((char*)osd->osd_array.data[1][0], OSD_CHAR_COLS, "Mode preset:");
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sniprintf((char*)osd->osd_array.data[1][1], OSD_CHAR_COLS, "%s", video_modes[cm.id].name);
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sniprintf((char*)osd->osd_array.data[2][0], OSD_CHAR_COLS, "Imode (FPGA):");
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sniprintf((char*)osd->osd_array.data[2][1], OSD_CHAR_COLS, "%lu-%c%c %lu.%.2luHz", (unsigned long)((sc_status.vmax+1)<<sc_status.interlace_flag)+sc_status.interlace_flag,
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sniprintf((char*)osd->osd_array.data[2][1], OSD_CHAR_COLS, "%lu-%c%c %lu.%.2luHz", (unsigned long)sc_status.vmax,
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sc_status.interlace_flag ? 'i' : 'p',
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sc_status.fpga_vsyncgen ? '*' : ' ',
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fpga_v_hz_x100/100,
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@@ -33,7 +33,7 @@
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extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
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extern alt_u16 rc_keymap[REMOTE_MAX_KEYS];
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extern SD_DEV sdcard_dev;
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extern alt_u16 sys_ctrl;
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extern alt_u32 sys_ctrl;
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static int check_fw_header(alt_u8 *databuf, fw_hdr *hdr)
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{
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@@ -31,7 +31,7 @@
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#define WRDELAY 20
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#define CLEARDELAY 800
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extern alt_u16 sys_ctrl;
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extern alt_u32 sys_ctrl;
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static void lcd_cmd(alt_u8 cmd, alt_u16 postdelay) {
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SPI_write(I2CA_BASE, &cmd, 1);
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@@ -7,7 +7,7 @@
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#include "spi_io.h"
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#include "av_controller.h"
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extern alt_u16 sys_ctrl;
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extern alt_u32 sys_ctrl;
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alt_u32 sd_timer_ts;
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Binary file not shown.
@@ -337,7 +337,7 @@
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#define PIO_0_BIT_CLEARING_EDGE_REGISTER 0
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#define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
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#define PIO_0_CAPTURE 0
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#define PIO_0_DATA_WIDTH 16
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#define PIO_0_DATA_WIDTH 32
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#define PIO_0_DO_TEST_BENCH_WIRING 0
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#define PIO_0_DRIVEN_SIM_VALUE 0
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#define PIO_0_EDGE_TYPE "NONE"
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