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add timeout to pll_reconfig and update postprocess pipeline diagram

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marqs committed 2019-10-07 23:20:44 +03:00
1 parent 3a12592c53
commit b22365af20
3 files changed
+18 -16
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rtl/scanconverter.v
+9 -9
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@@ -549,15 +549,15 @@ linebuf linebuf_rgb (
// RGB: 2 cycles
//
// Pipeline structure
// | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
// |-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
// | LBUF | LBUF | | | | | | | | | |
// | | | RLPF | RLPF | RLPF | | | | | | |
// | | | | Y | Y | | | | | | |
// | | | | | | SLG | SLG | SLG | SLG | SLG | |
// | | | | | | | | | | | MASK |
// | | | | | | | | | | | LTBOX |
// | | | | | | | | | | | OSD |
// | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 |
// |-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
// | RADDR | | | | | | | | | | | |
// | | LBUF | LBUF | | | | | | | | | |
// | | | | RLPF | RLPF | RLPF | | | | | | |
// | | | | | Y | Y | | | | | | |
// | | | | | | | SLG | SLG | SLG | SLG | SLG | |
// | | | | | | | | | | | | MASK |
// | | | | | | | | | | | | LTBOX |
integer pp_idx;
always @(posedge pclk_act)
begin