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add support for shadow masks (up to 4x4)

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This commit is contained in:
marqs 2023-09-22 20:56:51 +03:00
parent 1ba02417d5
commit c0dae3da36
13 changed files with 8697 additions and 8733 deletions
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3
ip/sc_config/inc/sc_config_regs.h
View File

@ -113,7 +113,8 @@ typedef union {
uint8_t vip_enable:1;
uint8_t bfi_str:4;
uint8_t bfi_enable:1;
uint32_t misc_rsv:11;
uint8_t shmask_mode:2;
uint32_t misc_rsv:9;
} __attribute__((packed, __may_alias__));
uint32_t data;
} misc_config_reg;

4
ossc.qsf
View File

@ -243,8 +243,7 @@ set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qi
set_global_assignment -name QIP_FILE rtl/linebuf.qip
set_global_assignment -name QIP_FILE rtl/char_rom.qip
set_global_assignment -name QIP_FILE rtl/pll_2x.qip
set_global_assignment -name QIP_FILE rtl/lpm_mult_hybr_ref_pre.qip
set_global_assignment -name QIP_FILE rtl/lpm_mult_hybr_ref.qip
set_global_assignment -name QIP_FILE rtl/lpm_mult_8x5_9.qip
set_global_assignment -name QIP_FILE rtl/lpm_mult_sl.qip
set_global_assignment -name SDC_FILE ossc.sdc
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
@ -255,4 +254,5 @@ set_global_assignment -name QIP_FILE rtl/char_array.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

2
rtl/lpm_mult_hybr_ref.qip → rtl/lpm_mult_8x5_9.qip
View File

@ -1,4 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
set_global_assignment -name IP_TOOL_VERSION "21.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_hybr_ref.v"]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_8x5_9.v"]

30
rtl/lpm_mult_hybr_ref_pre.v → rtl/lpm_mult_8x5_9.v
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@ -1,10 +1,10 @@
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// MODULE: lpm_mult
// ============================================================
// File Name: lpm_mult_hybr_ref_pre.v
// File Name: lpm_mult_8x5_9.v
// Megafunction Name(s):
// lpm_mult
//
@ -19,12 +19,12 @@
//Copyright (C) 2021 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
@ -37,7 +37,7 @@
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module lpm_mult_hybr_ref_pre (
module lpm_mult_8x5_9 (
clock,
dataa,
datab,
@ -108,10 +108,10 @@ endmodule
// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
// Retrieval info: CONNECT: @datab 0 0 5 0 datab 0 0 5 0
// Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_hybr_ref_pre.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_hybr_ref_pre.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_hybr_ref_pre.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_hybr_ref_pre.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_hybr_ref_pre_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_hybr_ref_pre_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_8x5_9.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_8x5_9.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_8x5_9.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_8x5_9.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_8x5_9_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_8x5_9_bb.v FALSE
// Retrieval info: LIB_FILE: lpm

117
rtl/lpm_mult_hybr_ref.v
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@ -1,117 +0,0 @@
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: lpm_mult_hybr_ref.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
// ************************************************************
//Copyright (C) 2021 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module lpm_mult_hybr_ref (
clock,
dataa,
datab,
result);
input clock;
input [8:0] dataa;
input [7:0] datab;
output [8:0] result;
wire [8:0] sub_wire0;
wire [8:0] result = sub_wire0[8:0];
lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 9,
lpm_mult_component.lpm_widthb = 8,
lpm_mult_component.lpm_widthp = 9;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "0"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "9"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "9"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "9"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
// Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL "result[8..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
// Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_hybr_ref.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_hybr_ref.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_hybr_ref.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_hybr_ref.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_hybr_ref_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_hybr_ref_bb.v FALSE
// Retrieval info: LIB_FILE: lpm

4
rtl/lpm_mult_hybr_ref_pre.qip
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@ -1,4 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
set_global_assignment -name IP_TOOL_VERSION "21.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_hybr_ref_pre.v"]

4
rtl/lpm_mult_sl.v
View File

@ -61,7 +61,7 @@ module lpm_mult_sl (
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
@ -93,7 +93,7 @@ endmodule
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_HINT STRING "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"

120
rtl/scanconverter.v
View File

@ -92,6 +92,9 @@ localparam PP_LINEBUF_END = PP_LINEBUF_START + PP_LINEBUF_LENGTH;
localparam PP_SRCSEL_START = PP_LINEBUF_END;
localparam PP_SRCSEL_LENGTH = 1;
localparam PP_SRCSEL_END = PP_SRCSEL_START + PP_SRCSEL_LENGTH;
localparam PP_SHMASK_START = PP_SRCSEL_START;
localparam PP_SHMASK_LENGTH = 3;
localparam PP_SHMASK_END = PP_SHMASK_START + PP_SHMASK_LENGTH;
localparam PP_Y_CALC_START = PP_SRCSEL_END;
localparam PP_Y_CALC_LENGTH = 2;
localparam PP_Y_CALC_END = PP_Y_CALC_START + PP_Y_CALC_LENGTH;
@ -148,12 +151,21 @@ wire MISC_LM_DEINT_MODE = misc_config[12];
wire MISC_NIR_EVEN_OFFSET = misc_config[13];
wire [3:0] MISC_BFI_STR = misc_config[19:16];
wire MISC_BFI_ENABLE = misc_config[20];
wire MISC_SHMASK_ENABLE = (misc_config[22:21] != '0);
wire [1:0] MISC_SHMASK_ID = (misc_config[22:21] - 1'b1);
wire [7:0] MASK_R = MISC_MASK_COLOR[2] ? {2{MISC_MASK_BR}} : 8'h00;
wire [7:0] MASK_G = MISC_MASK_COLOR[1] ? {2{MISC_MASK_BR}} : 8'h00;
wire [7:0] MASK_B = MISC_MASK_COLOR[0] ? {2{MISC_MASK_BR}} : 8'h00;
/* RGB Shadow mask presets: A-Grille, TV, PVM. Data from ShadowMasks_MiSTer */
wire [1:0] shmask_iv_x[0:2] = '{2'h3, 2'h3, 2'h2};
wire [1:0] shmask_iv_y[0:2] = '{2'h0, 2'h1, 2'h3};
wire [10:0] shmask_data[0:2][0:3][0:3] = '{'{ '{11'h44c,11'h24c,11'h14c,11'h04c}, '{11'h0,11'h0,11'h0,11'h0}, '{11'h0,11'h0,11'h0,11'h0}, '{11'h0,11'h0,11'h0,11'h0}},
'{ '{11'h708,11'h44c,11'h24c,11'h14c}, '{11'h44c,11'h24c,11'h14c,11'h708}, '{11'h0,11'h0,11'h0,11'h0}, '{11'h0,11'h0,11'h0,11'h0}},
'{ '{11'h42a,11'h72a,11'h72a,11'h0}, '{11'h42a,11'h22a,11'h72a,11'h0}, '{11'h72a,11'h22a,11'h12a,11'h0}, '{11'h42a,11'h72a,11'h12a,11'h0}}};
reg frame_change_sync1_reg, frame_change_sync2_reg, frame_change_prev, frame_change_resync;
wire frame_change = frame_change_sync2_reg;
@ -171,7 +183,8 @@ reg line_id;
reg ypos_pp_init;
reg sl_method;
reg [7:0] Y_sl_str, R_sl_str, G_sl_str, B_sl_str;
reg [3:0] sl_str;
reg [7:0] sl_str_thold, Y_sl_str, R_sl_str, G_sl_str, B_sl_str;
wire [7:0] R_sl_mult, G_sl_mult, B_sl_mult;
wire bfi_frame;
@ -180,6 +193,9 @@ reg [9:0] Y;
wire [8:0] Y_sl_hybr_ref_pre, R_sl_hybr_ref_pre, G_sl_hybr_ref_pre, B_sl_hybr_ref_pre;
wire [8:0] Y_sl_hybr_ref, R_sl_hybr_ref, G_sl_hybr_ref, B_sl_hybr_ref;
reg [4:0] R_shmask_str, G_shmask_str, B_shmask_str;
wire [8:0] R_shmask_mult, G_shmask_mult, B_shmask_mult;
wire [7:0] R_linebuf, G_linebuf, B_linebuf;
// Pipeline registers
@ -193,35 +209,36 @@ reg [11:0] xpos_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
reg [10:0] ypos_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
reg mask_enable_pp[PP_MASK_END:PP_TP_START] /* synthesis ramstyle = "logic" */;
reg draw_sl_pp[(PP_SLGEN_START+1):(PP_SLGEN_END-1)] /* synthesis ramstyle = "logic" */;
reg [7:0] sl_str_pp[(PP_SLGEN_START+1):(PP_SLGEN_START+2)] /* synthesis ramstyle = "logic" */;
reg [3:0] x_ctr_sl_pp[PP_PL_START:PP_SLGEN_START] /* synthesis ramstyle = "logic" */;
reg [2:0] y_ctr_sl_pp[PP_PL_START:PP_SLGEN_START] /* synthesis ramstyle = "logic" */;
reg [1:0] x_ctr_shmask_pp[PP_PL_START:PP_SHMASK_START] /* synthesis ramstyle = "logic" */;
reg [1:0] y_ctr_shmask_pp[PP_PL_START:PP_SHMASK_START] /* synthesis ramstyle = "logic" */;
assign PCLK_o = PCLK_OUT_i;
lpm_mult_hybr_ref_pre Y_sl_hybr_ref_pre_u
lpm_mult_8x5_9 Y_sl_hybr_ref_pre_u
(
.clock(PCLK_OUT_i),
.dataa(Y[9:2]),
.datab(SL_HYBRSTR),
.result(Y_sl_hybr_ref_pre)
);
lpm_mult_hybr_ref_pre R_sl_hybr_ref_pre_u
lpm_mult_8x5_9 R_sl_hybr_ref_pre_u
(
.clock(PCLK_OUT_i),
.dataa(R_pp[PP_SLGEN_START]),
.datab(SL_HYBRSTR),
.result(R_sl_hybr_ref_pre)
);
lpm_mult_hybr_ref_pre G_sl_hybr_ref_pre_u
lpm_mult_8x5_9 G_sl_hybr_ref_pre_u
(
.clock(PCLK_OUT_i),
.dataa(G_pp[PP_SLGEN_START]),
.datab(SL_HYBRSTR),
.result(G_sl_hybr_ref_pre)
);
lpm_mult_hybr_ref_pre B_sl_hybr_ref_pre_u
lpm_mult_8x5_9 B_sl_hybr_ref_pre_u
(
.clock(PCLK_OUT_i),
.dataa(B_pp[PP_SLGEN_START]),
@ -229,32 +246,32 @@ lpm_mult_hybr_ref_pre B_sl_hybr_ref_pre_u
.result(B_sl_hybr_ref_pre)
);
lpm_mult_hybr_ref Y_sl_hybr_ref_u
lpm_mult_8x5_9 Y_sl_hybr_ref_u
(
.clock(PCLK_OUT_i),
.dataa(Y_sl_hybr_ref_pre),
.datab(sl_str_pp[PP_SLGEN_START+1]),
.dataa(Y_sl_hybr_ref_pre[8:1]),
.datab({sl_str, 1'b0}),
.result(Y_sl_hybr_ref)
);
lpm_mult_hybr_ref R_sl_hybr_ref_u
lpm_mult_8x5_9 R_sl_hybr_ref_u
(
.clock(PCLK_OUT_i),
.dataa(R_sl_hybr_ref_pre),
.datab(sl_str_pp[PP_SLGEN_START+1]),
.dataa(R_sl_hybr_ref_pre[8:1]),
.datab({sl_str, 1'b0}),
.result(R_sl_hybr_ref)
);
lpm_mult_hybr_ref G_sl_hybr_ref_u
lpm_mult_8x5_9 G_sl_hybr_ref_u
(
.clock(PCLK_OUT_i),
.dataa(G_sl_hybr_ref_pre),
.datab(sl_str_pp[PP_SLGEN_START+1]),
.dataa(G_sl_hybr_ref_pre[8:1]),
.datab({sl_str, 1'b0}),
.result(G_sl_hybr_ref)
);
lpm_mult_hybr_ref B_sl_hybr_ref_u
lpm_mult_8x5_9 B_sl_hybr_ref_u
(
.clock(PCLK_OUT_i),
.dataa(B_sl_hybr_ref_pre),
.datab(sl_str_pp[PP_SLGEN_START+1]),
.dataa(B_sl_hybr_ref_pre[8:1]),
.datab({sl_str, 1'b0}),
.result(B_sl_hybr_ref)
);
@ -280,6 +297,29 @@ lpm_mult_sl B_sl_mult_u
.result(B_sl_mult)
);
lpm_mult_8x5_9 R_shmask_mult_u
(
.clock(PCLK_OUT_i),
.dataa(R_pp[PP_SHMASK_START+1]),
.datab(R_shmask_str),
.result(R_shmask_mult)
);
lpm_mult_8x5_9 G_shmask_mult_u
(
.clock(PCLK_OUT_i),
.dataa(G_pp[PP_SHMASK_START+1]),
.datab(G_shmask_str),
.result(G_shmask_mult)
);
lpm_mult_8x5_9 B_shmask_mult_u
(
.clock(PCLK_OUT_i),
.dataa(B_pp[PP_SHMASK_START+1]),
.datab(B_shmask_str),
.result(B_shmask_mult)
);
linebuf_top #(
.EMIF_ENABLE(EMIF_ENABLE),
.NUM_LINE_BUFFERS(NUM_LINE_BUFFERS)
@ -372,6 +412,7 @@ end
// | | MASK | | | | | | | | | | |
// | | LB_SETUP | LINEBUF | | | | | | | | | |
// | | | | SRCSEL | | | | | | | | |
// | | | | SHMASK | SHMASK | SHMASK | | | | | | |
// | | | | | Y | Y | | | | | | |
// | | | | | | | SLGEN | SLGEN | SLGEN | SLGEN | SLGEN | |
// | | | | | | | | | | | | TP |
@ -412,6 +453,7 @@ always @(posedge PCLK_OUT_i) begin
y_ctr_sl_pp[1] <= 0;
end
line_id <= ~line_id;
y_ctr_shmask_pp[1] <= '0;
end else begin
if (ypos_pp[1] != V_ACTIVE) begin
ypos_pp[1] <= ypos_pp[1] + 1'b1;
@ -429,14 +471,17 @@ always @(posedge PCLK_OUT_i) begin
end else begin
y_ctr <= y_ctr + 1'b1;
end
if (!ypos_pp_init)
if (!ypos_pp_init) begin
y_ctr_sl_pp[1] <= (y_ctr_sl_pp[1] == SL_IV_Y) ? '0 : y_ctr_sl_pp[1] + 1'b1;
y_ctr_shmask_pp[1] <= (y_ctr_shmask_pp[1] == shmask_iv_y[MISC_SHMASK_ID]) ? '0 : y_ctr_shmask_pp[1] + 1'b1;
end
end
end
xpos_pp[1] <= 0;
xpos_lb <= X_START_LB;
x_ctr <= 0;
x_ctr_sl_pp[1] <= 0;
x_ctr_shmask_pp[1] <= 0;
end else begin
if (xpos_pp[1] != H_ACTIVE) begin
xpos_pp[1] <= xpos_pp[1] + 1'b1;
@ -450,6 +495,7 @@ always @(posedge PCLK_OUT_i) begin
x_ctr <= x_ctr + 1'b1;
end
x_ctr_sl_pp[1] <= (x_ctr_sl_pp[1] == SL_IV_X) ? '0 : x_ctr_sl_pp[1] + 1'b1;
x_ctr_shmask_pp[1] <= (x_ctr_shmask_pp[1] == shmask_iv_x[MISC_SHMASK_ID]) ? '0 : x_ctr_shmask_pp[1] + 1'b1;
end
end
end
@ -468,6 +514,10 @@ always @(posedge PCLK_OUT_i) begin
x_ctr_sl_pp[pp_idx] <= x_ctr_sl_pp[pp_idx-1];
y_ctr_sl_pp[pp_idx] <= y_ctr_sl_pp[pp_idx-1];
end
for(pp_idx = PP_PL_START+1; pp_idx <= PP_SHMASK_START; pp_idx = pp_idx+1) begin
x_ctr_shmask_pp[pp_idx] <= x_ctr_shmask_pp[pp_idx-1];
y_ctr_shmask_pp[pp_idx] <= y_ctr_shmask_pp[pp_idx-1];
end
// Overridden later where necessary
for (pp_idx = PP_SRCSEL_END+1; pp_idx <= PP_PL_END; pp_idx = pp_idx+1) begin
R_pp[pp_idx] <= R_pp[pp_idx-1];
@ -498,17 +548,33 @@ always @(posedge PCLK_OUT_i) begin
Y_rb_tmp <= {1'b0, R_pp[PP_Y_CALC_START]} + {1'b0, B_pp[PP_Y_CALC_START]};
Y <= {1'b0, Y_rb_tmp} + {1'b0, G_pp[PP_Y_CALC_START+1], 1'b0};
/* ---------- Shadow mask calculation (3 cycles) ---------- */
R_shmask_str <= shmask_data[MISC_SHMASK_ID][y_ctr_shmask_pp[PP_SHMASK_START]][x_ctr_shmask_pp[PP_SHMASK_START]][10] ?
5'h10 + shmask_data[MISC_SHMASK_ID][y_ctr_shmask_pp[PP_SHMASK_START]][x_ctr_shmask_pp[PP_SHMASK_START]][7:4] :
shmask_data[MISC_SHMASK_ID][y_ctr_shmask_pp[PP_SHMASK_START]][x_ctr_shmask_pp[PP_SHMASK_START]][3:0];
G_shmask_str <= shmask_data[MISC_SHMASK_ID][y_ctr_shmask_pp[PP_SHMASK_START]][x_ctr_shmask_pp[PP_SHMASK_START]][9] ?
5'h10 + shmask_data[MISC_SHMASK_ID][y_ctr_shmask_pp[PP_SHMASK_START]][x_ctr_shmask_pp[PP_SHMASK_START]][7:4] :
shmask_data[MISC_SHMASK_ID][y_ctr_shmask_pp[PP_SHMASK_START]][x_ctr_shmask_pp[PP_SHMASK_START]][3:0];
B_shmask_str <= shmask_data[MISC_SHMASK_ID][y_ctr_shmask_pp[PP_SHMASK_START]][x_ctr_shmask_pp[PP_SHMASK_START]][8] ?
5'h10 + shmask_data[MISC_SHMASK_ID][y_ctr_shmask_pp[PP_SHMASK_START]][x_ctr_shmask_pp[PP_SHMASK_START]][7:4] :
shmask_data[MISC_SHMASK_ID][y_ctr_shmask_pp[PP_SHMASK_START]][x_ctr_shmask_pp[PP_SHMASK_START]][3:0];
// Cycle 3
R_pp[PP_SHMASK_END] <= MISC_SHMASK_ENABLE ? (R_shmask_mult[8] ? 8'hff : R_shmask_mult[7:0]) : R_pp[PP_SHMASK_START+2];
G_pp[PP_SHMASK_END] <= MISC_SHMASK_ENABLE ? (G_shmask_mult[8] ? 8'hff : G_shmask_mult[7:0]) : G_pp[PP_SHMASK_START+2];
B_pp[PP_SHMASK_END] <= MISC_SHMASK_ENABLE ? (B_shmask_mult[8] ? 8'hff : B_shmask_mult[7:0]) : B_pp[PP_SHMASK_START+2];
/* ---------- Scanline generation (5 cycles) ---------- */
if (MISC_BFI_ENABLE & bfi_frame) begin
sl_str_pp[PP_SLGEN_START+1] <= ((MISC_BFI_STR+8'h01)<<4)-1'b1;
sl_str <= MISC_BFI_STR;
sl_method <= 1'b1;
draw_sl_pp[PP_SLGEN_START+1] <= 1'b1;
end else if (|(SL_L_OVERLAY & (6'h1<<y_ctr_sl_pp[PP_SLGEN_START]))) begin
sl_str_pp[PP_SLGEN_START+1] <= ((SL_L_STR[y_ctr_sl_pp[PP_SLGEN_START]]+8'h01)<<4)-1'b1;
sl_str <= SL_L_STR[y_ctr_sl_pp[PP_SLGEN_START]];
sl_method <= ~SL_METHOD_PRE;
draw_sl_pp[PP_SLGEN_START+1] <= 1'b1;
end else if (|(SL_C_OVERLAY & (10'h1<<x_ctr_sl_pp[PP_SLGEN_START]))) begin
sl_str_pp[PP_SLGEN_START+1] <= ((SL_C_STR[x_ctr_sl_pp[PP_SLGEN_START]]+8'h01)<<4)-1'b1;
sl_str <= SL_C_STR[x_ctr_sl_pp[PP_SLGEN_START]];
sl_method <= ~SL_METHOD_PRE;
draw_sl_pp[PP_SLGEN_START+1] <= 1'b1;
end else begin
@ -519,13 +585,13 @@ always @(posedge PCLK_OUT_i) begin
end
// Cycle 2
sl_str_pp[PP_SLGEN_START+2] <= sl_str_pp[PP_SLGEN_START+1];
sl_str_thold <= ((sl_str+8'h01)<<4)-1'b1;
// Cycle 3
Y_sl_str <= {1'b0, sl_str_pp[PP_SLGEN_START+2]} < Y_sl_hybr_ref ? 8'h0 : sl_str_pp[PP_SLGEN_START+2] - Y_sl_hybr_ref[7:0];
R_sl_str <= {1'b0, sl_str_pp[PP_SLGEN_START+2]} < R_sl_hybr_ref ? 8'h0 : sl_str_pp[PP_SLGEN_START+2] - R_sl_hybr_ref[7:0];
G_sl_str <= {1'b0, sl_str_pp[PP_SLGEN_START+2]} < G_sl_hybr_ref ? 8'h0 : sl_str_pp[PP_SLGEN_START+2] - G_sl_hybr_ref[7:0];
B_sl_str <= {1'b0, sl_str_pp[PP_SLGEN_START+2]} < B_sl_hybr_ref ? 8'h0 : sl_str_pp[PP_SLGEN_START+2] - B_sl_hybr_ref[7:0];
Y_sl_str <= ({1'b0, sl_str_thold} < Y_sl_hybr_ref) ? 8'h0 : sl_str_thold - Y_sl_hybr_ref[7:0];
R_sl_str <= ({1'b0, sl_str_thold} < R_sl_hybr_ref) ? 8'h0 : sl_str_thold - R_sl_hybr_ref[7:0];
G_sl_str <= ({1'b0, sl_str_thold} < G_sl_hybr_ref) ? 8'h0 : sl_str_thold - G_sl_hybr_ref[7:0];
B_sl_str <= ({1'b0, sl_str_thold} < B_sl_hybr_ref) ? 8'h0 : sl_str_thold - B_sl_hybr_ref[7:0];
// Cycle 4
// store subtraction based scanlined RGB into pipeline registers

17126
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
View File

File diff suppressed because it is too large Load Diff

7
software/sys_controller/ossc/av_controller.c
View File

@ -478,12 +478,13 @@ void update_sc_config(mode_data_t *vm_in, mode_data_t *vm_out, vm_proc_config_t
misc_config.mask_br = avconfig->mask_br;
misc_config.mask_color = avconfig->mask_color;
misc_config.reverse_lpf = avconfig->reverse_lpf;
misc_config.lm_deint_mode = 0;
misc_config.shmask_mode = avconfig->shmask_mode;
/*misc_config.lm_deint_mode = 0;
misc_config.nir_even_offset = 0;
misc_config.ypbpr_cs = (avconfig->ypbpr_cs == 0) ? ((vm_in->type & VIDEO_HDTV) ? 1 : 0) : avconfig->ypbpr_cs-1;
misc_config.vip_enable = 0;
misc_config.bfi_enable = 0;
misc_config.bfi_str = 0;
misc_config.bfi_str = 0;*/
// set default/custom scanline interval
sl_def_iv_y = (vm_conf->y_rpt > 0) ? vm_conf->y_rpt : 1;
@ -830,7 +831,7 @@ void print_vm_stats() {
sniprintf((char*)osd->osd_array.data[++row][0], OSD_CHAR_COLS, "Profile:");
sniprintf((char*)osd->osd_array.data[row][1], OSD_CHAR_COLS, "%u: %s", profile_sel, (target_profile_name[0] == 0) ? "<empty>" : target_profile_name);
sniprintf((char*)osd->osd_array.data[++row][0], OSD_CHAR_COLS, "Firmware:");
sniprintf((char*)osd->osd_array.data[++row][0], OSD_CHAR_COLS, "FW:");
sniprintf((char*)osd->osd_array.data[row][1], OSD_CHAR_COLS, "%u.%.2u" FW_SUFFIX1 FW_SUFFIX2 " @ " __DATE__, FW_VER_MAJOR, FW_VER_MINOR);
osd->osd_config.status_refresh = 1;

1
software/sys_controller/ossc/avconfig.h
View File

@ -117,6 +117,7 @@ typedef struct {
alt_u8 mask_br;
alt_u8 mask_color;
alt_u8 reverse_lpf;
alt_u8 shmask_mode;
/* AFE settings */
alt_u8 sync_vth;

2
software/sys_controller/ossc/firmware.h
View File

@ -27,7 +27,7 @@
#define FW_VER_MINOR 06
#define PROFILE_VER_MAJOR 1
#define PROFILE_VER_MINOR 05
#define PROFILE_VER_MINOR 06
#define INITCFG_VER_MAJOR 1
#define INITCFG_VER_MINOR 00

10
software/sys_controller/ossc/menu.c
View File

@ -78,6 +78,7 @@ static const char *rgsb_ypbpr_desc[] = { "RGsB", "YPbPr" };
static const char *auto_input_desc[] = { "Off", "Current input", "All inputs" };
static const char *mask_color_desc[] = { "Black", "Blue", "Green", "Cyan", "Red", "Magenta", "Yellow", "White" };
static const char *av3_alt_rgb_desc[] = { "Off", "AV1", "AV2" };
static const char *shmask_mode_desc[] = { "Off", "A-Grille", "TV", "PVM" };
static void sync_vth_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%d mV", (v*1127)/100); }
static void intclks_to_time_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u.%.2u us", (unsigned)(((1000000U*v)/(TVP_INTCLK_HZ/1000))/1000), (unsigned)((((1000000U*v)/(TVP_INTCLK_HZ/1000))%1000)/10)); }
@ -115,8 +116,8 @@ MENU(menu_advtiming, P99_PROTECT({ \
{ LNG("V. synclen","V. ﾄﾞｳｷﾅｶﾞｻ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_synclen, V_SYNCLEN_MIN, V_SYNCLEN_MAX, vm_tweak } } },
{ LNG("V. backporch","V. ﾊﾞｯｸﾎﾟｰﾁ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_bporch, V_BPORCH_MIN, V_BPORCH_MAX, vm_tweak } } },
{ LNG("V. active","V. ｱｸﾃｨﾌﾞ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_active, V_ACTIVE_MIN, V_ACTIVE_MAX, vm_tweak } } },
{ "H. mask", OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_mask, 0, H_MASK_MAX, vm_tweak } } },
{ "V. mask", OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_mask, 0, V_MASK_MAX, vm_tweak } } },
{ "H. border", OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_mask, 0, H_MASK_MAX, vm_tweak } } },
{ "V. border", OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_mask, 0, V_MASK_MAX, vm_tweak } } },
{ LNG("Sampling phase","ｻﾝﾌﾟﾘﾝｸﾞﾌｪｰｽﾞ"), OPT_AVCONFIG_NUMVAL_U16, { .num_u16 = { &tc_sampler_phase, 0, SAMPLER_PHASE_MAX, vm_tweak } } },
}))
@ -201,8 +202,9 @@ MENU(menu_scanlines, P99_PROTECT({ \
}))
MENU(menu_postproc, P99_PROTECT({ \
{ "Mask color", OPT_AVCONFIG_SELECTION, { .sel = { &tc.mask_color, OPT_NOWRAP, SETTING_ITEM(mask_color_desc) } } },
{ LNG("Mask brightness","ﾏｽｸｱｶﾙｻ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.mask_br, OPT_NOWRAP, 0, HV_MASK_MAX_BR, value_disp } } },
{ "Shadow mask", OPT_AVCONFIG_SELECTION, { .sel = { &tc.shmask_mode, OPT_WRAP, SETTING_ITEM(shmask_mode_desc) } } },
{ "Border color", OPT_AVCONFIG_SELECTION, { .sel = { &tc.mask_color, OPT_NOWRAP, SETTING_ITEM(mask_color_desc) } } },
{ LNG("Border brightn.","ﾏｽｸｱｶﾙｻ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.mask_br, OPT_NOWRAP, 0, HV_MASK_MAX_BR, value_disp } } },
//{ LNG("<DIY lat. test>","DIYﾁｴﾝﾃｽﾄ"), OPT_FUNC_CALL, { .fun = { latency_test, &lt_arg_info } } },
}))