RomanRom2/ossc
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Release 0.69

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* Improved remote control handling code
* Fixed occasional mode change loop when switching to a non-interlace mode utilizing odd-field sync signal
* Fixed randomly missing blue channel at power-on when using DVI output mode
* Added H-PLL coast options
* Finer tuning range for scanline strength and mask
This commit is contained in:
marqs committed 2016-04-15 22:05:53 +03:00
1 parent f502b2e46c
commit c83653c880
14 files changed
+1148 -1103
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software/sys_controller/tvp7002/tvp7002.c
+10 -9
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@@ -40,12 +40,6 @@ const ypbpr_to_rgb_csc_t csc_coeffs[] = {
extern mode_data_t video_modes[];
static inline void tvp_set_hpllcoast(alt_u8 pre, alt_u8 post)
{
tvp_writereg(TVP_HPLLPRECOAST, pre);
tvp_writereg(TVP_HPLLPOSTCOAST, post);
}
static inline void tvp_set_ssthold(alt_u8 vsdetect_thold)
{
tvp_writereg(TVP_SSTHOLD, vsdetect_thold);
@@ -167,6 +161,12 @@ inline void tvp_enable_output()
usleep(10000);
}
inline void tvp_set_hpllcoast(alt_u8 pre, alt_u8 post)
{
tvp_writereg(TVP_HPLLPRECOAST, pre);
tvp_writereg(TVP_HPLLPOSTCOAST, post);
}
void tvp_init()
{
// disable output
@@ -311,7 +311,7 @@ void tvp_set_sog_thold(alt_u8 val)
printf("SOG thold set to 0x%x\n", val);
}
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 refclk)
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 refclk, alt_u8 pre_coast, alt_u8 post_coast)
{
// Configure clock settings
tvp_sel_clk(refclk);
@@ -348,8 +348,9 @@ void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz,
//Long coast may lead to PLL frequency drift and sync loss (e.g. SNES)
/*if (video_modes[modeid].v_active < 720)
tvp_set_hpllcoast(3, 3);
else*/
tvp_set_hpllcoast(1, 0);
else
tvp_set_hpllcoast(1, 0);*/
tvp_set_hpllcoast(pre_coast, post_coast);
// Hsync output width
tvp_writereg(TVP_HSOUTWIDTH, video_modes[modeid].h_synclen);
software/sys_controller/tvp7002/tvp7002.h
+3 -1
View File
@@ -67,6 +67,8 @@ inline void tvp_disable_output();
inline void tvp_enable_output();
inline void tvp_set_hpllcoast(alt_u8 pre, alt_u8 post);
void tvp_init();
void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 v_lines, alt_u8 hz, alt_u8 plldivby2);
@@ -83,7 +85,7 @@ void tvp_set_hpll_phase(alt_u8 val);
void tvp_set_sog_thold(alt_u8 val);
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 refclk);
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 refclk, alt_u8 pre_coast, alt_u8 post_coast);
void tvp_source_sel(tvp_input_t input, video_format fmt, alt_u8 refclk);
software/sys_controller/tvp7002/video_modes.c
+1
View File
@@ -27,6 +27,7 @@
const mode_data_t video_modes[] = {
{ "240p_L3M0", 1280, 240, 6000, 1704, 262, 196, 16, 124, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L3_MODE0) },
{ "240p_L3M1", 960, 240, 6000, 1278, 262, 147, 16, 93, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L3_MODE1|MODE_PLLDIVBY2) },
//{ "240p_L3M2", 384, 240, 6000, 512, 262, 66, 16, 31, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE2|MODE_PLLDIVBY2) }, //CPS2
{ "240p_L3M2", 320, 240, 6000, 426, 262, 49, 16, 31, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE2|MODE_PLLDIVBY2) },
{ "240p_L3M3", 256, 240, 6000, 341, 262, 39, 16, 25, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE3|MODE_PLLDIVBY2) },
{ "240p", 720, 240, 6000, 858, 262, 65, 16, 60, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L2ENABLE|MODE_PLLDIVBY2) },