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Merge branch 'gbi' of git://github.com/paulb-nl/ossc into paulb-nl-gbi

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marqs committed 2018-10-24 21:39:28 +03:00
2 parents c250042cdb f7075a0846
commit d03e0658a0
7 files changed
+99 -41
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software/sys_controller/tvp7002/video_modes.c
+39 -3
View File
@@ -49,7 +49,11 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
switch (video_modes[i].group) {
case GROUP_NONE:
case GROUP_240P:
break;
case GROUP_384P:
//fixed Line2x/3x mode for 240x360p
valid_lm[2] = MODE_L2_240x360;
valid_lm[3] = MODE_L3_240x360;
break;
case GROUP_480I:
//fixed Line3x/4x mode for 480i
@@ -107,7 +111,7 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
// Use native 2x sampling with low-res modes when possible to minimize jitter and generate min. 25MHz input pclk for FPGA PLL
if ((!cm.cc.vga_ilace_fix) && (video_modes[i].h_total < 1400) && ((video_modes[i].group == GROUP_240P) || (video_modes[i].group == GROUP_384P) || (video_modes[i].group == GROUP_480I))) {
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED_1X;
cm.sample_mult = 2;
} else {
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
@@ -122,16 +126,26 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
}
}
break;
case MODE_L2_256_COL:
case MODE_L2_512_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 2;
break;
case MODE_L2_256_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED_1X;
cm.sample_mult = 6;
break;
case MODE_L2_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED_1X;
cm.sample_mult = 4;
break;
case MODE_L2_240x360:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 5;
break;
case MODE_L3_GEN_16_9:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
@@ -147,6 +161,11 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_ASPECTFIX;
break;
case MODE_L3_512_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 2;
break;
case MODE_L3_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
@@ -157,6 +176,12 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 5;
break;
case MODE_L3_240x360:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 7;
cm.hsync_cut = 13;
break;
case MODE_L4_GEN_4_3:
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
@@ -168,6 +193,11 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.tx_pixelrep = TX_PIXELREP_2X;
}
break;
case MODE_L4_512_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 2;
break;
case MODE_L4_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
@@ -183,6 +213,12 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
cm.hsync_cut = 120;
break;
case MODE_L5_512_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 3;
cm.hsync_cut = 40;
break;
case MODE_L5_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
software/sys_controller/tvp7002/video_modes.h
+23 -12
View File
@@ -68,18 +68,24 @@ typedef enum {
//at least one of the flags below must be set for each mode
MODE_PT = (1<<2),
MODE_L2 = (1<<3),
MODE_L2_320_COL = (1<<4),
MODE_L2_256_COL = (1<<5),
MODE_L3_GEN_16_9 = (1<<6),
MODE_L3_GEN_4_3 = (1<<7),
MODE_L3_320_COL = (1<<8),
MODE_L3_256_COL = (1<<9),
MODE_L4_GEN_4_3 = (1<<10),
MODE_L4_320_COL = (1<<11),
MODE_L4_256_COL = (1<<12),
MODE_L5_GEN_4_3 = (1<<13),
MODE_L5_320_COL = (1<<14),
MODE_L5_256_COL = (1<<15),
MODE_L2_512_COL = (1<<4),
MODE_L2_320_COL = (1<<5),
MODE_L2_256_COL = (1<<6),
MODE_L2_240x360 = (1<<7),
MODE_L3_GEN_16_9 = (1<<8),
MODE_L3_GEN_4_3 = (1<<9),
MODE_L3_512_COL = (1<<10),
MODE_L3_320_COL = (1<<11),
MODE_L3_256_COL = (1<<12),
MODE_L3_240x360 = (1<<13),
MODE_L4_GEN_4_3 = (1<<14),
MODE_L4_512_COL = (1<<15),
MODE_L4_320_COL = (1<<16),
MODE_L4_256_COL = (1<<17),
MODE_L5_GEN_4_3 = (1<<18),
MODE_L5_512_COL = (1<<19),
MODE_L5_320_COL = (1<<20),
MODE_L5_256_COL = (1<<21),
} mode_flags;
typedef struct {
@@ -103,6 +109,7 @@ typedef struct {
{ "1600x240", 1600, 240, 2046, 262, 202, 15, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "1280x240", 1280, 240, 1560, 262, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "960x240", 960, 240, 1170, 262, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "512x240", 512, 240, 682, 262, 77, 14, 50, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL) }, \
{ "320x240", 320, 240, 426, 262, 49, 14, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
{ "256x240", 256, 240, 341, 262, 39, 14, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
{ "240p", 720, 240, 858, 262, 57, 15, 62, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
@@ -110,9 +117,13 @@ typedef struct {
{ "1600x240L", 1600, 240, 2046, 312, 202, 41, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "1280x288", 1280, 288, 1560, 312, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "960x288", 960, 288, 1170, 312, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "512x240LB", 512, 240, 682, 312, 77, 41, 50, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL) }, \
{ "320x240LB", 320, 240, 426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
{ "256x240LB", 256, 240, 341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
{ "288p", 720, 288, 864, 312, 69, 19, 63, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
/* 360p: GBI */ \
{ "480x360", 480, 360, 600, 375, 63, 10, 38, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
{ "240x360", 256, 360, 300, 375, 24, 10, 18, 3, (VIDEO_EDTV), GROUP_384P, (MODE_L2_240x360 | MODE_L3_240x360) }, \
/* 384p: Sega Model 2 */ \
{ "384p", 496, 384, 640, 423, 50, 29, 62, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
/* 640x400, VGA Mode 13h */ \