From d1fd30019f315086ed682b4d38bdc0f520b1fa59 Mon Sep 17 00:00:00 2001 From: marqs Date: Sat, 5 Oct 2019 11:33:59 +0300 Subject: [PATCH] osd_generator: add M9K support to allow larger character array --- ip/osd_generator/osd_generator_hw.tcl | 9 ++ ip/osd_generator/osd_generator_top.sv | 97 +++++++---- ossc.qsf | 3 +- rtl/char_array.qip | 6 + rtl/char_array.v | 222 ++++++++++++++++++++++++++ sys.sopcinfo | 12 +- 6 files changed, 311 insertions(+), 38 deletions(-) create mode 100644 rtl/char_array.qip create mode 100644 rtl/char_array.v diff --git a/ip/osd_generator/osd_generator_hw.tcl b/ip/osd_generator/osd_generator_hw.tcl index 54b4ab9..7ec49f3 100644 --- a/ip/osd_generator/osd_generator_hw.tcl +++ b/ip/osd_generator/osd_generator_hw.tcl @@ -20,6 +20,15 @@ set_module_property REPORT_TO_TALKBACK false set_module_property ALLOW_GREYBOX_GENERATION false set_module_property REPORT_HIERARCHY false +# +# parameters +# +add_parameter USE_MEMORY_BLOCKS INTEGER 1 +set_parameter_property USE_MEMORY_BLOCKS DISPLAY_NAME "Use memory blocks for character array" +set_parameter_property USE_MEMORY_BLOCKS DISPLAY_HINT boolean +set_parameter_property USE_MEMORY_BLOCKS UNITS None +set_parameter_property USE_MEMORY_BLOCKS HDL_PARAMETER true + # # file sets # diff --git a/ip/osd_generator/osd_generator_top.sv b/ip/osd_generator/osd_generator_top.sv index 59a5bb3..2bcd474 100644 --- a/ip/osd_generator/osd_generator_top.sv +++ b/ip/osd_generator/osd_generator_top.sv @@ -17,7 +17,9 @@ // along with this program. If not, see . // -module osd_generator_top( +module osd_generator_top #( + parameter USE_MEMORY_BLOCKS = 0 +) ( // common input clk_i, input rst_i, @@ -45,13 +47,10 @@ localparam OSD_CONFIG_REGNUM = 4'h0; reg [31:0] osd_config; -reg [7:0] char_ptr[CHAR_ROWS*CHAR_COLS-1:0], char_ptr_pp3[7:0] /* synthesis ramstyle = "logic" */; reg [10:0] xpos_scaled; reg [10:0] ypos_scaled; reg [7:0] x_ptr[2:5], y_ptr[2:5] /* synthesis ramstyle = "logic" */; reg osd_act_pp[2:5]; -reg [4:0] char_idx; -reg [2:0] char_idx_lo; reg [14:0] to_ctr, to_ctr_ms; wire render_enable = osd_config[0]; @@ -63,11 +62,31 @@ wire [2:0] y_offset = osd_config[10:8]; wire [1:0] x_size = osd_config[12:11]; wire [1:0] y_size = osd_config[14:13]; -wire [7:0] rom_rdaddr = char_ptr_pp3[char_idx_lo]; +wire [7:0] rom_rdaddr; wire [0:7] char_data[7:0]; +wire [4:0] char_idx = CHAR_COLS*(ypos_scaled >> 3) + (xpos_scaled >> 3); assign avalon_s_waitrequest_n = 1'b1; +generate + if (USE_MEMORY_BLOCKS == 1) begin + char_array char_array_inst ( + .byteena_a(avalon_s_byteenable), + .data(avalon_s_writedata), + .rdaddress(char_idx), + .rdclock(vclk), + .wraddress(avalon_s_address-1'b1), + .wrclock(clk_i), + .wren(avalon_s_chipselect && avalon_s_write && (avalon_s_address > 4'h0)), + .q(rom_rdaddr) + ); + end else begin + reg [7:0] char_ptr[CHAR_ROWS*CHAR_COLS-1:0], char_ptr_pp3[7:0] /* synthesis ramstyle = "logic" */; + reg [4:0] char_idx_pp[2:3]; + + assign rom_rdaddr = char_ptr_pp3[char_idx_pp[3][2:0]]; + end +endgenerate char_rom char_rom_inst ( .clock(vclk), @@ -76,12 +95,12 @@ char_rom char_rom_inst ( ); // Pipeline structure -// | 1 | 2 | 3 | 4 | 5 | 6 | -// |-------------|------------|-------------|---------|---------|------------| -// | xpos_scaled | x_ptr | x_ptr | x_ptr | x_ptr | | -// | ypos_scaled | y_ptr | y_ptr | y_ptr | y_ptr | | -// | | osd_act | osd_act | osd_act | osd_act | osd_enable | -// | | char_idx | char_idx_lo | CBUF | CBUF | osd_color | +// | 1 | 2 | 3 | 4 | 5 | 6 | +// |-------------|------------|----------|---------|---------|------------| +// | xpos_scaled | x_ptr | x_ptr | x_ptr | x_ptr | | +// | ypos_scaled | y_ptr | y_ptr | y_ptr | y_ptr | | +// | | osd_act | osd_act | osd_act | osd_act | osd_enable | +// | | char_idx | char_idx | CBUF | CBUF | osd_color | integer idx, pp_idx; always @(posedge vclk) begin xpos_scaled <= (xpos >> x_size)-({3'h0, x_offset} << 3); @@ -94,13 +113,6 @@ always @(posedge vclk) begin y_ptr[pp_idx] <= y_ptr[pp_idx-1]; end - char_idx <= CHAR_COLS*(ypos_scaled >> 3) + (xpos_scaled >> 3); - char_idx_lo <= char_idx[2:0]; - - for(idx = 0; idx <= 7; idx = idx+1) begin - char_ptr_pp3[idx] <= char_ptr[{char_idx[4:3], 3'(idx)}]; - end - osd_act_pp[2] <= render_enable & (menu_active || (to_ctr_ms > 0)) & ((xpos_scaled < 8*CHAR_COLS) && (ypos_scaled < 8*CHAR_ROWS)); for(pp_idx = 3; pp_idx <= 5; pp_idx = pp_idx+1) begin osd_act_pp[pp_idx] <= osd_act_pp[pp_idx-1]; @@ -110,6 +122,19 @@ always @(posedge vclk) begin osd_color = char_data[y_ptr[5]][x_ptr[5]]; end +generate + if (USE_MEMORY_BLOCKS == 0) begin + always @(posedge vclk) begin + char_idx_pp[2] <= char_idx; + char_idx_pp[3] <= char_idx_pp[2]; + + for(idx = 0; idx <= 7; idx = idx+1) begin + char_ptr_pp3[idx] <= char_ptr[{char_idx_pp[2][4:3], 3'(idx)}]; + end + end + end +endgenerate + // OSD status timeout counters always @(posedge clk_i) begin @@ -155,23 +180,25 @@ end genvar i; generate - for (i = 0; i < (CHAR_ROWS*CHAR_COLS); i = i + 4) begin : genreg - always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - char_ptr[i] <= 0; - char_ptr[i+1] <= 0; - char_ptr[i+2] <= 0; - char_ptr[i+3] <= 0; - end else begin - if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==1+(i/4))) begin - if (avalon_s_byteenable[3]) - char_ptr[i+3] <= avalon_s_writedata[31:24]; - if (avalon_s_byteenable[2]) - char_ptr[i+2] <= avalon_s_writedata[23:16]; - if (avalon_s_byteenable[1]) - char_ptr[i+1] <= avalon_s_writedata[15:8]; - if (avalon_s_byteenable[0]) - char_ptr[i] <= avalon_s_writedata[7:0]; + if (USE_MEMORY_BLOCKS == 0) begin + for (i = 0; i < (CHAR_ROWS*CHAR_COLS); i = i + 4) begin : genreg + always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + char_ptr[i] <= 0; + char_ptr[i+1] <= 0; + char_ptr[i+2] <= 0; + char_ptr[i+3] <= 0; + end else begin + if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==1+(i/4))) begin + if (avalon_s_byteenable[3]) + char_ptr[i+3] <= avalon_s_writedata[31:24]; + if (avalon_s_byteenable[2]) + char_ptr[i+2] <= avalon_s_writedata[23:16]; + if (avalon_s_byteenable[1]) + char_ptr[i+1] <= avalon_s_writedata[15:8]; + if (avalon_s_byteenable[0]) + char_ptr[i] <= avalon_s_writedata[7:0]; + end end end end diff --git a/ossc.qsf b/ossc.qsf index 1340465..13a319c 100644 --- a/ossc.qsf +++ b/ossc.qsf @@ -224,7 +224,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp set_global_assignment -name FITTER_EFFORT "AUTO FIT" -set_global_assignment -name SEED 1 +set_global_assignment -name SEED 2 @@ -247,4 +247,5 @@ set_global_assignment -name QIP_FILE rtl/mux5.qip set_global_assignment -name SDC_FILE ossc.sdc set_global_assignment -name CDF_FILE output_files/Chain1.cdf set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp +set_global_assignment -name QIP_FILE rtl/char_array.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/rtl/char_array.qip b/rtl/char_array.qip new file mode 100644 index 0000000..46ce66f --- /dev/null +++ b/rtl/char_array.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" +set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_array.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_bb.v"] diff --git a/rtl/char_array.v b/rtl/char_array.v new file mode 100644 index 0000000..ddb6284 --- /dev/null +++ b/rtl/char_array.v @@ -0,0 +1,222 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: char_array.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 17.1.0 Build 590 10/25/2017 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module char_array ( + byteena_a, + data, + rdaddress, + rdclock, + wraddress, + wrclock, + wren, + q); + + input [3:0] byteena_a; + input [31:0] data; + input [9:0] rdaddress; + input rdclock; + input [7:0] wraddress; + input wrclock; + input wren; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [3:0] byteena_a; + tri1 wrclock; + tri0 wren; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] q = sub_wire0[7:0]; + + altsyncram altsyncram_component ( + .address_a (wraddress), + .address_b (rdaddress), + .byteena_a (byteena_a), + .clock0 (wrclock), + .clock1 (rdclock), + .data_a (data), + .wren_a (wren), + .q_b (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({8{1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK1", + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone IV E", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 256, + altsyncram_component.numwords_b = 1024, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "CLOCK1", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.widthad_a = 8, + altsyncram_component.widthad_b = 10, + altsyncram_component.width_a = 32, + altsyncram_component.width_b = 8, + altsyncram_component.width_byteena_a = 4; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "1" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +// Retrieval info: PRIVATE: REGrren NUMERIC "1" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "1" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4" +// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC "byteena_a[3..0]" +// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]" +// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock" +// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]" +// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0 +// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0 +// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0 +// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/sys.sopcinfo b/sys.sopcinfo index 47a5a96..fb636c3 100644 --- a/sys.sopcinfo +++ b/sys.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1570135029 + 1570236075 false true false @@ -5944,6 +5944,14 @@ parameters are a RESULT of the module parameters. --> path="osd_generator_0"> + + int + 1 + false + true + true + true + java.lang.String UNKNOWN