mirror of
https://github.com/marqs85/ossc
synced 2026-07-17 09:26:58 +03:00
add compatibility option for disabling HDMI PR2x
This commit is contained in:
marqs
parent
35f8595a05
commit
d653b67ffc
31
ossc.qsf
31
ossc.qsf
@ -163,8 +163,6 @@ set_location_assignment PIN_129 -to btn[1]
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set_location_assignment PIN_128 -to btn[0]
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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@ -220,20 +218,33 @@ set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_new.stp
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set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name SEED 1
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[0]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[1]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[2]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[3]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[4]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[5]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[6]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[7]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[0]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[1]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[2]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[3]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[4]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[5]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[6]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[7]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[0]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[1]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[2]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[3]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[4]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[5]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[6]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[7]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_HS
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_VS
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_DE
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set_global_assignment -name VERILOG_FILE rtl/videogen.v
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@ -259,4 +270,6 @@ set_global_assignment -name SEARCH_PATH software/sys_controller/mem_init/
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set_global_assignment -name SEARCH_PATH ip/ibex_qsys/rtl_extra
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set_global_assignment -name VERILOG_MACRO "SYNTHESIS=<None>"
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set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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8
ossc.sdc
8
ossc.sdc
@ -43,10 +43,10 @@ foreach_in_collection c [get_clocks "pclk_tvp*"] {
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set_input_delay -clock $c -max $TVP_dmax $critinputs -add_delay
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}
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# output delay constraints as documented in the IT6613 datasheet
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# -- increased IT_Tsu from 1.0 to 1.5 due to #52
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set IT_Tsu 1.5
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set IT_Th -0.5
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# output delay constraints based on params from IT6613 datasheet (S=1ns, H=0.5ns)
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# shifted aperture window due to issues #52 and #56
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set IT_Tsu 2.0
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set IT_Th -0.2
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set critoutputs_hdmi [get_ports {HDMI_TX_RD* HDMI_TX_GD* HDMI_TX_BD* HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
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foreach_in_collection c [get_clocks pclk_*_out] {
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set_output_delay -clock $c -min $IT_Th $critoutputs_hdmi -add
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@ -107,6 +107,7 @@ typedef struct {
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alt_u8 fpga_pll_bw;
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alt_u8 panasonic_hack;
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alt_u8 o480p_pbox;
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alt_u8 hdmi_pr2x_disable;
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/* Postprocessing settings */
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alt_u8 sl_mode;
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@ -247,6 +247,7 @@ MENU(menu_compatibility, P99_PROTECT({ \
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{ "Full VSYNC bypas", OPT_AVCONFIG_SELECTION, { .sel = { &tc.full_vs_bypass, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
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{ "Default HDMI VIC", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.default_vic, OPT_NOWRAP, 0, HDMI_1080p50, value_disp } } },
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{ "Panasonic hack", OPT_AVCONFIG_SELECTION, { .sel = { &tc.panasonic_hack, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
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{ "Disable PR2x", OPT_AVCONFIG_SELECTION, { .sel = { &tc.hdmi_pr2x_disable, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
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}))
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MENU(menu_audio, P99_PROTECT({ \
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@ -143,6 +143,7 @@ const ude_item_map ude_profile_items[] = {
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UDE_ITEM(66, 120, tc.panasonic_hack),
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UDE_ITEM(67, 120, tc.o480p_pbox),
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UDE_ITEM(61, 122, tc.hdmi_ar),
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UDE_ITEM(61, 122, tc.hdmi_pr2x_disable),
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};
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int write_userdata(uint8_t entry) {
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@ -133,7 +133,7 @@ uint32_t calculate_pclk(uint32_t src_clk_hz, mode_data_t *vm_out, vm_proc_config
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int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm_proc_config_t *vm_conf)
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{
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int i, diff_lines, diff_v_hz_x100, mindiff_id=0, mindiff_lines=1000, mindiff_v_hz_x100=10000, x_rpt_decr=0;
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int i, diff_lines, diff_v_hz_x100, mindiff_id=0, mindiff_lines=1000, mindiff_v_hz_x100=10000, x_rpt_decr=0, skip_hv_mult=0;
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mode_data_t *mode_preset;
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mode_flags valid_lm[] = { (MODE_PT | (cc->pt_mode ? (MODE_L5_GEN_4_3<<(cc->pt_mode-1)) : 0)),
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(MODE_L2 | (MODE_L2<<cc->l2_mode)),
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@ -281,7 +281,6 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
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while ((((vm_out->timings.v_hz_x100*vm_out->timings.v_total)/100)*vm_out->timings.h_total*(vm_conf->h_skip+1))>>vm_out->timings.interlaced < 25000000UL) {
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vm_conf->x_rpt = vm_conf->h_skip = 2*(vm_conf->h_skip+1)-1;
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}
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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break;
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case MODE_L2:
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// Upsample / pixel-repeat horizontal resolution of 384p/480p/960i modes
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@ -289,16 +288,15 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
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if (upsample2x) {
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vmode_hv_mult(vm_in, 2, 1);
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vmode_hv_mult(vm_out, 2, VM_OUT_YMULT);
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skip_hv_mult = 1;
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} else {
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vm_conf->x_rpt = 1;
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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}
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} else {
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if (cc->o480p_pbox) {
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vm_conf->x_rpt = vm_conf->h_skip = 3;
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x_rpt_decr += 1;
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}
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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}
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break;
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case MODE_L3_GEN_16_9:
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@ -307,12 +305,14 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
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if (upsample2x) {
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vmode_hv_mult(vm_in, 2, 1);
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vmode_hv_mult(vm_out, 2, VM_OUT_YMULT);
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skip_hv_mult = 1;
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} else {
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vm_conf->x_rpt = 1;
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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}
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} else {
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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} else if (cc->hdmi_pr2x_disable && ((mode_preset->group == GROUP_480P) || (mode_preset->group == GROUP_576P))) {
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vmode_hv_mult(vm_in, 2, 1);
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vmode_hv_mult(vm_out, 2, VM_OUT_YMULT);
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skip_hv_mult = 1;
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}
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break;
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case MODE_L3_GEN_4_3:
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@ -328,6 +328,7 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
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vm_out->timings.h_total /= 3;
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vm_out->timings.h_total_adj = 0;
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vmode_hv_mult(vm_out, 4, VM_OUT_YMULT);
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skip_hv_mult = 1;
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break;
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case MODE_L4_GEN_4_3:
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// Upsample / pixel-repeat horizontal resolution of 480i mode
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@ -335,17 +336,30 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
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if (upsample2x) {
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vmode_hv_mult(vm_in, 2, 1);
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vmode_hv_mult(vm_out, 2, VM_OUT_YMULT);
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skip_hv_mult = 1;
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} else {
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vm_conf->x_rpt = 1;
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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}
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} else {
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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}
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break;
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case MODE_L5_GEN_4_3:
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if (cc->hdmi_pr2x_disable && mode_preset->group == GROUP_288P) {
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vmode_hv_mult(vm_in, 2, 1);
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vmode_hv_mult(vm_out, 2, VM_OUT_YMULT);
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skip_hv_mult = 1;
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}
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break;
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case MODE_L6_GEN_4_3:
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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if (cc->hdmi_pr2x_disable) {
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if (mode_preset->group == GROUP_288P) {
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// upsampled active would exceed 2048, must pixel-repeat
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vm_conf->x_rpt = 1;
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} else {
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vmode_hv_mult(vm_in, 2, 1);
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vmode_hv_mult(vm_out, 2, VM_OUT_YMULT);
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skip_hv_mult = 1;
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}
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}
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break;
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case MODE_L2_512_COL:
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case MODE_L2_384_COL:
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@ -356,13 +370,13 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
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} else {
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vm_conf->x_rpt = vm_conf->h_skip = 1;
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}
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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break;
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case MODE_L3_512_COL:
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case MODE_L4_512_COL:
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case MODE_L6_512_COL:
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vm_conf->x_rpt = vm_conf->h_skip = 1;
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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break;
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case MODE_L6_512_COL:
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vm_conf->x_rpt = vm_conf->h_skip = cc->hdmi_pr2x_disable ? 3 : 1;
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break;
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case MODE_L2_256_COL:
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if (cc->o480p_pbox) {
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@ -371,34 +385,35 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
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} else {
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vm_conf->x_rpt = vm_conf->h_skip = 2;
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}
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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break;
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case MODE_L3_384_COL:
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case MODE_L4_384_COL:
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case MODE_L5_512_COL:
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vm_conf->x_rpt = vm_conf->h_skip = 2;
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break;
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case MODE_L6_384_COL:
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case MODE_L6_320_COL:
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vm_conf->x_rpt = vm_conf->h_skip = 2;
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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vm_conf->x_rpt = vm_conf->h_skip = cc->hdmi_pr2x_disable ? 5 : 2;
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break;
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case MODE_L3_240x360:
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vm_conf->x_rpt = vm_conf->h_skip = 7;
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break;
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case MODE_L3_320_COL:
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case MODE_L4_320_COL:
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case MODE_L5_384_COL:
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case MODE_L6_256_COL:
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vm_conf->x_rpt = vm_conf->h_skip = 3;
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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break;
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case MODE_L6_256_COL:
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vm_conf->x_rpt = vm_conf->h_skip = cc->hdmi_pr2x_disable ? 7 : 3;
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break;
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case MODE_L2_240x360:
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case MODE_L3_256_COL:
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case MODE_L4_256_COL:
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case MODE_L5_320_COL:
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vm_conf->x_rpt = vm_conf->h_skip = 4;
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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break;
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case MODE_L5_256_COL:
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vm_conf->x_rpt = vm_conf->h_skip = 5;
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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break;
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default:
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printf("WARNING: invalid mindiff_lm\n");
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@ -406,6 +421,9 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
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break;
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}
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if (!skip_hv_mult)
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vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
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// Set clock multiplication factor
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if (mindiff_lm == MODE_L3_GEN_4_3)
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vm_conf->si_pclk_mult = 4;
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@ -415,11 +433,15 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
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// Reduce x_rpt for 1:1 PAR 256col mode
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if (mindiff_lm & (MODE_L2_256_COL|MODE_L4_256_COL|MODE_L5_256_COL))
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vm_conf->x_rpt -= cc->ar_256col;
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else if (mindiff_lm & (MODE_L3_256_COL|MODE_L6_256_COL))
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else if (mindiff_lm & MODE_L3_256_COL)
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vm_conf->x_rpt = cc->ar_256col ? 2 : 3;
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else if (mindiff_lm & MODE_L6_256_COL)
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vm_conf->x_rpt = cc->ar_256col ? (cc->hdmi_pr2x_disable+1)*3-1 : (cc->hdmi_pr2x_disable+1)*4-1;
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if (mindiff_lm & (MODE_L3_320_COL|MODE_L2_240x360|MODE_L3_240x360))
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if (mindiff_lm & (MODE_L3_320_COL|MODE_L2_240x360))
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x_rpt_decr += 1;
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else if (mindiff_lm & (MODE_L3_240x360))
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x_rpt_decr += 2;
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vm_conf->x_rpt -= x_rpt_decr;
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@ -429,9 +451,9 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
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}
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// Force TX pixel-repeat for high bandwidth modes
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if (((mindiff_lm == MODE_L5_GEN_4_3) && (mode_preset->group == GROUP_288P)) ||
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if (!cc->hdmi_pr2x_disable && (((mindiff_lm == MODE_L5_GEN_4_3) && (mode_preset->group == GROUP_288P)) ||
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((mindiff_lm == MODE_L3_GEN_16_9) && ((mode_preset->group == GROUP_480P) || (mode_preset->group == GROUP_576P))) ||
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(mindiff_lm == MODE_L3_240x360) || (mindiff_lm >= MODE_L6_GEN_4_3))
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(mindiff_lm >= MODE_L6_GEN_4_3)))
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vm_conf->tx_pixelrep = 1;
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sniprintf(vm_out->name, 11, "%s x%u", vm_in->name, vm_conf->y_rpt+1);
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