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make Lumacode palettes CPU controlled

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marqs committed 2025-06-16 22:53:34 +03:00
1 parent 6198ce7d9e
commit d6dba1618b
15 files changed
+695 -194
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ip/ibex_qsys
+1 -1
Submodule ip/ibex_qsys updated: 8056961584...79c0da7011.
ip/sc_config/inc/sc_config_regs.h
+2
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@@ -165,6 +165,8 @@ typedef struct {
sl_config_reg sl_config;
sl_config2_reg sl_config2;
sl_config3_reg sl_config3;
uint32_t padding[1];
uint32_t lumacode_pal_ram[496];
} sc_regs;
#endif //SC_CONFIG_REGS_H_
ip/sc_config/sc_config_hw.tcl
+19 -1
View File
@@ -100,7 +100,7 @@ set_interface_property avalon_s PORT_NAME_MAP ""
set_interface_property avalon_s CMSIS_SVD_VARIABLES ""
set_interface_property avalon_s SVD_ADDRESS_GROUP ""
add_interface_port avalon_s avalon_s_address address Input 4
add_interface_port avalon_s avalon_s_address address Input 9
add_interface_port avalon_s avalon_s_writedata writedata Input 32
add_interface_port avalon_s avalon_s_readdata readdata Output 32
add_interface_port avalon_s avalon_s_byteenable byteenable Input 4
@@ -158,3 +158,21 @@ add_interface_port sc_if misc_config_o misc_config_o Output 32
add_interface_port sc_if sl_config_o sl_config_o Output 32
add_interface_port sc_if sl_config2_o sl_config2_o Output 32
add_interface_port sc_if sl_config3_o sl_config3_o Output 32
#
# connection point lumacode_ram_if
#
add_interface lc_ram_if conduit end
set_interface_property lc_ram_if associatedClock ""
set_interface_property lc_ram_if associatedReset ""
set_interface_property lc_ram_if ENABLED true
set_interface_property lc_ram_if EXPORT_OF ""
set_interface_property lc_ram_if PORT_NAME_MAP ""
set_interface_property lc_ram_if CMSIS_SVD_VARIABLES ""
set_interface_property lc_ram_if SVD_ADDRESS_GROUP ""
add_interface_port lc_ram_if lumacode_clk_i lumacode_clk_i Input 1
add_interface_port lc_ram_if lumacode_addr_i lumacode_addr_i Input 9
add_interface_port lc_ram_if lumacode_rden_i lumacode_rden_i Input 1
add_interface_port lc_ram_if lumacode_data_o lumacode_data_o Output 32
ip/sc_config/sc_config_top.sv
+71 -17
View File
@@ -24,7 +24,7 @@ module sc_config_top(
// avalon slave
input [31:0] avalon_s_writedata,
output reg [31:0] avalon_s_readdata,
input [3:0] avalon_s_address,
input [8:0] avalon_s_address,
input [3:0] avalon_s_byteenable,
input avalon_s_write,
input avalon_s_read,
@@ -45,24 +45,31 @@ module sc_config_top(
output [31:0] misc_config_o,
output [31:0] sl_config_o,
output [31:0] sl_config2_o,
output [31:0] sl_config3_o
output [31:0] sl_config3_o,
// Lumacode interface
input lumacode_clk_i,
input [8:0] lumacode_addr_i,
input lumacode_rden_i,
output [31:0] lumacode_data_o
);
localparam FE_STATUS_REGNUM = 4'h0;
localparam FE_STATUS2_REGNUM = 4'h1;
localparam LT_STATUS_REGNUM = 4'h2;
localparam HV_IN_CONFIG_REGNUM = 4'h3;
localparam HV_IN_CONFIG2_REGNUM = 4'h4;
localparam HV_IN_CONFIG3_REGNUM = 4'h5;
localparam HV_OUT_CONFIG_REGNUM = 4'h6;
localparam HV_OUT_CONFIG2_REGNUM = 4'h7;
localparam HV_OUT_CONFIG3_REGNUM = 4'h8;
localparam XY_OUT_CONFIG_REGNUM = 4'h9;
localparam XY_OUT_CONFIG2_REGNUM = 4'ha;
localparam MISC_CONFIG_REGNUM = 4'hb;
localparam SL_CONFIG_REGNUM = 4'hc;
localparam SL_CONFIG2_REGNUM = 4'hd;
localparam SL_CONFIG3_REGNUM = 4'he;
localparam FE_STATUS_REGNUM = 9'h0;
localparam FE_STATUS2_REGNUM = 9'h1;
localparam LT_STATUS_REGNUM = 9'h2;
localparam HV_IN_CONFIG_REGNUM = 9'h3;
localparam HV_IN_CONFIG2_REGNUM = 9'h4;
localparam HV_IN_CONFIG3_REGNUM = 9'h5;
localparam HV_OUT_CONFIG_REGNUM = 9'h6;
localparam HV_OUT_CONFIG2_REGNUM = 9'h7;
localparam HV_OUT_CONFIG3_REGNUM = 9'h8;
localparam XY_OUT_CONFIG_REGNUM = 9'h9;
localparam XY_OUT_CONFIG2_REGNUM = 9'ha;
localparam MISC_CONFIG_REGNUM = 9'hb;
localparam SL_CONFIG_REGNUM = 9'hc;
localparam SL_CONFIG2_REGNUM = 9'hd;
localparam SL_CONFIG3_REGNUM = 9'he;
localparam LUMACODE_RAM_START = 9'h10;
reg [31:0] config_reg[HV_IN_CONFIG_REGNUM:SL_CONFIG3_REGNUM] /* synthesis ramstyle = "logic" */;
@@ -118,4 +125,51 @@ assign sl_config_o = config_reg[SL_CONFIG_REGNUM];
assign sl_config2_o = config_reg[SL_CONFIG2_REGNUM];
assign sl_config3_o = config_reg[SL_CONFIG3_REGNUM];
// Lumacode palette RAM
altsyncram lumacode_pal_ram (
.address_a (avalon_s_address),
.address_b (lumacode_addr_i),
.clock0 (clk_i),
.clock1 (lumacode_clk_i),
.data_a (avalon_s_writedata),
.rden_b (lumacode_rden_i),
.wren_a (avalon_s_chipselect && avalon_s_write && (avalon_s_address >= LUMACODE_RAM_START)),
.q_b (lumacode_data_o),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
lumacode_pal_ram.address_aclr_b = "NONE",
lumacode_pal_ram.address_reg_b = "CLOCK1",
lumacode_pal_ram.clock_enable_input_a = "BYPASS",
lumacode_pal_ram.clock_enable_input_b = "BYPASS",
lumacode_pal_ram.clock_enable_output_b = "BYPASS",
lumacode_pal_ram.intended_device_family = "Cyclone IV E",
lumacode_pal_ram.lpm_type = "altsyncram",
lumacode_pal_ram.numwords_a = 512,
lumacode_pal_ram.numwords_b = 512,
lumacode_pal_ram.operation_mode = "DUAL_PORT",
lumacode_pal_ram.outdata_aclr_b = "NONE",
lumacode_pal_ram.outdata_reg_b = "UNREGISTERED",
lumacode_pal_ram.power_up_uninitialized = "FALSE",
lumacode_pal_ram.rdcontrol_reg_b = "CLOCK1",
lumacode_pal_ram.widthad_a = 9,
lumacode_pal_ram.widthad_b = 9,
lumacode_pal_ram.width_a = 32,
lumacode_pal_ram.width_b = 32,
lumacode_pal_ram.width_byteena_a = 1;
endmodule