RomanRom2/ossc
1
0 Fork 0
mirror of https://github.com/marqs85/ossc synced 2026-11-02 13:17:18 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity

* Clean up some FPGA code

Browse Source 
* Wrap sampling phase setting
* Enable hal.enable_lightweight_device_driver_api to reduce CPU code size
This commit is contained in:
marqs committed 2016-12-31 14:18:21 +02:00
1 parent 0f8439abf3
commit d77c293b70
15 files changed
+1086 -1056
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

ossc.sdc
+4 -2
View File
@@ -2,9 +2,11 @@
create_clock -period 27MHz -name clk27 [get_ports clk27]
set_input_delay -clock clk27 0 [get_ports {sda scl ir_rx HDMI_TX_INT_N SD_CMD SD_DAT* btn* *ALTERA_DATA0}]
set_input_delay -clock clk27 0 [get_ports {sda scl SD_CMD SD_DAT* *ALTERA_DATA0}]
set_false_path -from [get_ports {btn* ir_rx HDMI_TX_INT_N HDMI_TX_MODE}]
set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
### Scanconverter clock constraints ###
create_clock -period 108MHz -name pclk_hdtv [get_ports PCLK_in]
@@ -27,7 +29,7 @@ create_generated_clock -master_clock pclk_ldtv_M3 -source {scanconverter_inst|pl
derive_clock_uncertainty
# input delay constraints
set critinputs [get_ports {R_in* G_in* B_in* FID_in HSYNC_in VSYNC_in}]
set critinputs [get_ports {R_in* G_in* B_in* HSYNC_in VSYNC_in FID_in}]
set_input_delay -clock pclk_sdtv -min 0 $critinputs
set_input_delay -clock pclk_sdtv -max 1.5 $critinputs
set_input_delay -clock pclk_hdtv -min 0 $critinputs -add_delay