* Clean up some FPGA code

* Wrap sampling phase setting
* Enable hal.enable_lightweight_device_driver_api to reduce CPU code size
This commit is contained in:
marqs committed 2016-12-31 14:18:21 +02:00
1 parent 0f8439abf3
commit d77c293b70
15 files changed
+1086 -1056

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@@ -156,8 +156,8 @@ void parse_control()
case RC_SL_MINUS: tc.sl_str = tc.sl_str ? (tc.sl_str - 1) : 0; break;
case RC_SL_PLUS: tc.sl_str = (tc.sl_str < SCANLINESTR_MAX) ? (tc.sl_str + 1) : SCANLINESTR_MAX; break;
case RC_LM_MODE: tc.linemult_target = (tc.linemult_target < LM_MODE_MAX) ? (tc.linemult_target + 1) : 0; break;
case RC_PHASE_PLUS: tc.sampler_phase = (tc.sampler_phase < SAMPLER_PHASE_MAX) ? (tc.sampler_phase + 1) : SAMPLER_PHASE_MAX; break;
case RC_PHASE_MINUS: tc.sampler_phase = tc.sampler_phase ? (tc.sampler_phase - 1) : 0; break;
case RC_PHASE_PLUS: tc.sampler_phase = (tc.sampler_phase < SAMPLER_PHASE_MAX) ? (tc.sampler_phase + 1) : 0; break;
case RC_PHASE_MINUS: tc.sampler_phase = tc.sampler_phase ? (tc.sampler_phase - 1) : SAMPLER_PHASE_MAX; break;
case RC_PROF_HOTKEY:
strncpy(menu_row1, "Profile load:", LCD_ROW_LEN+1);
strncpy(menu_row2, "press 0-9", LCD_ROW_LEN+1);
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@@ -105,7 +105,7 @@ static int check_fw_image(alt_u32 offset, alt_u32 size, alt_u32 golden_crc, alt_
#ifdef DEBUG
int fw_update()
{
sniprintf(menu_row2, LCD_ROW_LEN+1, "Not implemented");
sniprintf(menu_row2, LCD_ROW_LEN+1, "Unavailable");
lcd_write_menu();
usleep(1000000);
return -1;
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@@ -24,7 +24,7 @@
#include "sysconfig.h"
#define FW_VER_MAJOR 0
#define FW_VER_MINOR 74
#define FW_VER_MINOR 75
#ifdef DIY_AUDIO
#define FW_SUFFIX1 "a"
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@@ -86,7 +86,7 @@ MENU(menu_vinputproc, P99_PROTECT({ \
}))
MENU(menu_sampling, P99_PROTECT({ \
{ LNG("Sampling phase","サンヒプリングフェーズ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.sampler_phase, OPT_NOWRAP, 0, SAMPLER_PHASE_MAX, sampler_phase_disp } } },
{ LNG("Sampling phase","サンヒプリングフェーズ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.sampler_phase, OPT_WRAP, 0, SAMPLER_PHASE_MAX, sampler_phase_disp } } },
{ LNG("480p in sampler","サンプラーニ480p"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.s480p_mode, OPT_WRAP, SETTING_ITEM(s480p_mode_desc) } } },
{ LNG("<Adv. timing >","<カクシュタイミング>"), OPT_SUBMENU, { .sub = { &menu_advtiming, vm_display } } },
}))
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@@ -191,7 +191,8 @@ ALT_CPPFLAGS += -DALT_NO_EXIT
# devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.
# The Altera Host and read-only ZIP file systems can't be used if
# hal.enable_lightweight_device_driver_api is true.
# setting hal.enable_lightweight_device_driver_api is false
# setting hal.enable_lightweight_device_driver_api is true
ALT_CPPFLAGS += -DALT_USE_DIRECT_DRIVERS
# Adds code to emulate multiply and divide instructions in case they are
# executed but aren't present in the CPU. Normally this isn't required because
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@@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Dec 13, 2016 8:52:43 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1481655163358</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>Dec 31, 2016 11:50:32 AM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1483177832665</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
@@ -806,7 +806,7 @@
<SettingName>hal.enable_lightweight_device_driver_api</SettingName>
<Identifier>ALT_USE_DIRECT_DRIVERS</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<Value>1</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.</Description>
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@@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
* SOPC Builder design path: ../../sys.sopcinfo
*
* Generated: Thu Oct 20 01:24:13 EEST 2016
* Generated: Sat Dec 31 11:45:57 EET 2016
*/
/*