diff --git a/rtl/lpm_mult_4_hybr_ref_pre.qip b/rtl/lpm_mult_4_hybr_ref_pre.qip new file mode 100644 index 0000000..04f0083 --- /dev/null +++ b/rtl/lpm_mult_4_hybr_ref_pre.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MULT" +set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_pre.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_pre_bb.v"] diff --git a/rtl/lpm_mult_4_hybr_ref_pre.v b/rtl/lpm_mult_4_hybr_ref_pre.v new file mode 100644 index 0000000..2bbca20 --- /dev/null +++ b/rtl/lpm_mult_4_hybr_ref_pre.v @@ -0,0 +1,116 @@ +// megafunction wizard: %LPM_MULT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: lpm_mult + +// ============================================================ +// File Name: lpm_mult_4_hybr_ref_pre.v +// Megafunction Name(s): +// lpm_mult +// +// Simulation Library Files(s): +// lpm +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module lpm_mult_4_hybr_ref_pre ( + clock, + dataa, + datab, + result); + + input clock; + input [7:0] dataa; + input [4:0] datab; + output [8:0] result; + + wire [8:0] sub_wire0; + wire [8:0] result = sub_wire0[8:0]; + + lpm_mult lpm_mult_component ( + .clock (clock), + .dataa (dataa), + .datab (datab), + .result (sub_wire0), + .aclr (1'b0), + .clken (1'b1), + .sclr (1'b0), + .sum (1'b0)); + defparam + lpm_mult_component.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9", + lpm_mult_component.lpm_pipeline = 1, + lpm_mult_component.lpm_representation = "UNSIGNED", + lpm_mult_component.lpm_type = "LPM_MULT", + lpm_mult_component.lpm_widtha = 8, + lpm_mult_component.lpm_widthb = 5, + lpm_mult_component.lpm_widthp = 9; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "0" +// Retrieval info: PRIVATE: B_isConstant NUMERIC "0" +// Retrieval info: PRIVATE: ConstantB NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1" +// Retrieval info: PRIVATE: Latency NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SignedMult NUMERIC "0" +// Retrieval info: PRIVATE: USE_MULT NUMERIC "1" +// Retrieval info: PRIVATE: ValidConstant NUMERIC "0" +// Retrieval info: PRIVATE: WidthA NUMERIC "8" +// Retrieval info: PRIVATE: WidthB NUMERIC "5" +// Retrieval info: PRIVATE: WidthP NUMERIC "9" +// Retrieval info: PRIVATE: aclr NUMERIC "0" +// Retrieval info: PRIVATE: clken NUMERIC "0" +// Retrieval info: PRIVATE: new_diagram STRING "1" +// Retrieval info: PRIVATE: optimize NUMERIC "1" +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all +// Retrieval info: CONSTANT: LPM_HINT STRING "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9" +// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" +// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT" +// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "8" +// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "5" +// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "9" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]" +// Retrieval info: USED_PORT: datab 0 0 5 0 INPUT NODEFVAL "datab[4..0]" +// Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL "result[8..0]" +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0 +// Retrieval info: CONNECT: @datab 0 0 5 0 datab 0 0 5 0 +// Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre_bb.v TRUE +// Retrieval info: LIB_FILE: lpm diff --git a/rtl/lpm_mult_4_hybr_ref_pre_bb.v b/rtl/lpm_mult_4_hybr_ref_pre_bb.v new file mode 100644 index 0000000..dcf1b54 --- /dev/null +++ b/rtl/lpm_mult_4_hybr_ref_pre_bb.v @@ -0,0 +1,89 @@ +// megafunction wizard: %LPM_MULT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: lpm_mult + +// ============================================================ +// File Name: lpm_mult_4_hybr_ref_pre.v +// Megafunction Name(s): +// lpm_mult +// +// Simulation Library Files(s): +// lpm +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition +// ************************************************************ + +//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + +module lpm_mult_4_hybr_ref_pre ( + clock, + dataa, + datab, + result); + + input clock; + input [7:0] dataa; + input [4:0] datab; + output [8:0] result; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "0" +// Retrieval info: PRIVATE: B_isConstant NUMERIC "0" +// Retrieval info: PRIVATE: ConstantB NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1" +// Retrieval info: PRIVATE: Latency NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SignedMult NUMERIC "0" +// Retrieval info: PRIVATE: USE_MULT NUMERIC "1" +// Retrieval info: PRIVATE: ValidConstant NUMERIC "0" +// Retrieval info: PRIVATE: WidthA NUMERIC "8" +// Retrieval info: PRIVATE: WidthB NUMERIC "5" +// Retrieval info: PRIVATE: WidthP NUMERIC "9" +// Retrieval info: PRIVATE: aclr NUMERIC "0" +// Retrieval info: PRIVATE: clken NUMERIC "0" +// Retrieval info: PRIVATE: new_diagram STRING "1" +// Retrieval info: PRIVATE: optimize NUMERIC "1" +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all +// Retrieval info: CONSTANT: LPM_HINT STRING "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9" +// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" +// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT" +// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "8" +// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "5" +// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "9" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]" +// Retrieval info: USED_PORT: datab 0 0 5 0 INPUT NODEFVAL "datab[4..0]" +// Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL "result[8..0]" +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0 +// Retrieval info: CONNECT: @datab 0 0 5 0 datab 0 0 5 0 +// Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre_bb.v TRUE +// Retrieval info: LIB_FILE: lpm