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https://github.com/marqs85/ossc
synced 2025-04-09 22:56:34 +03:00
add support for 480p/576p Line3x
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marqs
parent
dae7b0b250
commit
e4cec87bec
@ -123,7 +123,7 @@ int parse_control()
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// one for each video_group
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alt_u8* pmcfg_ptr[] = { &pt_only, &tc.pm_240p, &tc.pm_240p, &tc.pm_384p, &tc.pm_480i, &tc.pm_480i, &tc.pm_480p, &tc.pm_480p, &pt_only, &tc.pm_1080i, &pt_only };
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alt_u8 valid_pm[] = { 0x1, 0x3f, 0x3f, 0x7, 0xf, 0xf, 0x3, 0x3, 0x1, 0x3, 0x1 };
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alt_u8 valid_pm[] = { 0x1, 0x3f, 0x3f, 0x7, 0xf, 0xf, 0x7, 0x7, 0x1, 0x3, 0x1 };
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avinput_t next_input = (cm.avinput == AV3_YPBPR) ? AV1_RGBs : (cm.avinput+1);
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@ -62,7 +62,7 @@ static const char *l5_fmt_desc[] = { "1920x1080", "1600x1200", "1920x1200" };
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static const char *pm_240p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x", "Line4x", "Line5x", "Line6x" };
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static const char *pm_480i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)", "Line3x (laced)", "Line4x (bob)" };
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static const char *pm_384p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x Generic", "Line2x 240x360", "Line3x 240x360" };
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static const char *pm_480p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x" };
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static const char *pm_480p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x Generic" };
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static const char *pm_1080i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)" };
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static const char *ar_256col_desc[] = { "Pseudo 4:3 DAR", "1:1 PAR" };
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static const char *tx_mode_desc[] = { "HDMI (RGB)", "HDMI (YCbCr444)", "DVI" };
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@ -80,8 +80,9 @@ static const char *auto_input_desc[] = { "Off", "Current input", "All inputs" };
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static const char *mask_color_desc[] = { "Black", "Blue", "Green", "Cyan", "Red", "Magenta", "Yellow", "White" };
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static const char *av3_alt_rgb_desc[] = { "Off", "AV1", "AV2" };
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static const char *shmask_mode_desc[] = { "Off", "A-Grille", "TV", "PVM" };
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static const char *lumacode_mode_desc[] = { "Off", "C64", "Spectrum", "Coleco/MSX" };
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static const char *pll_bw_desc[] = { "High", "Low" };
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static const char *lumacode_mode_desc[] = { "Off", "C64", "Spectrum", "Coleco/MSX", "NES" };
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static const char *adc_pll_bw_desc[] = { "High", "Medium", "Low", "Ultra low" };
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static const char *fpga_pll_bw_desc[] = { "High", "Low" };
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static void sync_vth_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%d mV", (v*1127)/100); }
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static void intclks_to_time_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u.%.2u us", (unsigned)(((1000000U*v)/(TVP_INTCLK_HZ/1000))/1000), (unsigned)((((1000000U*v)/(TVP_INTCLK_HZ/1000))%1000)/10)); }
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@ -174,8 +175,8 @@ MENU(menu_sync, P99_PROTECT({ \
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{ LNG("Vsync threshold","Vsyncｼｷｲﾁ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.vsync_thold, OPT_NOWRAP, VSYNC_THOLD_MIN, VSYNC_THOLD_MAX, intclks_to_time_disp } } },
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{ "H-PLL Pre-Coast", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.pre_coast, OPT_NOWRAP, 0, PLL_COAST_MAX, lines_disp } } },
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{ "H-PLL Post-Coast", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.post_coast, OPT_NOWRAP, 0, PLL_COAST_MAX, lines_disp } } },
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{ "ADC PLL BW", OPT_AVCONFIG_SELECTION, { .sel = { &tc.adc_pll_bw, OPT_WRAP, SETTING_ITEM(pll_bw_desc) } } },
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{ "FPGA PLL BW", OPT_AVCONFIG_SELECTION, { .sel = { &tc.fpga_pll_bw, OPT_WRAP, SETTING_ITEM(pll_bw_desc) } } },
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{ "ADC PLL BW", OPT_AVCONFIG_SELECTION, { .sel = { &tc.adc_pll_bw, OPT_WRAP, SETTING_ITEM(adc_pll_bw_desc) } } },
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{ "FPGA PLL BW", OPT_AVCONFIG_SELECTION, { .sel = { &tc.fpga_pll_bw, OPT_WRAP, SETTING_ITEM(fpga_pll_bw_desc) } } },
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}))
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MENU(menu_output, P99_PROTECT({ \
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@ -206,7 +207,9 @@ MENU(menu_scanlines, P99_PROTECT({ \
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{ "Sl. alternating", OPT_AVCONFIG_SELECTION, { .sel = { &tc.sl_altern, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
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{ LNG("Sl. alignment","ｽｷｬﾝﾗｲﾝﾎﾟｼﾞｼｮﾝ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.sl_id, OPT_WRAP, SETTING_ITEM(sl_id_desc) } } },
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{ LNG("Sl. type","ｽｷｬﾝﾗｲﾝﾙｲ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.sl_type, OPT_WRAP, SETTING_ITEM(sl_type_desc) } } },
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#ifndef DEBUG
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{ "< Custom Sl. >", OPT_SUBMENU, { .sub = { &menu_cust_sl, NULL, NULL } } },
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#endif
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}))
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MENU(menu_postproc, P99_PROTECT({ \
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@ -169,7 +169,7 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
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break;
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case GROUP_480I:
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case GROUP_576I:
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//fixed Line3x/4x mode for 480i
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//fixed Line3x/4x mode for 480i and onwards
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valid_lm[2] = MODE_L3_GEN_16_9;
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valid_lm[3] = MODE_L4_GEN_4_3;
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break;
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@ -399,7 +399,9 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
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}
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// Force TX pixel-repeat for high bandwidth modes
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if (((mindiff_lm == MODE_L5_GEN_4_3) && (mode_preset->group == GROUP_288P)) || (mindiff_lm == MODE_L3_240x360) || (mindiff_lm >= MODE_L6_GEN_4_3))
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if (((mindiff_lm == MODE_L5_GEN_4_3) && (mode_preset->group == GROUP_288P)) ||
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((mindiff_lm == MODE_L3_GEN_16_9) && ((mode_preset->group == GROUP_480P) || (mode_preset->group == GROUP_576P))) ||
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(mindiff_lm == MODE_L3_240x360) || (mindiff_lm >= MODE_L6_GEN_4_3))
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vm_conf->tx_pixelrep = 1;
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sniprintf(vm_out->name, 11, "%s x%u", vm_in->name, vm_conf->y_rpt+1);
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@ -108,7 +108,7 @@ typedef enum {
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} mode_flags;
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typedef enum {
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VMODE_480p = 23,
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VMODE_480p = 24,
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} vmode_t;
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typedef struct {
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@ -54,6 +54,7 @@ const mode_data_t video_modes_plm_default[] = {
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{ "640x384", HDMI_Unknown, { 640, 384, 5500, 800, 0, 492, 48, 63, 96, 2, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2), },
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/* ~525-line modes */
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{ "480i", HDMI_480i60, { 720, 240, 5994, 858, 0, 525, 57, 15, 62, 3, 1}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_480I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3), },
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{ "1920x480", HDMI_Unknown, { 960, 480, 5994, 1287, 0, 525, 150, 30, 93, 6, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_480P, (MODE_L3_GEN_16_9), },
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{ "480p", HDMI_480p60, { 720, 480, 5994, 858, 0, 525, 60, 30, 62, 6, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_480P, (MODE_PT | MODE_L2), },
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{ "640x480_60", HDMI_640x480p60, { 640, 480, 6000, 800, 0, 525, 48, 33, 96, 2, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_480P, (MODE_PT | MODE_L2), },
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/* 480p PSP in-game */ \
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@ -62,6 +63,7 @@ const mode_data_t video_modes_plm_default[] = {
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{ "640x512", HDMI_Unknown, { 640, 512, 6000, 800, 0, 568, 48, 34, 96, 6, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_480P, (MODE_PT | MODE_L2), },
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/* ~625-line modes */
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{ "576i", HDMI_576i50, { 720, 288, 5000, 864, 0, 625, 69, 19, 63, 3, 1}, DEF_PHASE, {{ 0, 0}}, VIDEO_SDTV, GROUP_576I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3), },
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{ "1920x480LB", HDMI_Unknown, { 960, 480, 5000, 1296, 0, 625, 162, 87, 96, 5, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_576P, (MODE_L3_GEN_16_9), },
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{ "576p", HDMI_576p50, { 720, 576, 5000, 864, 0, 625, 68, 39, 64, 5, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_EDTV, GROUP_576P, (MODE_PT | MODE_L2), },
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{ "800x600_60", HDMI_Unknown, { 800, 600, 6000, 1056, 0, 628, 88, 23, 128, 4, 0}, DEF_PHASE, {{ 0, 0}}, VIDEO_PC, GROUP_NONE, MODE_PT, },
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/* CEA 720p modes */
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