diff --git a/.gitmodules b/.gitmodules index 0495bad..d5bc5c3 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,3 @@ -[submodule "ip/pulpino_qsys"] - path = ip/pulpino_qsys - url = https://github.com/marqs85/pulpino_qsys.git +[submodule "ip/ibex_qsys"] + path = ip/ibex_qsys + url = git@github.com:marqs85/ibex_qsys.git diff --git a/ip/ibex_qsys b/ip/ibex_qsys new file mode 160000 index 0000000..95fd422 --- /dev/null +++ b/ip/ibex_qsys @@ -0,0 +1 @@ +Subproject commit 95fd422a056dcbb63f535c04f5eb5e54f78cd99d diff --git a/ip/pulpino_qsys b/ip/pulpino_qsys deleted file mode 160000 index dfb0af0..0000000 --- a/ip/pulpino_qsys +++ /dev/null @@ -1 +0,0 @@ -Subproject commit dfb0af0ed3b4e9e72e444eba2b1c149b5adad2cc diff --git a/ossc.cof b/ossc.cof index acdcc88..939b47d 100644 --- a/ossc.cof +++ b/ossc.cof @@ -10,9 +10,15 @@ Page_0 1 - output_files/ossc.sof1 + output_files/ossc.sof + + software/sys_controller/mem_init/flash.hex + relative + 524288 + 0 + 10 0 0 @@ -22,7 +28,7 @@ 0 - 0 + 1 2 0 -1 diff --git a/ossc.qsf b/ossc.qsf index 243d454..d3bd9b3 100644 --- a/ossc.qsf +++ b/ossc.qsf @@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE15E22C8 set_global_assignment -name TOP_LEVEL_ENTITY ossc set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03 MAY 17, 2014" -set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.1 Lite Edition" +set_global_assignment -name LAST_QUARTUS_VERSION "24.1std.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 @@ -172,9 +172,8 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name INI_VARS "FIOMGR_ENABLE_SPI_TIMING=ON" - -set_global_assignment -name SEARCH_PATH rtl set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 @@ -231,6 +230,12 @@ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[7] set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[1] set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[5] set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[7] + + + + + + set_global_assignment -name VERILOG_FILE rtl/videogen.v set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v set_global_assignment -name VERILOG_FILE rtl/ossc.v @@ -249,10 +254,8 @@ set_global_assignment -name SDC_FILE ossc.sdc set_global_assignment -name CDF_FILE output_files/Chain1.cdf set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp set_global_assignment -name QIP_FILE rtl/char_array.qip - - - - - - +set_global_assignment -name SEARCH_PATH rtl +set_global_assignment -name SEARCH_PATH software/sys_controller/mem_init/ +set_global_assignment -name SEARCH_PATH ip/ibex_qsys/rtl_extra +set_global_assignment -name VERILOG_MACRO "SYNTHESIS=" set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/rtl/char_array.qip b/rtl/char_array.qip index 7bbcb8b..a59d0a8 100644 --- a/rtl/char_array.qip +++ b/rtl/char_array.qip @@ -1,6 +1,4 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" -set_global_assignment -name IP_TOOL_VERSION "23.1" +set_global_assignment -name IP_TOOL_VERSION "24.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_array.v"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_inst.v"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_bb.v"] diff --git a/rtl/char_array.v b/rtl/char_array.v index 79240a2..d4a3607 100644 --- a/rtl/char_array.v +++ b/rtl/char_array.v @@ -14,24 +14,24 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 23.1std.1 Build 993 05/14/2024 SC Lite Edition +// 24.1std.0 Build 1077 03/04/2025 SC Lite Edition // ************************************************************ -//Copyright (C) 2024 Intel Corporation. All rights reserved. -//Your use of Intel Corporation's design tools, logic functions +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions //and other software and tools, and any partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject -//to the terms and conditions of the Intel Program License -//Subscription Agreement, the Intel Quartus Prime License Agreement, -//the Intel FPGA IP License Agreement, or other applicable license +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license //agreement, including, without limitation, that your use is for //the sole purpose of programming logic devices manufactured by -//Intel and sold by Intel or its authorized distributors. Please -//refer to the applicable agreement for further details, at -//https://fpgasoftware.intel.com/eula. +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. // synopsys translate_off @@ -218,6 +218,6 @@ endmodule // Retrieval info: GEN_FILE: TYPE_NORMAL char_array.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL char_array.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL char_array.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_bb.v FALSE // Retrieval info: LIB_FILE: altera_mf diff --git a/rtl/char_rom.qip b/rtl/char_rom.qip index 625ec26..f2ad035 100644 --- a/rtl/char_rom.qip +++ b/rtl/char_rom.qip @@ -1,6 +1,4 @@ set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "23.1" +set_global_assignment -name IP_TOOL_VERSION "24.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_rom.v"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_inst.v"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_bb.v"] diff --git a/rtl/char_rom.v b/rtl/char_rom.v index d9453e2..b83469f 100644 --- a/rtl/char_rom.v +++ b/rtl/char_rom.v @@ -14,24 +14,24 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 23.1std.1 Build 993 05/14/2024 SC Lite Edition +// 24.1std.0 Build 1077 03/04/2025 SC Lite Edition // ************************************************************ -//Copyright (C) 2024 Intel Corporation. All rights reserved. -//Your use of Intel Corporation's design tools, logic functions +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions //and other software and tools, and any partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject -//to the terms and conditions of the Intel Program License -//Subscription Agreement, the Intel Quartus Prime License Agreement, -//the Intel FPGA IP License Agreement, or other applicable license +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license //agreement, including, without limitation, that your use is for //the sole purpose of programming logic devices manufactured by -//Intel and sold by Intel or its authorized distributors. Please -//refer to the applicable agreement for further details, at -//https://fpgasoftware.intel.com/eula. +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. // synopsys translate_off @@ -160,6 +160,6 @@ endmodule // Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom_bb.v FALSE // Retrieval info: LIB_FILE: altera_mf diff --git a/rtl/linebuf.qip b/rtl/linebuf.qip index 9fe20c8..37ac7e8 100644 --- a/rtl/linebuf.qip +++ b/rtl/linebuf.qip @@ -1,4 +1,4 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" -set_global_assignment -name IP_TOOL_VERSION "23.1" +set_global_assignment -name IP_TOOL_VERSION "24.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "linebuf.v"] diff --git a/rtl/linebuf.v b/rtl/linebuf.v index 4190b1f..5980edd 100644 --- a/rtl/linebuf.v +++ b/rtl/linebuf.v @@ -14,24 +14,24 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 23.1std.1 Build 993 05/14/2024 SC Lite Edition +// 24.1std.0 Build 1077 03/04/2025 SC Lite Edition // ************************************************************ -//Copyright (C) 2024 Intel Corporation. All rights reserved. -//Your use of Intel Corporation's design tools, logic functions +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions //and other software and tools, and any partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject -//to the terms and conditions of the Intel Program License -//Subscription Agreement, the Intel Quartus Prime License Agreement, -//the Intel FPGA IP License Agreement, or other applicable license +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license //agreement, including, without limitation, that your use is for //the sole purpose of programming logic devices manufactured by -//Intel and sold by Intel or its authorized distributors. Please -//refer to the applicable agreement for further details, at -//https://fpgasoftware.intel.com/eula. +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. // synopsys translate_off diff --git a/rtl/lpm_mult_8x5_9.qip b/rtl/lpm_mult_8x5_9.qip index ed60fb5..e8b5455 100644 --- a/rtl/lpm_mult_8x5_9.qip +++ b/rtl/lpm_mult_8x5_9.qip @@ -1,4 +1,4 @@ set_global_assignment -name IP_TOOL_NAME "LPM_MULT" -set_global_assignment -name IP_TOOL_VERSION "23.1" +set_global_assignment -name IP_TOOL_VERSION "24.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_8x5_9.v"] diff --git a/rtl/lpm_mult_8x5_9.v b/rtl/lpm_mult_8x5_9.v index e27b9dc..eaf896d 100644 --- a/rtl/lpm_mult_8x5_9.v +++ b/rtl/lpm_mult_8x5_9.v @@ -14,24 +14,24 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 23.1std.1 Build 993 05/14/2024 SC Lite Edition +// 24.1std.0 Build 1077 03/04/2025 SC Lite Edition // ************************************************************ -//Copyright (C) 2024 Intel Corporation. All rights reserved. -//Your use of Intel Corporation's design tools, logic functions +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions //and other software and tools, and any partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject -//to the terms and conditions of the Intel Program License -//Subscription Agreement, the Intel Quartus Prime License Agreement, -//the Intel FPGA IP License Agreement, or other applicable license +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license //agreement, including, without limitation, that your use is for //the sole purpose of programming logic devices manufactured by -//Intel and sold by Intel or its authorized distributors. Please -//refer to the applicable agreement for further details, at -//https://fpgasoftware.intel.com/eula. +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. // synopsys translate_off diff --git a/rtl/lpm_mult_sl.qip b/rtl/lpm_mult_sl.qip index b6c579b..73ba150 100644 --- a/rtl/lpm_mult_sl.qip +++ b/rtl/lpm_mult_sl.qip @@ -1,4 +1,4 @@ set_global_assignment -name IP_TOOL_NAME "LPM_MULT" -set_global_assignment -name IP_TOOL_VERSION "23.1" +set_global_assignment -name IP_TOOL_VERSION "24.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_sl.v"] diff --git a/rtl/lpm_mult_sl.v b/rtl/lpm_mult_sl.v index 7818116..1c3c5f3 100644 --- a/rtl/lpm_mult_sl.v +++ b/rtl/lpm_mult_sl.v @@ -14,24 +14,24 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 23.1std.1 Build 993 05/14/2024 SC Lite Edition +// 24.1std.0 Build 1077 03/04/2025 SC Lite Edition // ************************************************************ -//Copyright (C) 2024 Intel Corporation. All rights reserved. -//Your use of Intel Corporation's design tools, logic functions +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions //and other software and tools, and any partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject -//to the terms and conditions of the Intel Program License -//Subscription Agreement, the Intel Quartus Prime License Agreement, -//the Intel FPGA IP License Agreement, or other applicable license +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license //agreement, including, without limitation, that your use is for //the sole purpose of programming logic devices manufactured by -//Intel and sold by Intel or its authorized distributors. Please -//refer to the applicable agreement for further details, at -//https://fpgasoftware.intel.com/eula. +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. // synopsys translate_off diff --git a/rtl/ossc.v b/rtl/ossc.v index 474bf10..e64c39e 100644 --- a/rtl/ossc.v +++ b/rtl/ossc.v @@ -365,10 +365,8 @@ defparam sys sys_inst( .clk_clk (clk27), .reset_reset_n (sys_reset_n), - .pulpino_0_config_testmode_i (1'b0), - .pulpino_0_config_fetch_enable_i (1'b1), - .pulpino_0_config_clock_gating_i (1'b0), - .pulpino_0_config_boot_addr_i (32'h00010000), + .ibex_0_config_boot_addr_i (32'h02080000), + .ibex_0_config_core_sleep_o (), .master_0_master_reset_reset (jtagm_reset_req), .i2c_opencores_0_export_scl_pad_io (scl), .i2c_opencores_0_export_sda_pad_io (sda), @@ -408,10 +406,7 @@ sys sys_inst( // These do not work in current Quartus version (23.1) and a patch file (scripts/qsys.patch) must be used after Qsys generation instead defparam - sys_inst.epcq_controller2_0.asmi2_inst_epcq_ctrl.xip_controller.avst_fifo_inst.USE_MEMORY_BLOCKS = 0, - sys_inst.epcq_controller2_0.asmi2_inst_epcq_ctrl.xip_controller.avst_fifo_inst.avst_fifo.USE_MEMORY_BLOCKS = 0, - sys_inst.master_0.fifo.USE_MEMORY_BLOCKS = 0, - sys_inst.onchip_memory2_0.the_altsyncram.MAXIMUM_DEPTH = 2048; + sys_inst.master_0.fifo.USE_MEMORY_BLOCKS = 0; scanconverter #( .EMIF_ENABLE(0), diff --git a/rtl/pll_2x.qip b/rtl/pll_2x.qip index 9716b1d..4313742 100644 --- a/rtl/pll_2x.qip +++ b/rtl/pll_2x.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "23.1" +set_global_assignment -name IP_TOOL_VERSION "24.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x.ppf"] diff --git a/rtl/pll_2x.v b/rtl/pll_2x.v index 4b590d1..821681d 100644 --- a/rtl/pll_2x.v +++ b/rtl/pll_2x.v @@ -9,29 +9,29 @@ // altpll // // Simulation Library Files(s): -// +// altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 23.1std.1 Build 993 05/14/2024 SC Lite Edition +// 24.1std.0 Build 1077 03/04/2025 SC Lite Edition // ************************************************************ -//Copyright (C) 2024 Intel Corporation. All rights reserved. -//Your use of Intel Corporation's design tools, logic functions +//Copyright (C) 2025 Altera Corporation. All rights reserved. +//Your use of Altera Corporation's design tools, logic functions //and other software and tools, and any partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject -//to the terms and conditions of the Intel Program License -//Subscription Agreement, the Intel Quartus Prime License Agreement, -//the Intel FPGA IP License Agreement, or other applicable license +//to the terms and conditions of the Altera Program License +//Subscription Agreement, the Altera Quartus Prime License Agreement, +//the Altera IP License Agreement, or other applicable license //agreement, including, without limitation, that your use is for //the sole purpose of programming logic devices manufactured by -//Intel and sold by Intel or its authorized distributors. Please -//refer to the applicable agreement for further details, at -//https://fpgasoftware.intel.com/eula. +//Altera and sold by Altera or its authorized distributors. Please +//refer to the Altera Software License Subscription Agreements +//on the Quartus Prime software download page. // synopsys translate_off @@ -377,4 +377,5 @@ endmodule // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.mif TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.hex TRUE +// Retrieval info: LIB_FILE: altera_mf // Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/rtl/tvp7002_frontend.v b/rtl/tvp7002_frontend.v index 6e99bdb..252fd9b 100644 --- a/rtl/tvp7002_frontend.v +++ b/rtl/tvp7002_frontend.v @@ -167,7 +167,7 @@ wire [7:0] lumacode_data_3s_G = lumacode_data_3s[{lc_code[1], lc_code[2], lc_cod wire [7:0] lumacode_data_3s_B = lumacode_data_3s[{lc_code[1], lc_code[2], lc_code[3]}][7:0]; // Lumacode palette Atari GTIA -wire [23:0] lumacode_data_gtia[0:255] = '{ +/*wire [23:0] lumacode_data_gtia[0:255] = '{ 24'h000000, 24'h111111, 24'h222222, 24'h333333, 24'h444444, 24'h555555, 24'h666666, 24'h777777, 24'h888888, 24'h999999, 24'haaaaaa, 24'hbbbbbb, 24'hcccccc, 24'hdddddd, 24'heeeeee, 24'hffffff, 24'h091900, 24'h192806, 24'h29370d, 24'h3a4714, 24'h4a561b, 24'h5a6522, 24'h6b7529, 24'h7b8430, 24'h8c9336, 24'h9ca33d, 24'hacb244, 24'hbdc14b, 24'hcdd152, 24'hdee059, 24'heeef60, 24'hffff67, 24'h300000, 24'h3d1108, 24'h4b2211, 24'h593319, 24'h674422, 24'h75552a, 24'h826633, 24'h90773b, 24'h9e8844, 24'hac994c, 24'hbaaa55, 24'hc7bb5d, 24'hd5cc66, 24'he3dd6e, 24'hf1ee77, 24'hffff80, @@ -183,10 +183,10 @@ wire [23:0] lumacode_data_gtia[0:255] = '{ 24'h003400, 24'h0c410a, 24'h194f14, 24'h265c1e, 24'h336a28, 24'h407732, 24'h4c853c, 24'h599246, 24'h66a050, 24'h73ad5a, 24'h80bb64, 24'h8cc86e, 24'h99d678, 24'ha6e382, 24'hb3f18c, 24'hc0ff97, 24'h002a00, 24'h0f3807, 24'h1e460e, 24'h2d5416, 24'h3c621d, 24'h4b7124, 24'h5a7f2c, 24'h698d33, 24'h799b3b, 24'h88a942, 24'h97b849, 24'ha6c651, 24'hb5d458, 24'hc4e260, 24'hd3f067, 24'he3ff6f, 24'h0d1700, 24'h1d2606, 24'h2d350d, 24'h3d4514, 24'h4d541b, 24'h5d6422, 24'h6d7329, 24'h7d8330, 24'h8e9237, 24'h9ea23e, 24'haeb145, 24'hbec14c, 24'hced053, 24'hdee05a, 24'heeef61, 24'hffff68, -24'h330000, 24'h401008, 24'h4e2111, 24'h5b321a, 24'h694323, 24'h77542c, 24'h846535, 24'h92763e, 24'h9f8646, 24'had974f, 24'hbba858, 24'hc8b961, 24'hd6ca6a, 24'he3db73, 24'hf1ec7c, 24'hfffd85}; +24'h330000, 24'h401008, 24'h4e2111, 24'h5b321a, 24'h694323, 24'h77542c, 24'h846535, 24'h92763e, 24'h9f8646, 24'had974f, 24'hbba858, 24'hc8b961, 24'hd6ca6a, 24'he3db73, 24'hf1ec7c, 24'hfffd85};*/ // Lumacode palette Atari CTIA/TIA -wire [23:0] lumacode_data_ctia[0:127] = '{ +/*wire [23:0] lumacode_data_ctia[0:127] = '{ 24'h000000, 24'h404040, 24'h6C6C6C, 24'h909090, 24'hB0B0B0, 24'hC8C8C8, 24'hDCDCDC, 24'hECECEC, 24'h444400, 24'h646410, 24'h848424, 24'hA0A034, 24'hB8B840, 24'hD0D050, 24'hE8E85C, 24'hFCFC68, 24'h702800, 24'h844414, 24'h985C28, 24'hAC783C, 24'hBC8C4C, 24'hCCA05C, 24'hDCB468, 24'hECC878, @@ -202,7 +202,7 @@ wire [23:0] lumacode_data_ctia[0:127] = '{ 24'h003C00, 24'h205C20, 24'h407C40, 24'h5C9C5C, 24'h74B474, 24'h8CD08C, 24'hA4E4A4, 24'hB8FCB8, 24'h143800, 24'h345C1C, 24'h507C38, 24'h6C9850, 24'h84B468, 24'h9CCC7C, 24'hB4E490, 24'hC8FCA4, 24'h2C3000, 24'h4C501C, 24'h687034, 24'h848C4C, 24'h9CA864, 24'hB4C078, 24'hCCD488, 24'hE0EC9C, -24'h442800, 24'h644818, 24'h846830, 24'hA08444, 24'hB89C58, 24'hD0B46C, 24'hE8CC7C, 24'hFCE08C}; +24'h442800, 24'h644818, 24'h846830, 24'hA08444, 24'hB89C58, 24'hD0B46C, 24'hE8CC7C, 24'hFCE08C};*/ // SOF position for scaler wire [10:0] V_SOF_LINE = hv_in_config3[23:13]; @@ -350,11 +350,13 @@ always @(posedge PCLK_i) begin // Store hue and luma (high bits) for 1st pixel, and display last pixel of previous pair lc_atari_hue <= {lc_code[1], lc_code[2]}; lc_atari_luma[3:2] <= lc_code[3]; - {R_pp[2], G_pp[2], B_pp[2]} <= lumacode_data_gtia[{lc_atari_hue, lc_atari_luma}]; + //{R_pp[2], G_pp[2], B_pp[2]} <= lumacode_data_gtia[{lc_atari_hue, lc_atari_luma}]; + {R_pp[2], G_pp[2], B_pp[2]} <= '0; end else begin // Store luma for 2nd pixel, and display first pixel of current pair lc_atari_luma <= {lc_code[2], lc_code[3]}; - {R_pp[2], G_pp[2], B_pp[2]} <= lumacode_data_gtia[{lc_atari_hue, lc_atari_luma[3:2], lc_code[1]}]; + //{R_pp[2], G_pp[2], B_pp[2]} <= lumacode_data_gtia[{lc_atari_hue, lc_atari_luma[3:2], lc_code[1]}]; + {R_pp[2], G_pp[2], B_pp[2]} <= '0; end end // Lumacode Atari VCS @@ -365,7 +367,8 @@ always @(posedge PCLK_i) begin lc_atari_hue <= {lc_code[1], lc_code[2]}; end else begin // Display pixel after receiving remaining 2 lumacode samples (luma) - {R_pp[2], G_pp[2], B_pp[2]} <= lumacode_data_ctia[{lc_atari_hue, lc_code[1], lc_code[2][1]}]; + //{R_pp[2], G_pp[2], B_pp[2]} <= lumacode_data_ctia[{lc_atari_hue, lc_code[1], lc_code[2][1]}]; + {R_pp[2], G_pp[2], B_pp[2]} <= '0; end end end diff --git a/scripts/dump_flash_regs.tcl b/scripts/dump_flash_regs.tcl new file mode 100644 index 0000000..d588777 --- /dev/null +++ b/scripts/dump_flash_regs.tcl @@ -0,0 +1,58 @@ +# flash details +set flash_base 0x02000000 +set flash_imem_offset 0x00100000 +set flash_imem_base [format 0x%.8x [expr $flash_base + $flash_imem_offset]] +set flash_secsize 65536 + +# flash controller register addresses +set control_register 0x00020100 +set operating_protocols_setting 0x00020110 +set read_instr 0x00020114 +set write_instr 0x00020118 +set flash_cmd_setting 0x0002011c +set flash_cmd_ctrl 0x00020120 +set flash_cmd_addr_register 0x00020124 +set flash_cmd_write_data_0 0x00020128 +set flash_cmd_read_data_0 0x00020130 + +#Select the master service type and check for available service paths. +set service_paths [get_service_paths master] + +#Set the master service path. +set master_service_path [lindex $service_paths 0] + +#Open the master service. +set claim_path [claim_service master $master_service_path mylib] + +puts "Halting CPU" +master_write_32 $claim_path 0x40 0x00000001 +master_write_32 $claim_path 0x40 0x80000001 + +#read status reg +master_write_32 $claim_path $flash_cmd_setting 0x00001805 +master_write_32 $claim_path $flash_cmd_ctrl 0x1 +set st [master_read_8 $claim_path $flash_cmd_read_data_0 1] +puts "\nSTATUS: $st" + +#read flag reg +master_write_32 $claim_path $flash_cmd_setting 0x00001848 +master_write_32 $claim_path $flash_cmd_ctrl 0x1 +set flags [master_read_8 $claim_path $flash_cmd_read_data_0 1] +puts "FLAGS: $flags" + +#read vcr reg +master_write_32 $claim_path $flash_cmd_setting 0x00001861 +master_write_32 $claim_path $flash_cmd_ctrl 0x1 +set vcr [master_read_8 $claim_path $flash_cmd_read_data_0 1] +puts "VCR: $vcr" + +#read evcr reg +master_write_32 $claim_path $flash_cmd_setting 0x00001881 +master_write_32 $claim_path $flash_cmd_ctrl 0x1 +set evcr [master_read_8 $claim_path $flash_cmd_read_data_0 1] +puts "EVCR: $evcr" + +#clear flag register +master_write_32 $claim_path $flash_cmd_setting 0x00000050 +master_write_32 $claim_path $flash_cmd_ctrl 0x1 + diff --git a/scripts/qsys.patch b/scripts/qsys.patch deleted file mode 100644 index d5de326..0000000 --- a/scripts/qsys.patch +++ /dev/null @@ -1,35 +0,0 @@ ---- sys/synthesis/submodules/altera_asmi2_xip_controller.sv 2024-07-15 02:34:49.476724296 +0300 -+++ sys/synthesis/submodules/altera_asmi2_xip_controller.sv 2024-07-15 02:50:24.750038794 +0300 -@@ -611,7 +611,7 @@ - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (3), -- .USE_MEMORY_BLOCKS (1), -+ .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ---- sys/synthesis/submodules/sys_master_0.v 2024-07-15 02:34:47.396703537 +0300 -+++ sys/synthesis/submodules/sys_master_0.v 2024-07-15 02:50:14.617938092 +0300 -@@ -163,7 +163,7 @@ - .USE_PACKETS (0), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (3), -- .USE_MEMORY_BLOCKS (1), -+ .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) - ---- sys/synthesis/submodules/sys_onchip_memory2_0.v 2024-07-15 02:34:47.540704974 +0300 -+++ sys/synthesis/submodules/sys_onchip_memory2_0.v 2024-07-15 02:49:59.685789671 +0300 -@@ -71,7 +71,7 @@ - defparam the_altsyncram.byte_size = 8, - the_altsyncram.init_file = INIT_FILE, - the_altsyncram.lpm_type = "altsyncram", -- the_altsyncram.maximum_depth = 10496, -+ the_altsyncram.maximum_depth = 2048, - the_altsyncram.numwords_a = 10496, - the_altsyncram.operation_mode = "SINGLE_PORT", - the_altsyncram.outdata_reg_a = "UNREGISTERED", diff --git a/scripts/reprogram.sh b/scripts/reprogram.sh index ae062f4..187080c 100755 --- a/scripts/reprogram.sh +++ b/scripts/reprogram.sh @@ -1,6 +1,5 @@ #!/bin/sh -jtagconfig make rv-reprogram if [ $# -eq 1 ] && [ $1 = "jtag_uart" ] && [ $(pgrep -c nios2-terminal) = 0 ]; then diff --git a/scripts/rv-bt.tcl b/scripts/rv-bt.tcl new file mode 100644 index 0000000..7c49468 --- /dev/null +++ b/scripts/rv-bt.tcl @@ -0,0 +1,36 @@ +#Select the master service type and check for available service paths. +while 1 { + set service_paths [get_service_paths master] + if {[llength $service_paths] > 0} { + break + } + puts "Refreshing connections..." + refresh_connections + after 100 +} + +#Set the master service path. +set master_service_path [lindex $service_paths 0] + +#Open the master service. +set claim_path [claim_service master $master_service_path mylib] + +puts "Halting CPU" +master_write_32 $claim_path 0x40 0x00000001 +master_write_32 $claim_path 0x40 0x80000001 + +master_write_32 $claim_path 0x5c [expr 0x2207b1] +puts "DPC: [master_read_32 $claim_path 0x10 1]" +master_write_32 $claim_path 0x5c [expr 0x220341] +puts "MEPC: [master_read_32 $claim_path 0x10 1]" +master_write_32 $claim_path 0x5c [expr 0x220342] +puts "MCAUSE: [master_read_32 $claim_path 0x10 1]" + +set offset 0x1001 +foreach i {ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5} { + master_write_32 $claim_path 0x5c [expr 0x220000 + $offset] + puts "$i: [master_read_32 $claim_path 0x10 1]" + set offset [expr $offset + 1] +} + +master_write_32 $claim_path 0x40 0x40000000 diff --git a/scripts/rv-reboot.tcl b/scripts/rv-reboot.tcl new file mode 100644 index 0000000..28de9ac --- /dev/null +++ b/scripts/rv-reboot.tcl @@ -0,0 +1,31 @@ +#Select the master service type and check for available service paths. +while 1 { + set service_paths [get_service_paths master] + if {[llength $service_paths] > 0} { + break + } + puts "Refreshing connections..." + refresh_connections + after 100 +} + +#Set the master service path. +set master_service_path [lindex $service_paths 0] + +#Open the master service. +set claim_path [claim_service master $master_service_path mylib] + +puts "Halting CPU" +master_write_32 $claim_path 0x40 0x00000001 +master_write_32 $claim_path 0x40 0x80000001 + +close_service master $claim_path + + +set jtag_debug_list [get_service_paths jtag_debug] +set jd [ lindex $jtag_debug_list 0 ] +open_service jtag_debug $jd +puts "Resetting system" +jtag_debug_reset_system $jd +close_service jtag_debug $jd +puts "Done" diff --git a/scripts/rv-reprogram.tcl b/scripts/rv-reprogram.tcl index 7e1b80a..15ba4a0 100644 --- a/scripts/rv-reprogram.tcl +++ b/scripts/rv-reprogram.tcl @@ -1,3 +1,25 @@ +# flash details +set flash_base 0x02000000 +set flash_imem_offset 0x00080000 +set flash_imem_base [format 0x%.8x [expr $flash_base + $flash_imem_offset]] +set flash_secsize 65536 + +# flash controller register addresses +set control_register 0x00020100 +set operating_protocols_setting 0x00020110 +set read_instr 0x00020114 +set write_instr 0x00020118 +set flash_cmd_setting 0x0002011c +set flash_cmd_ctrl 0x00020120 +set flash_cmd_addr_register 0x00020124 +set flash_cmd_write_data_0 0x00020128 +set flash_cmd_read_data_0 0x00020130 + +# target file details +set bin_file mem_init/flash.bin +set bin_size [file size $bin_file] +set num_sectors [expr ($bin_size / $flash_secsize) + (($bin_size % $flash_secsize) ne 0)] + #Select the master service type and check for available service paths. while 1 { set service_paths [get_service_paths master] @@ -16,10 +38,46 @@ set master_service_path [lindex $service_paths 0] set claim_path [claim_service master $master_service_path mylib] puts "Halting CPU" -master_write_32 $claim_path 0x0 0x10000 +master_write_32 $claim_path 0x40 0x00000001 +master_write_32 $claim_path 0x40 0x80000001 -puts "Writing block RAM" -master_write_from_file $claim_path mem_init/sys_onchip_memory2_0.bin 0x10000 +#write enable +master_write_32 $claim_path $flash_cmd_setting 0x00000006 +master_write_32 $claim_path $flash_cmd_ctrl 0x1 + +#write status register (clear BP) +master_write_32 $claim_path $flash_cmd_setting 0x00001001 +#master_write_32 $claim_path $flash_cmd_write_data_0 0x0000005c +master_write_32 $claim_path $flash_cmd_write_data_0 0x00000000 +master_write_32 $claim_path $flash_cmd_ctrl 0x1 + +puts "Erasing $num_sectors flash sectors" +set addr $flash_imem_offset +for {set i 0} {$i<$num_sectors} {incr i} { + master_write_32 $claim_path $flash_cmd_setting 0x00000006 + master_write_32 $claim_path $flash_cmd_ctrl 0x1 + master_write_32 $claim_path $flash_cmd_setting 0x000003D8 + master_write_32 $claim_path $flash_cmd_addr_register $addr + master_write_32 $claim_path $flash_cmd_ctrl 0x1 + set addr [expr $addr + $flash_secsize] + after 500 +} + +puts "Writing flash" +# writes garbage and occasionally hangs (bug in generic serial flash IF?) +#master_write_from_file $claim_path mem_init/flash.bin $flash_imem_base + +# work around the issue by writing into small chunks so that FIFO does not fill up +set chunks [llength [glob mem_init/chunks/*]] +puts "Programming $chunks chunks" +set addr $flash_imem_base +for {set i 0} {$i<$chunks} {incr i} { + set file [format "flash.%04d" $i] + master_write_from_file $claim_path mem_init/chunks/$file $addr + set addr [expr $addr + 64] +} +#master_read_to_file $claim_path mem_init/flash_readback.bin $flash_imem_base $bin_size +#master_read_to_file $claim_path mem_init/ram_readback.bin 0x010000 65536 close_service master $claim_path diff --git a/software/ossc_sw.project b/software/ossc_sw.project index 087a3ca..18a971a 100644 --- a/software/ossc_sw.project +++ b/software/ossc_sw.project @@ -142,7 +142,7 @@ cd ../sys_controller_bsp && touch bsp_timestamp make clean - make ENABLE_AUDIO=y APP_CFLAGS_DEBUG_LEVEL="-DDEBUG" generate_hex + make ENABLE_AUDIO=y APP_CFLAGS_DEBUG_LEVEL="-DDEBUG" @@ -188,7 +188,7 @@ cd ../sys_controller_bsp && touch bsp_timestamp make clean - make ENABLE_AUDIO=y generate_hex + make ENABLE_AUDIO=y diff --git a/software/sys_controller/Makefile b/software/sys_controller/Makefile index 1a919fe..08ee02d 100644 --- a/software/sys_controller/Makefile +++ b/software/sys_controller/Makefile @@ -258,7 +258,7 @@ endif all: @$(ECHO) [$(APP_NAME) build complete] -all : build_pre_process libs app build_post_process +all : build_pre_process libs app mem_init_generate_new build_post_process #------------------------------------------------------------------------------ @@ -1139,16 +1139,28 @@ ossc/menu_sjis.c: ossc/menu.c ossc/userdata_sjis.c: ossc/userdata.c iconv -f UTF-8 -t SHIFT-JIS ossc/userdata.c > ossc/userdata_sjis.c -mem_init/sys_onchip_memory2_0.hex: sys_controller.elf - $(RV_OBJCOPY) --change-addresses -0x10000 -O binary --gap-fill 0 $< mem_init/sys_onchip_memory2_0.bin - ../../tools/bin2hex 4 mem_init/sys_onchip_memory2_0.bin mem_init/sys_onchip_memory2_0.hex +mem_init/flash.hex: sys_controller.elf + $(RV_OBJCOPY) --change-addresses -0x02A00000 -O binary --gap-fill 0 $< mem_init/flash.bin + $(RV_OBJCOPY) --change-addresses -0x02A00000 -O ihex --gap-fill 0 $< mem_init/flash.hex + mkdir -p mem_init/chunks + rm -f mem_init/chunks/* + split -d -b 64 -a 4 mem_init/flash.bin mem_init/chunks/flash. .PHONY: mem_init_generate_new -mem_init_generate_new: mem_init/sys_onchip_memory2_0.hex +mem_init_generate_new: mem_init/flash.hex -.PHONY: generate_hex -generate_hex: clean mem_init_generate_new +.PHONY: regenerate_hex +regenerate_hex: clean mem_init_generate_new .PHONY: rv-reprogram rv-reprogram: mem_init_generate_new + jtagconfig system-console -cli --script ../../scripts/rv-reprogram.tcl + +rv-bt: + jtagconfig + system-console -cli --script ../../scripts/rv-bt.tcl + +rv-reboot: + jtagconfig + system-console -cli --script ../../scripts/rv-reboot.tcl diff --git a/software/sys_controller/crt0.boot.S b/software/sys_controller/crt0.boot.S index 863deb9..e4f1606 100644 --- a/software/sys_controller/crt0.boot.S +++ b/software/sys_controller/crt0.boot.S @@ -71,6 +71,14 @@ zero_loop: ble x26, x27, zero_loop zero_loop_end: +copy_sections: + jal alt_load + +cache_setup: + fence.i + csrwi 0x7C0, 1 +cache_setup_end: + main_entry: /* jump to alt_main program entry point */ diff --git a/software/sys_controller/crt0.boot_E.S b/software/sys_controller/crt0.boot_E.S index eaf071d..5968eb0 100644 --- a/software/sys_controller/crt0.boot_E.S +++ b/software/sys_controller/crt0.boot_E.S @@ -55,6 +55,15 @@ zero_loop: ble x14, x15, zero_loop zero_loop_end: +copy_sections: + jal alt_load +copy_sections_end: + +cache_setup: + fence.i + csrwi 0x7C0, 1 +cache_setup_end: + main_entry: /* jump to alt_main program entry point */ diff --git a/software/sys_controller/link.common.ld b/software/sys_controller/link.common.ld index 48a00f3..8ec949d 100644 --- a/software/sys_controller/link.common.ld +++ b/software/sys_controller/link.common.ld @@ -1,13 +1,19 @@ SEARCH_DIR(.) __DYNAMIC = 0; +/* First 16 flash sectors reserved for firmware image (1MB). + In typical configuration a firmware image consists of + * compressed bitstream (8 sectors / 0.5MB) + * flash_imem (8 sectors / 0.5MB) + Last 16 flash sectors reserved for userdata (16x 64KB). */ MEMORY { - dataram : ORIGIN = 0x00010000, LENGTH = 0xa400 + flash_imem : ORIGIN = 0x02080000, LENGTH = 524288 + dataram : ORIGIN = 0x00010000, LENGTH = 16384 } /* Stack information variables */ -_min_stack = 0x4B0; /* 1200 - minimum stack space to reserve */ +_min_stack = 0x1000; /* 4KB - minimum stack space to reserve */ _stack_start = ORIGIN(dataram) + LENGTH(dataram); /* We have to align each sector to word boundaries as our current s19->slm @@ -19,7 +25,7 @@ SECTIONS { . = ALIGN(4); KEEP(*(.vectors)) - } > dataram + } > flash_imem .text : { . = ALIGN(4); @@ -40,7 +46,15 @@ SECTIONS *(.lit) *(.shdata) _endtext = .; - } > dataram + } > flash_imem + + .rodata : { + . = ALIGN(4); + *(.rodata); + *(.rodata.*) + *(.srodata); + *(.srodata.*) + } > flash_imem /*--------------------------------------------------------------------*/ /* Global constructor/destructor segement */ @@ -69,19 +83,18 @@ SECTIONS PROVIDE_HIDDEN (__fini_array_end = .); } > dataram - .rodata : { + .text_bram : AT ( LOADADDR (.rodata) + SIZEOF (.rodata) ) { + PROVIDE (__ram_text_start = ABSOLUTE(.)); . = ALIGN(4); - *(.rodata); - *(.rodata.*) + *(.text_bram); + LONG(0) + PROVIDE (__ram_text_end = ABSOLUTE(.)); } > dataram - .shbss : - { - . = ALIGN(4); - *(.shbss) - } > dataram + PROVIDE (__flash_text_bram_start = LOADADDR(.text_bram)); - .data : { + .data : AT ( LOADADDR (.text_bram) + SIZEOF (.text_bram) ) { + PROVIDE (__ram_rwdata_start = ABSOLUTE(.)); . = ALIGN(4); sdata = .; _sdata = .; @@ -93,6 +106,15 @@ SECTIONS *(.sdata2.*) edata = .; _edata = .; + PROVIDE (__ram_rwdata_end = ABSOLUTE(.)); + } > dataram + + PROVIDE (__flash_rwdata_start = LOADADDR(.data)); + + .shbss : + { + . = ALIGN(4); + *(.shbss) } > dataram .bss : diff --git a/software/sys_controller/memory/flash.c b/software/sys_controller/memory/flash.c index b3a3847..92b2abb 100644 --- a/software/sys_controller/memory/flash.c +++ b/software/sys_controller/memory/flash.c @@ -18,52 +18,46 @@ // #include -#include -#include "system.h" #include "flash.h" -#include "utils.h" -// save some code space -#define SINGLE_FLASH_INSTANCE +void __attribute__((noinline, flatten, __section__(".text_bram"))) flash_write_protect(flash_ctrl_dev *dev, int enable) { + // Write enable + dev->regs->flash_cmd_cfg = 0x00000006; + dev->regs->flash_cmd_ctrl = 1; -alt_flash_dev *epcq_dev; + // Write status register + dev->regs->flash_cmd_cfg = 0x00001001; + dev->regs->flash_cmd_wrdata[0] = enable ? 0x0000005c : 0x00000000; + dev->regs->flash_cmd_ctrl = 1; - -int init_flash() -{ -#ifdef SINGLE_FLASH_INSTANCE - extern alt_llist alt_flash_dev_list; - epcq_dev = (alt_flash_dev*)alt_flash_dev_list.next; -#else - epcq_dev = alt_flash_open_dev(EPCQ_CONTROLLER2_0_AVL_MEM_NAME); -#endif - - if (epcq_dev == NULL) - return -1; - - return 0; -} - -int verify_flash(alt_u32 offset, alt_u32 length, alt_u32 golden_crc, alt_u8 *tmpbuf) -{ - alt_u32 crcval=0, i, j, bytes_to_read; - int retval; - - for (i=0; iregs->flash_cmd_cfg = 0x00001805; + dev->regs->flash_cmd_ctrl = 1; + if (!(dev->regs->flash_cmd_rddata[0] & (1<<0))) + break; } - if (crcval != golden_crc) - return -FLASH_VERIFY_ERROR; - - return 0; + // Write disable + dev->regs->flash_cmd_cfg = 0x00000004; + dev->regs->flash_cmd_ctrl = 1; +} + +void __attribute__((noinline, flatten, __section__(".text_bram"))) flash_sector_erase(flash_ctrl_dev *dev, uint32_t addr) { + // Write enable + dev->regs->flash_cmd_cfg = 0x00000006; + dev->regs->flash_cmd_ctrl = 1; + + // Sector erase + dev->regs->flash_cmd_cfg = (dev->flash_size > 0x1000000) ? 0x000004DC : 0x000003D8; + dev->regs->flash_cmd_addr = addr; + dev->regs->flash_cmd_ctrl = 1; + + // Poll status register until write has completed + while (1) { + dev->regs->flash_cmd_cfg = 0x00001805; + dev->regs->flash_cmd_ctrl = 1; + if (!(dev->regs->flash_cmd_rddata[0] & (1<<0))) + break; + } } diff --git a/software/sys_controller/memory/flash.h b/software/sys_controller/memory/flash.h index 8604568..5147f17 100644 --- a/software/sys_controller/memory/flash.h +++ b/software/sys_controller/memory/flash.h @@ -20,22 +20,32 @@ #ifndef FLASH_H_ #define FLASH_H_ -#include "alt_types.h" +#include #include "sysconfig.h" -#include "altera_epcq_controller2.h" -// EPCS16 pagesize is 256 bytes -// Flash is split 50-50 to FW and userdata, 1MB each -#define PAGESIZE 256 -#define PAGES_PER_SECTOR 256 //EPCS "sector" corresponds to "block" on Spansion flash -#define SECTORSIZE (PAGESIZE*PAGES_PER_SECTOR) -#define USERDATA_OFFSET 0x100000 -#define MAX_USERDATA_ENTRY 15 // 16 sectors for userdata +#define FLASH_SECTOR_SIZE 65536 -#define FLASH_VERIFY_ERROR 204 +typedef struct { + uint32_t ctrl; + uint32_t baud_rate; + uint32_t cs_delay; + uint32_t read_capture; + uint32_t oper_mode; + uint32_t read_instr; + uint32_t write_instr; + uint32_t flash_cmd_cfg; + uint32_t flash_cmd_ctrl; + uint32_t flash_cmd_addr; + uint32_t flash_cmd_wrdata[2]; + uint32_t flash_cmd_rddata[2]; +} gen_flash_if_regs; +typedef struct { + volatile gen_flash_if_regs *regs; + uint32_t flash_size; +} flash_ctrl_dev; -int init_flash(); -int verify_flash(alt_u32 offset, alt_u32 length, alt_u32 golden_crc, alt_u8 *tmpbuf); +void flash_write_protect(flash_ctrl_dev *dev, int enable); +void flash_sector_erase(flash_ctrl_dev *dev, uint32_t addr); #endif /* FLASH_H_ */ diff --git a/software/sys_controller/memory/sdcard.c b/software/sys_controller/memory/sdcard.c index 52d1c3c..2caf973 100644 --- a/software/sys_controller/memory/sdcard.c +++ b/software/sys_controller/memory/sdcard.c @@ -23,7 +23,7 @@ #include "flash.h" #include "utils.h" -extern alt_flash_dev *epcq_dev; +//extern alt_flash_dev *epcq_dev; SD_DEV sdcard_dev; @@ -45,7 +45,7 @@ int copy_sd_to_flash(alt_u32 sd_blknum, alt_u32 flash_pagenum, alt_u32 length, a int retval, i; alt_u32 bytes_to_rw; - while (length > 0) { + /*while (length > 0) { bytes_to_rw = (length < SD_BLK_SIZE) ? length : SD_BLK_SIZE; res = SD_Read(&sdcard_dev, tmpbuf, sd_blknum, 0, bytes_to_rw); if (res != SD_OK) { @@ -68,7 +68,7 @@ int copy_sd_to_flash(alt_u32 sd_blknum, alt_u32 flash_pagenum, alt_u32 length, a ++sd_blknum; flash_pagenum += bytes_to_rw/PAGESIZE; length -= bytes_to_rw; - } + }*/ return 0; } @@ -79,7 +79,7 @@ int copy_flash_to_sd(alt_u32 flash_pagenum, alt_u32 sd_blknum, alt_u32 length, a int retval, i; alt_u32 bytes_to_rw; - while (length > 0) { + /*while (length > 0) { bytes_to_rw = (length < SD_BLK_SIZE) ? length : SD_BLK_SIZE; retval = alt_epcq_controller2_read(epcq_dev, flash_pagenum*PAGESIZE, tmpbuf, bytes_to_rw); for (i=0; itype) { case OPT_AVCONFIG_SELECTION: @@ -335,7 +335,7 @@ void write_option_value(menuitem_t *item, int func_called, int retval) void render_osd_page() { int i; - menuitem_t *item; + const menuitem_t *item; uint32_t row_mask[2] = {0, 0}; if (!menu_active || (osd_enable != 1)) @@ -360,7 +360,7 @@ void render_osd_page() { void display_menu(alt_u8 forcedisp) { menucode_id code = NO_ACTION; - menuitem_t *item; + const menuitem_t *item; alt_u8 *val, val_wrap, val_min, val_max; alt_u16 *val_u16, val_u16_min, val_u16_max; int i, func_called = 0, retval = 0; diff --git a/software/sys_controller/ossc/menu.h b/software/sys_controller/ossc/menu.h index 5ff77ff..1cc49db 100644 --- a/software/sys_controller/ossc/menu.h +++ b/software/sys_controller/ossc/menu.h @@ -55,7 +55,7 @@ typedef struct { alt_u8 wrap_cfg; alt_u8 min; alt_u8 max; - const char **setting_str; + const char *const *const setting_str; } opt_avconfig_selection; typedef struct { @@ -100,11 +100,11 @@ typedef struct { struct menustruct { alt_u8 num_items; - menuitem_t *items; + const menuitem_t *items; }; #define SETTING_ITEM(x) 0, sizeof(x)/sizeof(char*)-1, x -#define MENU(X, Y) menuitem_t X##_items[] = Y; const menu_t X = { sizeof(X##_items)/sizeof(menuitem_t), X##_items }; +#define MENU(X, Y) const menuitem_t X##_items[] = Y; const menu_t X = { sizeof(X##_items)/sizeof(menuitem_t), X##_items }; #define P99_PROTECT(...) __VA_ARGS__ typedef enum { diff --git a/software/sys_controller/ossc/userdata.c b/software/sys_controller/ossc/userdata.c index be424fb..5a6064d 100644 --- a/software/sys_controller/ossc/userdata.c +++ b/software/sys_controller/ossc/userdata.c @@ -50,7 +50,6 @@ extern alt_u8 lcd_bl_timeout; extern alt_u8 auto_input, auto_av1_ypbpr, auto_av2_ypbpr, auto_av3_ypbpr; extern alt_u8 osd_enable, osd_status_timeout, phase_hotkey_enable; extern SD_DEV sdcard_dev; -extern alt_flash_dev *epcq_dev; extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1]; char target_profile_name[PROFILE_NAME_LEN+1]; @@ -92,9 +91,9 @@ int write_userdata(alt_u8 entry) memcpy(((ude_initcfg*)databuf)->keys, rc_keymap, sizeof(rc_keymap)); for (i=0; i PAGESIZE) ? PAGESIZE : vm_to_write); for (i=0; i PAGESIZE) ? PAGESIZE : vm_to_write); + /*retval = alt_epcq_controller2_write_block(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), (USERDATA_OFFSET+entry*SECTORSIZE+pageno*PAGESIZE), databuf, (vm_to_write > PAGESIZE) ? PAGESIZE : vm_to_write); if (retval != 0) - return retval; + return retval;*/ srcoffset += PAGESIZE; vm_to_write = (vm_to_write < PAGESIZE) ? 0 : (vm_to_write - PAGESIZE); @@ -165,7 +164,7 @@ int read_userdata(alt_u8 entry, int dry_run) return -1; } - retval = alt_epcq_controller2_read(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, PAGESIZE); + //retval = alt_epcq_controller2_read(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, PAGESIZE); for (i=0; i= 7 cyc + loops = ((ALT_CPU_FREQ/1000000)*us)/120; + + for (i=7; i= 7 cyc @@ -64,6 +85,7 @@ unsigned int alt_busy_sleep (unsigned int us) for (i=7; i - -/* - * EPCQ_RD_STATUS register offset - * - * The EPCQ_RD_STATUS register contains information from the read status - * register operation. A full description of the register can be found in the - * data sheet, - * - */ -#define ALTERA_EPCQ_CONTROLLER2_STATUS_REG (0x0) - -/* - * EPCQ_RD_STATUS register access macros - */ -#define IOADDR_ALTERA_EPCQ_CONTROLLER2_STATUS(base) \ - __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_STATUS_REG) - -#define IORD_ALTERA_EPCQ_CONTROLLER2_STATUS(base) \ - IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_STATUS_REG) - -#define IOWR_ALTERA_EPCQ_CONTROLLER2_STATUS(base, data) \ - IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_STATUS_REG, data) - -/* - * EPCQ_RD_STATUS register description macros - */ - -/** Write in progress bit */ -#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_MASK (0x00000001) -#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_AVAILABLE (0x00000000) -#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_BUSY (0x00000001) -/** When to time out a poll of the write in progress bit */ -/* 0.7 sec time out */ -#define ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE 700000 - -/* - * EPCQ_RD_SID register offset - * - * The EPCQ_RD_SID register contains the information from the read silicon ID - * operation and can be used to determine what type of EPCS device we have. - * Only support in EPCS16 and EPCS64. - * - * This register is valid only if the device is an EPCS. - * - */ -#define ALTERA_EPCQ_CONTROLLER2_SID_REG (0x4) - -/* - * EPCQ_RD_SID register access macros - */ -#define IOADDR_ALTERA_EPCQ_CONTROLLER2_SID(base) \ - __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_SID_REG) - -#define IORD_ALTERA_EPCQ_CONTROLLER2_SID(base) \ - IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_SID_REG) - -#define IOWR_ALTERA_EPCQ_CONTROLLER2_SID(base, data) \ - IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_SID_REG, data) - -/* - * EPCQ_RD_SID register description macros - * - * Specific device values obtained from Table 14 of: - * "Serial Configuration (EPCS) Devices Datasheet" - */ -#define ALTERA_EPCQ_CONTROLLER2_SID_MASK (0x000000FF) -#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS16 (0x00000014) -#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS64 (0x00000016) -#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS128 (0x00000018) - -/* - * EPCQ_RD_RDID register offset - * - * The EPCQ_RD_RDID register contains the information from the read memory - * capacity operation and can be used to determine what type of EPCQ device - * we have. - * - * This register is only valid if the device is an EPCQ. - * - */ -#define ALTERA_EPCQ_CONTROLLER2_RDID_REG (0x8) - -/* - * EPCQ_RD_RDID register access macros - */ -#define IOADDR_ALTERA_EPCQ_CONTROLLER2_RDID(base) \ - __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_RDID_REG) - -#define IORD_ALTERA_EPCQ_CONTROLLER2_RDID(base) \ - IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_RDID_REG) - -#define IOWR_ALTERA_EPCQ_CONTROLLER2_RDID(base, data) \ - IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_RDID_REG, data) - -/* - * EPCQ_RD_RDID register description macros - * - * Specific device values obtained from Table 28 of: - * "Quad-Serial Configuration (EPCQ (www.altera.com/literature/hb/cfg/cfg_cf52012.pdf)) - * Devices Datasheet" - */ -#define ALTERA_EPCQ_CONTROLLER2_RDID_MASK (0x000000FF) -#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ16 (0x00000015) -#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ32 (0x00000016) -#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ64 (0x00000017) -#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ128 (0x00000018) -#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ256 (0x00000019) -#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ512 (0x00000020) -#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ1024 (0x00000021) - -/* - * EPCQ_MEM_OP register offset - * - * The EPCQ_MEM_OP register is used to do memory protect and erase operations - * - */ -#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG (0xC) - -/* - * EPCQ_MEM_OP register access macros - */ -#define IOADDR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(base) \ - __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG) - -#define IORD_ALTERA_EPCQ_CONTROLLER2_MEM_OP(base) \ - IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG) - -#define IOWR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(base, data) \ - IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG, data) - -/* - * EPCQ_MEM_OP register description macros - */ -#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_CMD_MASK (0x00000003) -#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_BULK_ERASE_CMD (0x00000001) -#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_ERASE_CMD (0x00000002) -#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_PROTECT_CMD (0x00000003) -#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_WRITE_ENABLE_CMD (0x00000004) - -/** see datasheet for sector values */ -#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_VALUE_MASK (0x00FFFF00) - -/* - * EPCQ_ISR register offset - * - * The EPCQ_ISR register is used to determine whether an invalid write or erase - * operation triggered an interrupt - * - */ -#define ALTERA_EPCQ_CONTROLLER2_ISR_REG (0x10) - -/* - * EPCQ_ISR register access macros - */ -#define IOADDR_ALTERA_EPCQ_CONTROLLER2_ISR(base) \ - __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_ISR_REG) - -#define IORD_ALTERA_EPCQ_CONTROLLER2_ISR(base) \ - IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_ISR_REG) - -#define IOWR_ALTERA_EPCQ_CONTROLLER2_ISR(base, data) \ - IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_ISR_REG, data) - -/* - * EPCQ_ISR register description macros - */ -#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_MASK (0x00000001) -#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_ACTIVE (0x00000001) - -#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_MASK (0x00000002) -#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_ACTIVE (0x00000002) - - -/* - * EPCQ_IMR register offset - * - * The EPCQ_IMR register is used to mask the invalid erase or the invalid write - * interrupts. - * - */ -#define ALTERA_EPCQ_CONTROLLER2_IMR_REG (0x14) - -/* - * EPCQ_IMR register access macros - */ -#define IOADDR_ALTERA_EPCQ_CONTROLLER2_IMR(base) \ - __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_IMR_REG) - -#define IORD_ALTERA_EPCQ_CONTROLLER2_IMR(base) \ - IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_IMR_REG) - -#define IOWR_ALTERA_EPCQ_CONTROLLER2_IMR(base, data) \ - IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_IMR_REG, data) - -/* - * EPCQ_IMR register description macros - */ -#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_ERASE_MASK (0x00000001) -#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_ERASE_ENABLED (0x00000001) - -#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_WRITE_MASK (0x00000002) -#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_WRITE_ENABLED (0x00000002) - -/* - * EPCQ_CHIP_SELECT register offset - * - * The EPCQ_CHIP_SELECT register is used to issue chip select - */ -#define ALTERA_EPCQ_CHIP_SELECT_REG (0x18) - -/* - * EPCQ_CHIP_SELECT register access macros - */ -#define IOADDR_ALTERA_EPCQ_CHIP_SELECT(base) \ - __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CHIP_SELECT_REG) - -#define IOWR_ALTERA_EPCQ_CHIP_SELECT(base, data) \ - IOWR_32DIRECT(base, ALTERA_EPCQ_CHIP_SELECT_REG, data) - -/* - * EPCQ_CHIP_SELECT register description macros - */ -#define ALTERA_EPCQ_CHIP1_SELECT (0x00000001) -#define ALTERA_EPCQ_CHIP2_SELECT (0x00000002) -#define ALTERA_EPCQ_CHIP3_SELECT (0x00000003) - -#endif /* __ALTERA_EPCQ_CONTROLLER2_REGS_H__ */ diff --git a/software/sys_controller_bsp/drivers/src/altera_avalon_timer_ts.c b/software/sys_controller_bsp/drivers/src/altera_avalon_timer_ts.c index 53988f6..4b9a84d 100644 --- a/software/sys_controller_bsp/drivers/src/altera_avalon_timer_ts.c +++ b/software/sys_controller_bsp/drivers/src/altera_avalon_timer_ts.c @@ -97,7 +97,7 @@ int alt_timestamp_start(void) * was reset. */ -alt_timestamp_type alt_timestamp(void) +alt_timestamp_type __attribute__((noinline, flatten, __section__(".text_bram"))) alt_timestamp(void) { void* base = altera_avalon_timer_ts_base; diff --git a/software/sys_controller_bsp/drivers/src/altera_epcq_controller2.c b/software/sys_controller_bsp/drivers/src/altera_epcq_controller2.c deleted file mode 100644 index 142c7e0..0000000 --- a/software/sys_controller_bsp/drivers/src/altera_epcq_controller2.c +++ /dev/null @@ -1,810 +0,0 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include -#include -#include -#include -#include "sys/param.h" -#include "alt_types.h" -#include "altera_epcq_controller2_regs.h" -#include "altera_epcq_controller2.h" -#include "priv/alt_busy_sleep.h" -#include "sys/alt_debug.h" -#include "sys/alt_cache.h" - - -ALT_INLINE alt_32 static alt_epcq_validate_read_write_arguments(alt_epcq_controller2_dev *flash_info,alt_u32 offset, alt_u32 length); -alt_32 static alt_epcq_poll_for_write_in_progress(alt_epcq_controller2_dev* epcq_flash_info); - -/* - * Public API - * - * Refer to “Using Flash Devices” in the - * Developing Programs Using the Hardware Abstraction Layer chapter - * of the Nios II Software Developer’s Handbook. - */ - - - /** - * alt_epcq_controller2_lock - * - * Locks the range of the memory sectors, which - * protected from write and erase. - * - * Arguments: - * - *flash_info: Pointer to general flash device structure. - * - sectors_to_lock: Block protection bits in EPCQ ==> Bit4 | Bit3 | Bit2 | Bit1 | Bit0 - * TB | BP3 | BP2 | BP1 | BP0 - * For details of setting sectors protection, please refer to EPCQ datasheet. - * - * Returns: - * 0 -> success - * -EINVAL -> Invalid arguments - * -ETIME -> Time out and skipping the looping after 0.7 sec. - * -ENOLCK -> Sectors lock failed. -**/ -int alt_epcq_controller2_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock) -{ - alt_u32 mem_op_value = 0; /* value to write to EPCQ_MEM_OP register */ - alt_epcq_controller2_dev* epcq_flash_info = NULL; - alt_u32 result = 0; - alt_32 status = 0; - - /* return -EINVAL if flash_info is NULL */ - if(NULL == flash_info || 0 > sectors_to_lock) - { - return -EINVAL; - } - - epcq_flash_info = (alt_epcq_controller2_dev*)flash_info; - - /* sector value should occupy bits 17:8 */ - mem_op_value = sectors_to_lock << 8; - - /* sector protect commands 0b11 occupies lower 2 bits */ - mem_op_value |= ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_PROTECT_CMD; - - /* write sector protect command to EPCQ_MEM_OP register to protect sectors */ - IOWR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(epcq_flash_info->csr_base, mem_op_value); - - /* poll write in progress to make sure no operation is in progress */ - status = alt_epcq_poll_for_write_in_progress(epcq_flash_info); - if(status != 0) - { - return status; - } - - status = IORD_ALTERA_EPCQ_CONTROLLER2_STATUS(epcq_flash_info->csr_base); - result |= (status >> 2) & 0x07; /* extract out BP3 - BP0 */ - result |= (status >> 3) & 0x08; /* extract out BP4 */ - result |= (status >> 1) & 0x10; /* extract out TOP/BOTTOM bit */ - - if(result != sectors_to_lock) - { - /*return -ENOLCK;*/ - } - - return 0; -} - -/** - * alt_epcq_controller2_get_info - * - * Pass the table of erase blocks to the user. This flash will return a single - * flash_region that gives the number and size of sectors for the device used. - * - * Arguments: - * - *fd: Pointer to general flash device structure. - * - **info: Pointer to flash region - * - *number_of_regions: Pointer to number of regions - * - * For details of setting sectors protection, please refer to EPCQ datasheet. - * - * Returns: - * 0 -> success - * -EINVAL -> Invalid arguments - * -EIO -> Could be hardware problem. -**/ -int alt_epcq_controller2_get_info -( - alt_flash_fd *fd, /** flash device descriptor */ - flash_region **info, /** pointer to flash_region will be stored here */ - int *number_of_regions /** number of regions will be stored here */ -) -{ - alt_flash_dev* flash = NULL; - - /* return -EINVAL if fd,info and number_of_regions are NULL */ - if(NULL == fd || NULL == info || NULL == number_of_regions) - { - return -EINVAL; - } - - flash = (alt_flash_dev*)fd; - - *number_of_regions = flash->number_of_regions; - - if (!flash->number_of_regions) - { - return -EIO; - } - else - { - *info = &flash->region_info[0]; - } - - return 0; -} - -/** - * alt_epcq_controller2_erase_block - * - * This function erases a single flash sector. - * - * Arguments: - * - *flash_info: Pointer to EPCQ flash device structure. - * - block_offset: byte-addressed offset, from start of flash, of the sector to be erased - * - * Returns: - * 0 -> success - * -EINVAL -> Invalid arguments - * -EIO -> write failed, sector might be protected -**/ -int alt_epcq_controller2_erase_block(alt_flash_dev *flash_info, int block_offset) -{ - alt_32 ret_code = 0; - alt_u32 mem_op_value = 0; /* value to write to EPCQ_MEM_OP register */ - alt_epcq_controller2_dev* epcq_flash_info = NULL; - alt_u32 sector_number = 0; - - /* return -EINVAL if flash_info is NULL */ - if(NULL == flash_info) - { - return -EINVAL; - } - - epcq_flash_info = (alt_epcq_controller2_dev*)flash_info; - - /* - * Sanity checks that block_offset is within the flash memory span and that the - * block offset is sector aligned. - * - */ - if((block_offset < 0) - || (block_offset >= epcq_flash_info->size_in_bytes) - || (block_offset & (epcq_flash_info->sector_size - 1)) != 0) - { - return -EINVAL; - } - - /* calculate current sector/block number */ - sector_number = (block_offset/(epcq_flash_info->sector_size)); - - /* sector value should occupy bits 23:8 */ - mem_op_value = (sector_number << 8) & ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_VALUE_MASK; - - /* write enable command */ - mem_op_value |= ALTERA_EPCQ_CONTROLLER2_MEM_OP_WRITE_ENABLE_CMD; - - /* write sector erase command to EPCQ_MEM_OP register to erase sector "sector_number" */ - IOWR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(epcq_flash_info->csr_base, mem_op_value); - - /* sector value should occupy bits 23:8 */ - mem_op_value = (sector_number << 8) & ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_VALUE_MASK; - - /* sector erase commands 0b10 occupies lower 2 bits */ - mem_op_value |= ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_ERASE_CMD; - - /* write sector erase command to EPCQ_MEM_OP register to erase sector "sector_number" */ - IOWR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(epcq_flash_info->csr_base, mem_op_value); - - /* check whether erase triggered a illegal erase interrupt */ - if((IORD_ALTERA_EPCQ_CONTROLLER2_ISR(epcq_flash_info->csr_base) & - ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_MASK) == - ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_ACTIVE) - { - /* clear register */ - /* EPCQ_ISR access is write one to clear (W1C) */ - IOWR_ALTERA_EPCQ_CONTROLLER2_ISR(epcq_flash_info->csr_base, - ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_MASK ); - return -EIO; /* erase failed, sector might be protected */ - } - - return ret_code; -} - -/** - * alt_epcq_controller2_write_block - * - * This function writes one block/sector of data to flash. The length of the write can NOT - * spill into the adjacent sector. - * - * It assumes that someone has already erased the appropriate sector(s). - * - * Arguments: - * - *flash_info: Pointer to EPCQ flash device structure. - * - block_offset: byte-addressed offset, from the start of flash, of the sector to written to - * - data-offset: Byte offset (unaligned access) of write into flash memory. - * For best performance, word(32 bits - aligned access) offset of write is recommended. - * - *src_addr: source buffer - * - length: size of writing - * - * Returns: - * 0 -> success - * -EINVAL -> Invalid arguments - * -EIO -> write failed, sector might be protected -**/ -int alt_epcq_controller2_write_block -( - alt_flash_dev *flash_info, /** flash device info */ - int block_offset, /** sector/block offset in byte addressing */ - int data_offset, /** offset of write from base address */ - const void *data, /** data to be written */ - int length /** bytes of data to be written, >0 */ -) -{ - alt_u32 buffer_offset = 0; /** offset into data buffer to get write data */ - alt_u32 remaining_length = length; /** length left to write */ - alt_u32 write_offset = data_offset; /** offset into flash to write too */ - - alt_epcq_controller2_dev *epcq_flash_info = (alt_epcq_controller2_dev*)flash_info; - - /* - * Sanity checks that data offset is not larger then a sector, that block offset is - * sector aligned and within the valid flash memory range and a write doesn't spill into - * the adjacent flash sector. - */ - if(block_offset < 0 - || data_offset < 0 - || NULL == flash_info - || NULL == data - || data_offset >= epcq_flash_info->size_in_bytes - || block_offset >= epcq_flash_info->size_in_bytes - || length > (epcq_flash_info->sector_size - (data_offset - block_offset)) - || length < 0 - || (block_offset & (epcq_flash_info->sector_size - 1)) != 0) - { - return -EINVAL; - } - - /* - * Do writes one 32-bit word at a time. - * We need to make sure that we pad the first few bytes so they're word aligned if they are - * not already. - */ - while (remaining_length > 0) - { - alt_u32 word_to_write = 0xFFFFFFFF; /** initialize word to write to blank word */ - alt_u32 padding = 0; /** bytes to pad the next word that is written */ - alt_u32 bytes_to_copy = sizeof(alt_u32); /** number of bytes from source to copy */ - - /* - * we need to make sure the write is word aligned - * this should only be true at most 1 time - */ - if (0 != (write_offset & (sizeof(alt_u32) - 1))) - { - /* - * data is not word aligned - * calculate padding bytes need to add before start of a data offset - */ - padding = write_offset & (sizeof(alt_u32) - 1); - - /* update variables to account for padding being added */ - bytes_to_copy -= padding; - - if(bytes_to_copy > remaining_length) - { - bytes_to_copy = remaining_length; - } - - write_offset = write_offset - padding; - if(0 != (write_offset & (sizeof(alt_u32) - 1))) - { - return -EINVAL; - } - } - else - { - if(bytes_to_copy > remaining_length) - { - bytes_to_copy = remaining_length; - } - } - - /* prepare the word to be written */ - memcpy((((void*)&word_to_write)) + padding, ((void*)data) + buffer_offset, bytes_to_copy); - - /* update offset and length variables */ - buffer_offset += bytes_to_copy; - remaining_length -= bytes_to_copy; - - /* write to flash 32 bits at a time */ - IOWR_32DIRECT(epcq_flash_info->data_base, write_offset, word_to_write); - if (IORD_32DIRECT(epcq_flash_info->data_base, write_offset) != word_to_write) - { - IOWR_32DIRECT(epcq_flash_info->data_base, write_offset, word_to_write); - } - - /* check whether write triggered a illegal write interrupt */ - if((IORD_ALTERA_EPCQ_CONTROLLER2_ISR(epcq_flash_info->csr_base) & - ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_MASK) == - ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_ACTIVE) - { - /* clear register */ - IOWR_ALTERA_EPCQ_CONTROLLER2_ISR(epcq_flash_info->csr_base, - ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_MASK ); - return -EIO; /** write failed, sector might be protected */ - } - - /* update current offset */ - write_offset = write_offset + sizeof(alt_u32); - } - - return 0; -} - -/** - * alt_epcq_controller2_write - * - * Program the data into the flash at the selected address. - * - * The different between this function and alt_epcq_controller2_write_block function - * is that this function (alt_epcq_controller2_write) will automatically erase a block as needed - * Arguments: - * - *flash_info: Pointer to EPCQ flash device structure. - * - offset: Byte offset (unaligned access) of write to flash memory. For best performance, - * word(32 bits - aligned access) offset of write is recommended. - * - *src_addr: source buffer - * - length: size of writing - * - * Returns: - * 0 -> success - * -EINVAL -> Invalid arguments - * -EIO -> write failed, sector might be protected - * -**/ -int alt_epcq_controller2_write( - alt_flash_dev *flash_info, /** device info */ - int offset, /** offset of write from base address */ - const void *src_addr, /** source buffer */ - int length /** size of writing */ -) -{ - alt_32 ret_code = 0; - - alt_epcq_controller2_dev *epcq_flash_info = NULL; - - alt_u32 write_offset = offset; /** address of next byte to write */ - alt_u32 remaining_length = length; /** length of write data left to be written */ - alt_u32 buffer_offset = 0; /** offset into source buffer to get write data */ - alt_u32 i = 0; - - /* return -EINVAL if flash_info and src_addr are NULL */ - if(NULL == flash_info || NULL == src_addr) - { - return -EINVAL; - } - - epcq_flash_info = (alt_epcq_controller2_dev*)flash_info; - - /* make sure the write parameters are within the bounds of the flash */ - ret_code = alt_epcq_validate_read_write_arguments(epcq_flash_info, offset, length); - - if(0 != ret_code) - { - return ret_code; - } - - /* - * This loop erases and writes data one sector at a time. We check for write completion - * before starting the next sector. - */ - for(i = offset/epcq_flash_info->sector_size ; i < epcq_flash_info->number_of_sectors; i++) - { - alt_u32 block_offset = 0; /** block offset in byte addressing */ - alt_u32 offset_within_current_sector = 0; /** offset into current sector to write */ - alt_u32 length_to_write = 0; /** length to write to current sector */ - - if(0 >= remaining_length) - { - break; /* out of data to write */ - } - - /* calculate current sector/block offset in byte addressing */ - block_offset = write_offset & ~(epcq_flash_info->sector_size - 1); - - /* calculate offset into sector/block if there is one */ - if(block_offset != write_offset) - { - offset_within_current_sector = write_offset - block_offset; - } - - /* erase sector */ - ret_code = alt_epcq_controller2_erase_block(flash_info, block_offset); - - if(0 != ret_code) - { - return ret_code; - } - - /* calculate the byte size of data to be written in a sector */ - length_to_write = MIN(epcq_flash_info->sector_size - offset_within_current_sector, - remaining_length); - - /* write data to erased block */ - ret_code = alt_epcq_controller2_write_block(flash_info, block_offset, write_offset, - src_addr + buffer_offset, length_to_write); - - - if(0 != ret_code) - { - return ret_code; - } - - /* update remaining length and buffer_offset pointer */ - remaining_length -= length_to_write; - buffer_offset += length_to_write; - write_offset += length_to_write; - } - - return ret_code; -} - -/** - * alt_epcq_controller2_read - * - * There's no real need to use this function as opposed to using memcpy directly. It does - * do some sanity checks on the bounds of the read. - * - * Arguments: - * - *flash_info: Pointer to general flash device structure. - * - offset: offset read from flash memory. - * - *dest_addr: destination buffer - * - length: size of reading - * - * Returns: - * 0 -> success - * -EINVAL -> Invalid arguments -**/ -int alt_epcq_controller2_read -( - alt_flash_dev *flash_info, /** device info */ - int offset, /** offset of read from base address */ - void *dest_addr, /** destination buffer */ - int length /** size of read */ -) -{ - alt_32 ret_code = 0; - alt_epcq_controller2_dev *epcq_flash_info = NULL; - - /* return -EINVAL if flash_info and dest_addr are NULL */ - if(NULL == flash_info || NULL == dest_addr) - { - return -EINVAL; - } - - epcq_flash_info = (alt_epcq_controller2_dev*)flash_info; - - /* validate arguments */ - ret_code = alt_epcq_validate_read_write_arguments(epcq_flash_info, offset, length); - - /* copy data from flash to destination address */ - if(0 == ret_code) - { - memcpy(dest_addr, (alt_u8*)epcq_flash_info->data_base + offset, length); - } - - return ret_code; -} - -/** - * altera_epcq_controller2_init - * - * alt_sys_init.c will call this function automatically through macro - * - * Information in system.h is checked against expected values that are determined by the silicon_id. - * If the information doesn't match then this system is configured incorrectly. Most likely the wrong - * type of EPCS or EPCQ device was selected when instantiating the soft IP. - * - * Arguments: - * - *flash: Pointer to EPCQ flash device structure. - * - * Returns: - * 0 -> success - * -EINVAL -> Invalid arguments. - * -ENODEV -> System is configured incorrectly. -**/ -alt_32 altera_epcq_controller2_init(alt_epcq_controller2_dev *flash) -{ - alt_u32 silicon_id = 0; - alt_u32 size_in_bytes = 0; - alt_u32 number_of_sectors = 0; - - /* return -EINVAL if flash is NULL */ - if(NULL == flash) - { - return -EINVAL; - } - - /* return -ENODEV if CSR slave is not attached */ - if(NULL == (void *)flash->csr_base) - { - return -ENODEV; - } - - - /* - * If flash is an EPCQ device, we read the EPCQ_RD_RDID register for the ID - * If flash is an EPCS device, we read the EPCQ_RD_SID register for the ID - * - * Whether or not the flash is a EPCQ or EPCS is indicated in the system.h. The system.h gets - * this value from the hw.tcl of the IP. If this value is set incorrectly, then things will go - * badly. - * - * In both cases, we can determine the number of sectors, which we can use - * to calculate a size. We compare that size to the system.h value to make sure - * the EPCQ soft IP was configured correctly. - */ - if(0 == flash->is_epcs) - { - /* If we're an EPCQ, we read EPCQ_RD_RDID for the silicon ID */ - silicon_id = IORD_ALTERA_EPCQ_CONTROLLER2_RDID(flash->csr_base); - silicon_id &= ALTERA_EPCQ_CONTROLLER2_RDID_MASK; - - /* Determine which EPCQ device so we can figure out the number of sectors */ - /* EPCQ share the same ID for the same capacity*/ - switch(silicon_id) - { - case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ16: - { - number_of_sectors = 32; - break; - } - case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ32: - { - number_of_sectors = 64; - break; - } - case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ64: - { - number_of_sectors = 128; - break; - } - case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ128: - { - number_of_sectors = 256; - break; - } - case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ256: - { - number_of_sectors = 512; - break; - } - case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ512: - { - number_of_sectors = 1024; - break; - } - case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ1024: - { - number_of_sectors = 2048; - break; - } - default: - { - return -ENODEV; - } - } - } - else { - /* If we're an EPCS, we read EPCQ_RD_SID for the silicon ID */ - silicon_id = IORD_ALTERA_EPCQ_CONTROLLER2_SID(flash->csr_base); - silicon_id &= ALTERA_EPCQ_CONTROLLER2_SID_MASK; - - /* Determine which EPCS device so we can figure out various properties */ - switch(silicon_id) - { - case ALTERA_EPCQ_CONTROLLER2_SID_EPCS16: - { - number_of_sectors = 32; - break; - } - case ALTERA_EPCQ_CONTROLLER2_SID_EPCS64: - { - number_of_sectors = 128; - break; - } - case ALTERA_EPCQ_CONTROLLER2_SID_EPCS128: - { - number_of_sectors = 256; - break; - } - default: - { - return -ENODEV; - } - } - } - - /* Calculate size of flash based on number of sectors */ - size_in_bytes = number_of_sectors * flash->sector_size; - - /* - * Make sure calculated size is the same size given in system.h - * Also check number of sectors is the same number given in system.h - * Otherwise the EPCQ IP was not configured correctly - */ - if( size_in_bytes != flash->size_in_bytes || - number_of_sectors != flash->number_of_sectors) - { - flash->dev.number_of_regions = 0; - return -ENODEV; - } - else - { - flash->silicon_id = silicon_id; - flash->number_of_sectors = number_of_sectors; - - /* - * populate fields of region_info required to conform to HAL API - * create 1 region that composed of "number_of_sectors" blocks - */ - flash->dev.number_of_regions = 1; - flash->dev.region_info[0].offset = 0; - flash->dev.region_info[0].region_size = size_in_bytes; - flash->dev.region_info[0].number_of_blocks = number_of_sectors; - flash->dev.region_info[0].block_size = flash->sector_size; - } - - - /* - * Register this device as a valid flash device type - * - * Only register the device if it's configured correctly. - */ - alt_flash_device_register(&(flash->dev)); - - - return 0; -} - - -/* - * Private API - * - * Helper functions used by Public API functions. - * - * Arguments: - * - *flash_info: Pointer to EPCQ flash device structure. - * - offset: Offset of read/write from base address. - * - length: Length of read/write in bytes. - * - * Returns: - * 0 -> success - * -EINVAL -> Invalid arguments - */ -/** - * Used to check that arguments to a read or write are valid - */ -ALT_INLINE alt_32 static alt_epcq_validate_read_write_arguments -( - alt_epcq_controller2_dev *flash_info, /** device info */ - alt_u32 offset, /** offset of read/write */ - alt_u32 length /** length of read/write */ -) -{ - alt_epcq_controller2_dev *epcq_flash_info = NULL; - alt_u32 start_address = 0; - alt_32 end_address = 0; - - /* return -EINVAL if flash_info is NULL */ - if(NULL == flash_info) - { - return -EINVAL; - } - - epcq_flash_info = (alt_epcq_controller2_dev*)flash_info; - - start_address = epcq_flash_info->data_base + offset; /** first address of read or write */ - end_address = start_address + length; /** last address of read or write (not inclusive) */ - - /* make sure start and end address is less then the end address of the flash */ - if( - start_address >= epcq_flash_info->data_end || - end_address > epcq_flash_info->data_end || - offset < 0 || - length < 0 - ) - { - return -EINVAL; - } - - return 0; -} - -/* - * Private function that polls write in progress bit EPCQ_RD_STATUS. - * - * Write in progress will be set if any of the following operations are in progress: - * -WRITE STATUS REGISTER - * -WRITE NONVOLATILE CONFIGURATION REGISTER - * -PROGRAM - * -ERASE - * - * Assumes EPCQ was configured correctly. - * - * If ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE is set, the function will time out after - * a period of time determined by that value. - * - * Arguments: - * - *epcq_flash_info: Pointer to EPCQ flash device structure. - * - * Returns: - * 0 -> success - * -EINVAL -> Invalid arguments - * -ETIME -> Time out and skipping the looping after 0.7 sec. - */ -alt_32 static alt_epcq_poll_for_write_in_progress(alt_epcq_controller2_dev* epcq_flash_info) -{ - /* we'll want to implement timeout if a timeout value is specified */ -#if ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE > 0 - alt_u32 timeout = ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE; - alt_u16 counter = 0; -#endif - - /* return -EINVAL if epcq_flash_info is NULL */ - if(NULL == epcq_flash_info) - { - return -EINVAL; - } - - /* while Write in Progress bit is set, we wait */ - while((IORD_ALTERA_EPCQ_CONTROLLER2_STATUS(epcq_flash_info->csr_base) & - ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_MASK) == - ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_BUSY) - { - alt_busy_sleep(1); /* delay 1us */ -#if ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE > 0 - if(timeout <= counter ) - { - return -ETIME; - } - - counter++; -#endif - - } - - return 0; -} - - diff --git a/software/sys_controller_bsp/libhal_bsp.a b/software/sys_controller_bsp/libhal_bsp.a deleted file mode 100644 index b3002f2..0000000 Binary files a/software/sys_controller_bsp/libhal_bsp.a and /dev/null differ diff --git a/software/sys_controller_bsp/public.mk b/software/sys_controller_bsp/public.mk index b57a1a2..1ffdabe 100644 --- a/software/sys_controller_bsp/public.mk +++ b/software/sys_controller_bsp/public.mk @@ -259,7 +259,7 @@ ALT_CPPFLAGS += -DSMALL_C_LIB # or common. none # setting hal.make.cflags_mgpopt is -mgpopt=global #ALT_CFLAGS += -mgpopt=global -ALT_CFLAGS += -march=rv32emc -mabi=ilp32e +ALT_CFLAGS += -march=rv32emc_zicsr_zifencei -mabi=ilp32e # Enable BSP generation to query if SOPC system is big endian. If true ignores # export of 'ALT_CFLAGS += -meb' to public.mk if big endian system. none diff --git a/software/sys_controller_bsp/system.h b/software/sys_controller_bsp/system.h index 6e506f6..b77361a 100644 --- a/software/sys_controller_bsp/system.h +++ b/software/sys_controller_bsp/system.h @@ -52,7 +52,7 @@ #define __SYSTEM_H_ /* Include definitions from linker script generator */ -#include "linker.h" +//#include "linker.h" /* @@ -151,7 +151,7 @@ #define __ALTERA_AVALON_ONCHIP_MEMORY2 #define __ALTERA_AVALON_PIO #define __ALTERA_AVALON_TIMER -#define __ALTERA_EPCQ_CONTROLLER2 +#define __INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP #define __ALTERA_NIOS2_GEN2 #define __ALTERA_NIOS_CUSTOM_INSTR_BITSWAP #define __ALTERA_NIOS_CUSTOM_INSTR_ENDIANCONVERTER @@ -175,19 +175,19 @@ #define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 #define ALT_NUM_INTERRUPT_CONTROLLERS 1 #define ALT_STDERR "/dev/jtag_uart_0" -#define ALT_STDERR_BASE 0x20020 +#define ALT_STDERR_BASE 0x20040 #define ALT_STDERR_DEV jtag_uart_0 #define ALT_STDERR_IS_JTAG_UART #define ALT_STDERR_PRESENT #define ALT_STDERR_TYPE "altera_avalon_jtag_uart" #define ALT_STDIN "/dev/jtag_uart_0" -#define ALT_STDIN_BASE 0x20020 +#define ALT_STDIN_BASE 0x20040 #define ALT_STDIN_DEV jtag_uart_0 #define ALT_STDIN_IS_JTAG_UART #define ALT_STDIN_PRESENT #define ALT_STDIN_TYPE "altera_avalon_jtag_uart" #define ALT_STDOUT "/dev/jtag_uart_0" -#define ALT_STDOUT_BASE 0x20020 +#define ALT_STDOUT_BASE 0x20040 #define ALT_STDOUT_DEV jtag_uart_0 #define ALT_STDOUT_IS_JTAG_UART #define ALT_STDOUT_PRESENT @@ -196,43 +196,31 @@ /* - * epcq_controller2_0_avl_csr configuration + * intel_generic_serial_flash_interface_top_0_avl_csr configuration * */ -#define ALT_MODULE_CLASS_epcq_controller2_0_avl_csr altera_epcq_controller2 -#define EPCQ_CONTROLLER2_0_AVL_CSR_BASE 0x20100 -#define EPCQ_CONTROLLER2_0_AVL_CSR_FLASH_TYPE "EPCQ16" -#define EPCQ_CONTROLLER2_0_AVL_CSR_IRQ 2 -#define EPCQ_CONTROLLER2_0_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define EPCQ_CONTROLLER2_0_AVL_CSR_IS_EPCS 0 -#define EPCQ_CONTROLLER2_0_AVL_CSR_NAME "/dev/epcq_controller2_0_avl_csr" -#define EPCQ_CONTROLLER2_0_AVL_CSR_NUMBER_OF_SECTORS 32 -#define EPCQ_CONTROLLER2_0_AVL_CSR_PAGE_SIZE 256 -#define EPCQ_CONTROLLER2_0_AVL_CSR_SECTOR_SIZE 65536 -#define EPCQ_CONTROLLER2_0_AVL_CSR_SPAN 64 -#define EPCQ_CONTROLLER2_0_AVL_CSR_SUBSECTOR_SIZE 4096 -#define EPCQ_CONTROLLER2_0_AVL_CSR_TYPE "altera_epcq_controller2" +#define ALT_MODULE_CLASS_intel_generic_serial_flash_interface_top_0_avl_csr intel_generic_serial_flash_interface_top +#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE 0x00020100 +#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_IRQ -1 +#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_NAME "/dev/intel_generic_serial_flash_interface_top_0_avl_csr" +#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_SPAN 256 +#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_TYPE "intel_generic_serial_flash_interface_top" /* - * epcq_controller2_0_avl_mem configuration + * intel_generic_serial_flash_interface_top_0_avl_mem configuration * */ -#define ALT_MODULE_CLASS_epcq_controller2_0_avl_mem altera_epcq_controller2 -#define EPCQ_CONTROLLER2_0_AVL_MEM_BASE 0x800000 -#define EPCQ_CONTROLLER2_0_AVL_MEM_FLASH_TYPE "EPCQ16" -#define EPCQ_CONTROLLER2_0_AVL_MEM_IRQ -1 -#define EPCQ_CONTROLLER2_0_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define EPCQ_CONTROLLER2_0_AVL_MEM_IS_EPCS 0 -#define EPCQ_CONTROLLER2_0_AVL_MEM_NAME "/dev/epcq_controller2_0_avl_mem" -#define EPCQ_CONTROLLER2_0_AVL_MEM_NUMBER_OF_SECTORS 32 -#define EPCQ_CONTROLLER2_0_AVL_MEM_PAGE_SIZE 256 -#define EPCQ_CONTROLLER2_0_AVL_MEM_SECTOR_SIZE 65536 -#define EPCQ_CONTROLLER2_0_AVL_MEM_SPAN 2097152 -#define EPCQ_CONTROLLER2_0_AVL_MEM_SUBSECTOR_SIZE 4096 -#define EPCQ_CONTROLLER2_0_AVL_MEM_TYPE "altera_epcq_controller_mod" +#define ALT_MODULE_CLASS_intel_generic_serial_flash_interface_top_0_avl_mem intel_generic_serial_flash_interface_top +#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_BASE 0x02000000 +#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_IRQ -1 +#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_NAME "/dev/intel_generic_serial_flash_interface_top_0_avl_mem" +#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_SPAN 2097152 +#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_TYPE "intel_generic_serial_flash_interface_top" /* @@ -279,7 +267,7 @@ */ #define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart -#define JTAG_UART_0_BASE 0x20020 +#define JTAG_UART_0_BASE 0x20040 #define JTAG_UART_0_IRQ 1 #define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0 #define JTAG_UART_0_NAME "/dev/jtag_uart_0" @@ -416,7 +404,7 @@ #define ALT_MODULE_CLASS_timer_0 altera_avalon_timer #define TIMER_0_ALWAYS_RUN 0 #define TIMER_0_BASE 0x20000 -#define TIMER_0_COUNTER_SIZE 32 +#define TIMER_0_COUNTER_SIZE 64 #define TIMER_0_FIXED_PERIOD 0 #define TIMER_0_FREQ 27000000 #define TIMER_0_IRQ 0 @@ -428,7 +416,7 @@ #define TIMER_0_PERIOD_UNITS "us" #define TIMER_0_RESET_OUTPUT 0 #define TIMER_0_SNAPSHOT 1 -#define TIMER_0_SPAN 32 +#define TIMER_0_SPAN 64 #define TIMER_0_TICKS_PER_SEC 1000000 #define TIMER_0_TIMEOUT_PULSE_OUTPUT 0 #define TIMER_0_TYPE "altera_avalon_timer" diff --git a/sys.qsys b/sys.qsys index 253950b..6852664 100644 --- a/sys.qsys +++ b/sys.qsys @@ -13,44 +13,10 @@ { datum _sortIndex { - value = "1"; + value = "0"; type = "int"; } } - element epcq_controller2_0 - { - datum _sortIndex - { - value = "6"; - type = "int"; - } - } - element epcq_controller2_0.avl_csr - { - datum _lockedAddress - { - value = "1"; - type = "boolean"; - } - datum baseAddress - { - value = "131328"; - type = "String"; - } - } - element epcq_controller2_0.avl_mem - { - datum _lockedAddress - { - value = "1"; - type = "boolean"; - } - datum baseAddress - { - value = "8388608"; - type = "String"; - } - } element hw_crc32_0 { datum _sortIndex @@ -114,23 +80,86 @@ type = "String"; } } + element ibex_0 + { + datum _sortIndex + { + value = "1"; + type = "int"; + } + } + element ibex_0.avalon_slave_dbgreg + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + } + element ibex_0.avalon_slave_dm + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + } + element intel_generic_serial_flash_interface_top_0 + { + datum _sortIndex + { + value = "6"; + type = "int"; + } + } + element intel_generic_serial_flash_interface_top_0.avl_csr + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "131328"; + type = "String"; + } + } + element intel_generic_serial_flash_interface_top_0.avl_mem + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "33554432"; + type = "String"; + } + } element jtag_uart_0 { datum _sortIndex { - value = "0"; + value = "5"; type = "int"; } } + element jtag_uart_0.avalon_jtag_slave + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "131136"; + type = "String"; + } + } element master_0 - { - datum _sortIndex - { - value = "4"; - type = "int"; - } - } - element onchip_memory2_0 { datum _sortIndex { @@ -138,6 +167,14 @@ type = "int"; } } + element onchip_memory2_0 + { + datum _sortIndex + { + value = "2"; + type = "int"; + } + } element onchip_memory2_0.s1 { datum _lockedAddress @@ -151,6 +188,19 @@ type = "String"; } } + element onchip_memory2_0.s2 + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "65536"; + type = "String"; + } + } element osd_generator_0 { datum _sortIndex @@ -235,22 +285,6 @@ type = "String"; } } - element pulpino_0 - { - datum _sortIndex - { - value = "2"; - type = "int"; - } - } - element pulpino_0.avalon_slave_debug - { - datum _lockedAddress - { - value = "1"; - type = "boolean"; - } - } element sc_config_0 { datum _sortIndex @@ -276,10 +310,23 @@ { datum _sortIndex { - value = "5"; + value = "4"; type = "int"; } } + element timer_0.s1 + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "131072"; + type = "String"; + } + } } ]]> @@ -312,6 +359,11 @@ internal="i2c_opencores_1.export" type="conduit" dir="end" /> + - - + - - - - - - - - - - COMPILER_SUPPORT 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 ANY_QFP 0 ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 HARDCOPY 0 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_HSPICE_WRITER_SUPPORT 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_18_BIT_MULTS 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IFP_USE_LEGACY_IO_CHECKER 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_BARE_DIE 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_JZ_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_SMI_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M144K_MEMORY 0 M10K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_MIGRATABLE 0 NOT_LISTED 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_POF 0 NO_PIN_OUT 0 NO_RPE_SUPPORT 0 NO_TDC_SUPPORT 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_CRC 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QMAP_IN_DEVELOPMENT 0 QFIT_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_OCT_AUTO_CALIBRATION 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -406,7 +474,7 @@ @@ -420,7 +488,7 @@ $${FILENAME}_onchip_memory2_0 @@ -429,15 +497,15 @@ - COMPILER_SUPPORT 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 ANY_QFP 0 ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 HARDCOPY 0 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_HSPICE_WRITER_SUPPORT 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_18_BIT_MULTS 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IFP_USE_LEGACY_IO_CHECKER 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_BARE_DIE 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_JZ_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_SMI_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M144K_MEMORY 0 M10K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_MIGRATABLE 0 NOT_LISTED 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_POF 0 NO_PIN_OUT 0 NO_RPE_SUPPORT 0 NO_TDC_SUPPORT 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_CRC 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QMAP_IN_DEVELOPMENT 0 QFIT_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_OCT_AUTO_CALIBRATION 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 - + COMPILER_SUPPORT 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 ANY_QFP 0 ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 HARDCOPY 0 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_HSPICE_WRITER_SUPPORT 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_18_BIT_MULTS 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IFP_USE_LEGACY_IO_CHECKER 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_BARE_DIE 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_JZ_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_LTH_485_PIN 0 IS_SMI_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M144K_MEMORY 0 M10K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_MIGRATABLE 0 NOT_LISTED 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_POF 0 NO_PIN_OUT 0 NO_RPE_SUPPORT 0 NO_TDC_SUPPORT 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_CRC 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QMAP_IN_DEVELOPMENT 0 QFIT_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_OCT_AUTO_CALIBRATION 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 + - + - + @@ -450,7 +518,7 @@ - + @@ -464,7 +532,7 @@ - + @@ -479,22 +547,10 @@ - - - - - - - - - - - - - + - + @@ -506,26 +562,17 @@ - - - - - - + @@ -533,8 +580,8 @@ @@ -542,8 +589,8 @@ @@ -551,8 +598,8 @@ @@ -560,8 +607,8 @@ @@ -569,8 +616,8 @@ @@ -578,26 +625,35 @@ + version="24.1" + start="ibex_0.avalon_master_bus_data" + end="ibex_0.avalon_slave_dm"> + + + + + + version="24.1" + start="ibex_0.avalon_master_bus_data" + end="intel_generic_serial_flash_interface_top_0.avl_mem"> - + @@ -605,8 +661,8 @@ @@ -614,8 +670,8 @@ @@ -623,186 +679,220 @@ + version="24.1" + start="ibex_0.avalon_master_bus_data" + end="onchip_memory2_0.s2"> + version="24.1" + start="ibex_0.avalon_master_bus_instr" + end="ibex_0.avalon_slave_dm"> + + + + + - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + - + - - - - - - - - - - + version="24.1" + start="ibex_0.interrupt_receiver" + end="i2c_opencores_0.interrupt_sender"> + + + + + + + end="intel_generic_serial_flash_interface_top_0.reset" /> - + diff --git a/sys.sopcinfo b/sys.sopcinfo index 63a6d53..948d898 100644 --- a/sys.sopcinfo +++ b/sys.sopcinfo @@ -1,11 +1,11 @@ - - + + java.lang.Integer - 1721036059 + 1743023379 false true false @@ -95,7 +95,7 @@ true true - + @@ -148,7 +148,7 @@ the requested settings for a module instance. --> true true - + @@ -213,7 +213,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -262,7 +262,7 @@ parameters are a RESULT of the module parameters. --> reset_n - + @@ -360,24 +360,30 @@ parameters are a RESULT of the module parameters. --> clk master_0.clk + + false + intel_generic_serial_flash_interface_top_0 + clk + intel_generic_serial_flash_interface_top_0.clk + false onchip_memory2_0 clk1 onchip_memory2_0.clk1 - - false - pulpino_0 - clk_sink - pulpino_0.clk_sink - false hw_crc32_0 clk_sink hw_crc32_0.clk_sink + + false + ibex_0 + clk_sink + ibex_0.clk_sink + false i2c_opencores_0 @@ -408,14 +414,8 @@ parameters are a RESULT of the module parameters. --> clock_sink pll_reconfig_0.clock_sink - - false - epcq_controller2_0 - clock_sink - epcq_controller2_0.clock_sink - - + @@ -477,1165 +477,6 @@ parameters are a RESULT of the module parameters. --> - - - - embeddedsw.CMacro.FLASH_TYPE - EPCQ16 - - - embeddedsw.CMacro.IS_EPCS - 0 - - - embeddedsw.CMacro.NUMBER_OF_SECTORS - 32 - - - embeddedsw.CMacro.PAGE_SIZE - 256 - - - embeddedsw.CMacro.SECTOR_SIZE - 65536 - - - embeddedsw.CMacro.SUBSECTOR_SIZE - 4096 - - - embeddedsw.dts.compatible - altr,epcq-1.0 - - - embeddedsw.dts.group - epcq - - - embeddedsw.dts.name - epcq - - - embeddedsw.dts.vendor - altr - - - embeddedsw.memoryInfo.GENERATE_DAT_SYM - 0 - - - embeddedsw.memoryInfo.GENERATE_FLASH - 0 - - - embeddedsw.memoryInfo.GENERATE_HEX - 1 - - - embeddedsw.memoryInfo.HEX_INSTALL_DIR - QPF_DIR - - - embeddedsw.memoryInfo.IS_FLASH - 1 - - - embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH - 32 - - - embeddedsw.memoryInfo.USE_BYTE_ADDRESSING_FOR_HEX - 1 - - - java.lang.String - CYCLONEIVE - false - true - false - true - DEVICE_FAMILY - - - int - 1 - true - true - false - true - - - int - 1 - true - true - false - true - - - int - 19 - true - true - false - true - - - int - 24 - true - true - false - true - - - int - 0 - true - true - false - true - - - java.lang.String - COMPILER_SUPPORT 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 ANY_QFP 0 ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 HARDCOPY 0 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_HSPICE_WRITER_SUPPORT 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_18_BIT_MULTS 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IFP_USE_LEGACY_IO_CHECKER 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_BARE_DIE 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_JZ_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_SMI_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M144K_MEMORY 0 M10K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_MIGRATABLE 0 NOT_LISTED 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_POF 0 NO_PIN_OUT 0 NO_RPE_SUPPORT 0 NO_TDC_SUPPORT 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_CRC 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QMAP_IN_DEVELOPMENT 0 QFIT_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_OCT_AUTO_CALIBRATION 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 - false - true - false - true - DEVICE_FEATURES - - - int - 0 - false - true - false - true - - - long - 27000000 - false - true - false - true - CLOCK_RATE - clock_sink - - - java.lang.String - EPCQ16 - false - true - true - true - - - java.lang.String - STANDARD - false - false - true - true - - - int - 1 - false - false - true - true - - - java.lang.String - EP4CE15E22C8 - false - true - false - true - DEVICE - - - java.lang.String - 8 - false - true - false - true - DEVICE_SPEEDGRADE - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 64 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - 0 - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - avl_csr_read - Input - 1 - read - - - avl_csr_waitrequest - Output - 1 - waitrequest - - - avl_csr_write - Input - 1 - write - - - avl_csr_addr - Input - 4 - address - - - avl_csr_wrdata - Input - 32 - writedata - - - avl_csr_rddata - Output - 32 - readdata - - - avl_csr_rddata_valid - Output - 1 - readdatavalid - - - - - - embeddedsw.configuration.isFlash - 1 - - - embeddedsw.configuration.isMemoryDevice - 1 - - - embeddedsw.configuration.isNonVolatileStorage - 1 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 2097152 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - 0 - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - true - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - avl_mem_write - Input - 1 - write - - - avl_mem_burstcount - Input - 7 - burstcount - - - avl_mem_waitrequest - Output - 1 - waitrequest - - - avl_mem_read - Input - 1 - read - - - avl_mem_addr - Input - 19 - address - - - avl_mem_wrdata - Input - 32 - writedata - - - avl_mem_rddata - Output - 32 - readdata - - - avl_mem_rddata_valid - Output - 1 - readdatavalid - - - avl_mem_byteenable - Input - 4 - byteenable - - - - - - com.altera.entityinterfaces.IConnectionPoint - epcq_controller2_0.avl_csr - false - true - true - true - - - java.lang.String - clock_sink - false - true - false - true - - - java.lang.String - reset - false - true - false - true - - - java.lang.Integer - 0 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - irq - Output - 1 - irq - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 27000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - @@ -1655,7 +496,7 @@ the requested settings for a module instance. --> true true - + @@ -1700,7 +541,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -1745,7 +586,7 @@ parameters are a RESULT of the module parameters. --> reset - + @@ -2154,7 +995,7 @@ the requested settings for a module instance. --> true true - + @@ -2199,7 +1040,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -2244,7 +1085,7 @@ parameters are a RESULT of the module parameters. --> reset - + @@ -2301,7 +1142,7 @@ parameters are a RESULT of the module parameters. --> export - + @@ -2672,7 +1513,7 @@ parameters are a RESULT of the module parameters. --> waitrequest_n - + @@ -2781,7 +1622,7 @@ the requested settings for a module instance. --> true true - + @@ -2826,7 +1667,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -2871,7 +1712,7 @@ parameters are a RESULT of the module parameters. --> reset - + @@ -2928,7 +1769,7 @@ parameters are a RESULT of the module parameters. --> export - + @@ -3299,7 +2140,7 @@ parameters are a RESULT of the module parameters. --> waitrequest_n - + @@ -3377,10 +2218,2930 @@ parameters are a RESULT of the module parameters. --> + + + + boolean + true + false + true + true + true + + + java.math.BigInteger + 15 + false + true + false + true + INTERRUPTS_USED + interrupt_receiver + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk_i + Input + 1 + clk + + + + + + java.lang.String + clk_sink + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + rst_ni + Input + 1 + reset_n + + + + + + java.lang.String + clk_sink + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + boot_addr_i + Input + 32 + boot_addr_i + + + core_sleep_o + Output + 1 + core_sleep_o + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + java.lang.String + clk_sink + false + true + false + true + + + java.lang.String + reset_sink + false + true + false + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + INDIVIDUAL_REQUESTS + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + true + + irq_fast_i + Input + 15 + irq + + + false + i2c_opencores_1 + interrupt_sender + i2c_opencores_1.interrupt_sender + 0 + + + false + i2c_opencores_0 + interrupt_sender + i2c_opencores_0.interrupt_sender + 1 + + + false + jtag_uart_0 + irq + jtag_uart_0.irq + 2 + + + false + timer_0 + irq + timer_0.irq + 3 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk_sink + false + true + true + true + + + java.lang.String + reset_sink + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + bus_instr_addr + Output + 32 + address + + + bus_instr_rdata + Input + 32 + readdata + + + bus_instr_read + Output + 1 + read + + + bus_instr_rvalid + Input + 1 + readdatavalid + + + bus_instr_busy + Input + 1 + waitrequest + + + false + ibex_0 + avalon_slave_dm + ibex_0.avalon_slave_dm + 0 + 4096 + + + false + intel_generic_serial_flash_interface_top_0 + avl_mem + intel_generic_serial_flash_interface_top_0.avl_mem + 33554432 + 2097152 + + + false + onchip_memory2_0 + s1 + onchip_memory2_0.s1 + 65536 + 16384 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk_sink + false + true + true + true + + + java.lang.String + reset_sink + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + bus_data_addr + Output + 32 + address + + + bus_data_rdata + Input + 32 + readdata + + + bus_data_read + Output + 1 + read + + + bus_data_rvalid + Input + 1 + readdatavalid + + + bus_data_busy + Input + 1 + waitrequest + + + bus_data_write + Output + 1 + write + + + bus_data_be + Output + 4 + byteenable + + + bus_data_wdata + Output + 32 + writedata + + + bus_data_resp + Input + 2 + response + + + bus_data_wrespvalid + Input + 1 + writeresponsevalid + + + false + jtag_uart_0 + avalon_jtag_slave + jtag_uart_0.avalon_jtag_slave + 131136 + 8 + + + false + sc_config_0 + avalon_s + sc_config_0.avalon_s + 139264 + 64 + + + false + osd_generator_0 + avalon_s + osd_generator_0.avalon_s + 147456 + 1024 + + + false + pll_reconfig_0 + avalon_s + pll_reconfig_0.avalon_s + 163840 + 32 + + + false + hw_crc32_0 + avalon_slave + hw_crc32_0.avalon_slave + 135168 + 32 + + + false + i2c_opencores_0 + avalon_slave_0 + i2c_opencores_0.avalon_slave_0 + 135232 + 32 + + + false + i2c_opencores_1 + avalon_slave_0 + i2c_opencores_1.avalon_slave_0 + 135200 + 32 + + + false + ibex_0 + avalon_slave_dm + ibex_0.avalon_slave_dm + 0 + 4096 + + + false + intel_generic_serial_flash_interface_top_0 + avl_csr + intel_generic_serial_flash_interface_top_0.avl_csr + 131328 + 256 + + + false + intel_generic_serial_flash_interface_top_0 + avl_mem + intel_generic_serial_flash_interface_top_0.avl_mem + 33554432 + 2097152 + + + false + timer_0 + s1 + timer_0.s1 + 131072 + 64 + + + false + pio_0 + s1 + pio_0.s1 + 135392 + 16 + + + false + pio_1 + s1 + pio_1.s1 + 135376 + 16 + + + false + onchip_memory2_0 + s2 + onchip_memory2_0.s2 + 65536 + 16384 + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4096 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk_sink + false + true + true + true + + + java.lang.String + reset_sink + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + dm_avalon_s_address + Input + 12 + address + + + dm_avalon_s_readdata + Output + 32 + readdata + + + dm_avalon_s_read + Input + 1 + read + + + dm_avalon_s_write + Input + 1 + write + + + dm_avalon_s_writedata + Input + 32 + writedata + + + dm_avalon_s_byteenable + Input + 4 + byteenable + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 1024 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk_sink + false + true + true + true + + + java.lang.String + reset_sink + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + dbgreg_avalon_s_address + Input + 10 + address + + + dbgreg_avalon_s_readdata + Output + 32 + readdata + + + dbgreg_avalon_s_readdatavalid + Output + 1 + readdatavalid + + + dbgreg_avalon_s_read + Input + 1 + read + + + dbgreg_avalon_s_response + Output + 2 + response + + + dbgreg_avalon_s_write + Input + 1 + write + + + dbgreg_avalon_s_writedata + Input + 32 + writedata + + + dbgreg_avalon_s_writeresponsevalid + Output + 1 + writeresponsevalid + + + dbgreg_avalon_s_byteenable + Input + 4 + byteenable + + + dbgreg_avalon_s_chipselect + Input + 1 + chipselect + + + dbgreg_avalon_s_waitrequest_n + Output + 1 + waitrequest_n + + + + + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 0 + + + embeddedsw.memoryInfo.GENERATE_FLASH + 0 + + + embeddedsw.memoryInfo.GENERATE_HEX + 1 + + + embeddedsw.memoryInfo.HEX_INSTALL_DIR + QPF_DIR + + + embeddedsw.memoryInfo.IS_FLASH + 1 + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 32 + + + embeddedsw.memoryInfo.USE_BYTE_ADDRESSING_FOR_HEX + 1 + + + java.lang.String + CYCLONEIVE + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + CYCLONEIVE + false + true + false + true + DEVICE_FAMILY + + + int + 16 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 19 + true + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 3 + false + true + false + true + + + int + 1282 + false + true + false + true + + + int + 6149 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EP4CE15E22C8 + false + true + false + true + DEVICE + + + java.lang.String + 8 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 256 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + 0 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + avl_csr_address + Input + 6 + address + + + avl_csr_read + Input + 1 + read + + + avl_csr_readdata + Output + 32 + readdata + + + avl_csr_write + Input + 1 + write + + + avl_csr_writedata + Input + 32 + writedata + + + avl_csr_waitrequest + Output + 1 + waitrequest + + + avl_csr_readdatavalid + Output + 1 + readdatavalid + + + + + + embeddedsw.configuration.isFlash + 1 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 1 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 2097152 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + 0 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + true + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + avl_mem_write + Input + 1 + write + + + avl_mem_burstcount + Input + 7 + burstcount + + + avl_mem_waitrequest + Output + 1 + waitrequest + + + avl_mem_read + Input + 1 + read + + + avl_mem_address + Input + 19 + address + + + avl_mem_writedata + Input + 32 + writedata + + + avl_mem_readdata + Output + 32 + readdata + + + avl_mem_readdatavalid + Output + 1 + readdatavalid + + + avl_mem_byteenable + Input + 4 + byteenable + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk_clk + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_reset + Input + 1 + reset + + + @@ -3504,6 +5265,70 @@ the requested settings for a module instance. --> true true + + boolean + false + false + true + true + true + + + int + 8 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 4 + true + true + false + true + + + java.lang.String + OFF + true + true + false + true + + + java.lang.String + OFF + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 16 + true + true + false + true + long 27000000 @@ -3563,7 +5388,7 @@ the requested settings for a module instance. --> true true - + @@ -3624,7 +5449,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -3669,7 +5494,7 @@ parameters are a RESULT of the module parameters. --> reset_n - + @@ -4046,7 +5871,7 @@ parameters are a RESULT of the module parameters. --> waitrequest - + @@ -4127,7 +5952,7 @@ parameters are a RESULT of the module parameters. --> @@ -4221,7 +6046,7 @@ the requested settings for a module instance. --> true true - + @@ -4266,7 +6091,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -4311,7 +6136,7 @@ parameters are a RESULT of the module parameters. --> reset - + @@ -4631,22 +6456,38 @@ parameters are a RESULT of the module parameters. --> false - pulpino_0 - avalon_slave_debug - pulpino_0.avalon_slave_debug + ibex_0 + avalon_slave_dbgreg + ibex_0.avalon_slave_dbgreg 0 - 32768 + 1024 + + + false + intel_generic_serial_flash_interface_top_0 + avl_csr + intel_generic_serial_flash_interface_top_0.avl_csr + 131328 + 256 + + + false + intel_generic_serial_flash_interface_top_0 + avl_mem + intel_generic_serial_flash_interface_top_0.avl_mem + 33554432 + 2097152 false onchip_memory2_0 - s1 - onchip_memory2_0.s1 + s2 + onchip_memory2_0.s2 65536 - 41984 + 16384 - + @@ -4711,7 +6552,7 @@ parameters are a RESULT of the module parameters. --> @@ -4729,7 +6570,7 @@ the requested settings for a module instance. --> embeddedsw.CMacro.DUAL_PORT - 0 + 1 embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE @@ -4741,7 +6582,7 @@ the requested settings for a module instance. --> embeddedsw.CMacro.INIT_MEM_CONTENT - 1 + 0 embeddedsw.CMacro.INSTANCE_ID @@ -4769,7 +6610,7 @@ the requested settings for a module instance. --> embeddedsw.CMacro.SIZE_VALUE - 41984 + 16384 embeddedsw.CMacro.WRITABLE @@ -4845,7 +6686,7 @@ the requested settings for a module instance. --> boolean - false + true false true true @@ -4855,7 +6696,7 @@ the requested settings for a module instance. --> boolean false false - false + true true true @@ -4869,7 +6710,7 @@ the requested settings for a module instance. --> boolean - true + false false true true @@ -4887,7 +6728,7 @@ the requested settings for a module instance. --> boolean false false - true + false true true @@ -4901,7 +6742,7 @@ the requested settings for a module instance. --> long - 41984 + 16384 false true true @@ -4911,7 +6752,7 @@ the requested settings for a module instance. --> java.lang.String DONT_CARE false - false + true true true @@ -4935,7 +6776,7 @@ the requested settings for a module instance. --> boolean true false - false + true true true @@ -4959,7 +6800,7 @@ the requested settings for a module instance. --> int 1 false - false + true true true @@ -4967,7 +6808,7 @@ the requested settings for a module instance. --> boolean false false - true + false true true @@ -5031,7 +6872,7 @@ the requested settings for a module instance. --> java.lang.String - COMPILER_SUPPORT 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 ANY_QFP 0 ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 HARDCOPY 0 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_HSPICE_WRITER_SUPPORT 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_18_BIT_MULTS 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IFP_USE_LEGACY_IO_CHECKER 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_BARE_DIE 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_JZ_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_SMI_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M144K_MEMORY 0 M10K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_MIGRATABLE 0 NOT_LISTED 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_POF 0 NO_PIN_OUT 0 NO_RPE_SUPPORT 0 NO_TDC_SUPPORT 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_CRC 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QMAP_IN_DEVELOPMENT 0 QFIT_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_OCT_AUTO_CALIBRATION 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 + COMPILER_SUPPORT 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 ANY_QFP 0 ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 HARDCOPY 0 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_HSPICE_WRITER_SUPPORT 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_18_BIT_MULTS 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IFP_USE_LEGACY_IO_CHECKER 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_BARE_DIE 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_JZ_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_LTH_485_PIN 0 IS_SMI_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M144K_MEMORY 0 M10K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_MIGRATABLE 0 NOT_LISTED 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_POF 0 NO_PIN_OUT 0 NO_RPE_SUPPORT 0 NO_TDC_SUPPORT 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_CRC 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QMAP_IN_DEVELOPMENT 0 QFIT_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_OCT_AUTO_CALIBRATION 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 false true false @@ -5040,7 +6881,7 @@ the requested settings for a module instance. --> int - 14 + 12 true true false @@ -5048,7 +6889,7 @@ the requested settings for a module instance. --> int - 14 + 12 true true false @@ -5102,52 +6943,7 @@ the requested settings for a module instance. --> true true - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk - Input - 1 - clk - - - + @@ -5177,7 +6973,7 @@ parameters are a RESULT of the module parameters. --> int - 0 + 1 false true false @@ -5185,7 +6981,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 41984 + 16384 true true false @@ -5273,7 +7069,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 41984 + 16384 false true true @@ -5484,7 +7280,7 @@ parameters are a RESULT of the module parameters. --> address Input - 14 + 12 address @@ -5524,7 +7320,429 @@ parameters are a RESULT of the module parameters. --> byteenable - + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 1 + false + true + false + true + + + java.math.BigInteger + 16384 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk1 + false + true + true + true + + + java.lang.String + reset1 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 16384 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address2 + Input + 12 + address + + + chipselect2 + Input + 1 + chipselect + + + clken2 + Input + 1 + clken + + + write2 + Input + 1 + write + + + readdata2 + Output + 32 + readdata + + + writedata2 + Input + 32 + writedata + + + byteenable2 + Input + 4 + byteenable + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + @@ -5599,7 +7817,7 @@ the requested settings for a module instance. --> true true - + @@ -5644,7 +7862,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -5689,7 +7907,7 @@ parameters are a RESULT of the module parameters. --> reset - + @@ -6072,7 +8290,7 @@ parameters are a RESULT of the module parameters. --> waitrequest_n - + @@ -6142,7 +8360,7 @@ parameters are a RESULT of the module parameters. --> - + @@ -6399,7 +8617,7 @@ the requested settings for a module instance. --> true true - + @@ -6460,7 +8678,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -6505,7 +8723,7 @@ parameters are a RESULT of the module parameters. --> reset_n - + @@ -6870,7 +9088,7 @@ parameters are a RESULT of the module parameters. --> readdata - + @@ -6916,7 +9134,7 @@ parameters are a RESULT of the module parameters. --> - + @@ -7173,7 +9391,7 @@ the requested settings for a module instance. --> true true - + @@ -7234,7 +9452,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -7279,7 +9497,7 @@ parameters are a RESULT of the module parameters. --> reset_n - + @@ -7626,7 +9844,7 @@ parameters are a RESULT of the module parameters. --> readdata - + @@ -7695,7 +9913,7 @@ the requested settings for a module instance. --> true true - + @@ -7740,7 +9958,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -7785,7 +10003,7 @@ parameters are a RESULT of the module parameters. --> reset - + @@ -8168,7 +10386,7 @@ parameters are a RESULT of the module parameters. --> waitrequest_n - + @@ -8244,1470 +10462,6 @@ parameters are a RESULT of the module parameters. --> - - - - int - 32 - false - true - true - true - - - int - 32 - false - true - true - true - - - int - 10 - false - true - true - true - - - int - 10 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - true - true - - - java.math.BigInteger - 31 - false - true - false - true - INTERRUPTS_USED - interrupt_receiver - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - clk_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - rst_n - Input - 1 - reset_n - - - - - - java.lang.String - clk_sink - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - testmode_i - Input - 1 - testmode_i - - - fetch_enable_i - Input - 1 - fetch_enable_i - - - clock_gating_i - Input - 1 - clock_gating_i - - - boot_addr_i - Input - 32 - boot_addr_i - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk - Input - 1 - clk - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - java.lang.String - clk_sink - false - true - false - true - - - java.lang.String - reset_sink - false - true - false - true - - - java.lang.String - - false - true - false - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - INDIVIDUAL_REQUESTS - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - true - - irq_i - Input - 32 - irq - - - false - i2c_opencores_0 - interrupt_sender - i2c_opencores_0.interrupt_sender - 3 - - - false - i2c_opencores_1 - interrupt_sender - i2c_opencores_1.interrupt_sender - 4 - - - false - epcq_controller2_0 - interrupt_sender - epcq_controller2_0.interrupt_sender - 2 - - - false - timer_0 - irq - timer_0.irq - 0 - - - false - jtag_uart_0 - irq - jtag_uart_0.irq - 1 - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - int - 0 - false - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - int - 8 - false - true - true - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 32 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - true - - instr_addr - Output - 32 - address - - - instr_rdata - Input - 32 - readdata - - - instr_read - Output - 1 - read - - - instr_rvalid - Input - 1 - readdatavalid - - - instr_busy - Input - 1 - waitrequest - - - false - onchip_memory2_0 - s1 - onchip_memory2_0.s1 - 65536 - 41984 - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - int - 0 - false - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - int - 8 - false - true - true - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 32 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - true - - lsu_addr - Output - 32 - address - - - lsu_rdata - Input - 32 - readdata - - - lsu_read - Output - 1 - read - - - lsu_rvalid - Input - 1 - readdatavalid - - - lsu_busy - Input - 1 - waitrequest - - - lsu_write - Output - 1 - write - - - lsu_be - Output - 4 - byteenable - - - lsu_wdata - Output - 32 - writedata - - - lsu_resp - Input - 2 - response - - - lsu_wrespvalid - Input - 1 - writeresponsevalid - - - false - jtag_uart_0 - avalon_jtag_slave - jtag_uart_0.avalon_jtag_slave - 131104 - 8 - - - false - sc_config_0 - avalon_s - sc_config_0.avalon_s - 139264 - 64 - - - false - osd_generator_0 - avalon_s - osd_generator_0.avalon_s - 147456 - 1024 - - - false - pll_reconfig_0 - avalon_s - pll_reconfig_0.avalon_s - 163840 - 32 - - - false - hw_crc32_0 - avalon_slave - hw_crc32_0.avalon_slave - 135168 - 32 - - - false - i2c_opencores_0 - avalon_slave_0 - i2c_opencores_0.avalon_slave_0 - 135232 - 32 - - - false - i2c_opencores_1 - avalon_slave_0 - i2c_opencores_1.avalon_slave_0 - 135200 - 32 - - - false - epcq_controller2_0 - avl_csr - epcq_controller2_0.avl_csr - 131328 - 64 - - - false - epcq_controller2_0 - avl_mem - epcq_controller2_0.avl_mem - 8388608 - 2097152 - - - false - timer_0 - s1 - timer_0.s1 - 131072 - 32 - - - false - pio_0 - s1 - pio_0.s1 - 135392 - 16 - - - false - pio_1 - s1 - pio_1.s1 - 135376 - 16 - - - false - onchip_memory2_0 - s1 - onchip_memory2_0.s1 - 65536 - 41984 - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 32768 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk_sink - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - debug_addr - Input - 15 - address - - - debug_rdata - Output - 32 - readdata - - - debug_read - Input - 1 - read - - - debug_rvalid - Output - 1 - readdatavalid - - - debug_busy - Output - 1 - waitrequest - - - debug_write - Input - 1 - write - - - debug_wdata - Input - 32 - writedata - - - @@ -9727,7 +10481,7 @@ the requested settings for a module instance. --> true true - + @@ -9772,7 +10526,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -9817,7 +10571,7 @@ parameters are a RESULT of the module parameters. --> reset - + @@ -10200,7 +10954,7 @@ parameters are a RESULT of the module parameters. --> waitrequest_n - + @@ -10333,7 +11087,7 @@ parameters are a RESULT of the module parameters. --> @@ -10343,7 +11097,7 @@ the requested settings for a module instance. --> embeddedsw.CMacro.COUNTER_SIZE - 32 + 64 embeddedsw.CMacro.FIXED_PERIOD @@ -10419,7 +11173,7 @@ the requested settings for a module instance. --> int - 32 + 64 false true true @@ -10541,7 +11295,7 @@ the requested settings for a module instance. --> int - 3 + 4 true true false @@ -10563,7 +11317,7 @@ the requested settings for a module instance. --> true true - + @@ -10624,7 +11378,7 @@ parameters are a RESULT of the module parameters. --> clk - + @@ -10669,7 +11423,7 @@ parameters are a RESULT of the module parameters. --> reset_n - + @@ -10711,7 +11465,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 8 + 16 true true false @@ -11010,7 +11764,7 @@ parameters are a RESULT of the module parameters. --> address Input - 3 + 4 address @@ -11038,7 +11792,7 @@ parameters are a RESULT of the module parameters. --> write_n - + @@ -11117,61 +11871,10 @@ parameters are a RESULT of the module parameters. --> - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00010000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pulpino_0 - avalon_master_instr - onchip_memory2_0 - s1 - - int @@ -11183,7 +11886,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x00020020 + 0x00020040 false true true @@ -11213,16 +11916,16 @@ parameters are a RESULT of the module parameters. --> true true - pulpino_0 - avalon_master_lsu + ibex_0 + avalon_master_bus_data jtag_uart_0 avalon_jtag_slave int @@ -11264,16 +11967,16 @@ parameters are a RESULT of the module parameters. --> true true - pulpino_0 - avalon_master_lsu + ibex_0 + avalon_master_bus_data sc_config_0 avalon_s int @@ -11315,16 +12018,16 @@ parameters are a RESULT of the module parameters. --> true true - pulpino_0 - avalon_master_lsu + ibex_0 + avalon_master_bus_data osd_generator_0 avalon_s int @@ -11366,16 +12069,16 @@ parameters are a RESULT of the module parameters. --> true true - pulpino_0 - avalon_master_lsu + ibex_0 + avalon_master_bus_data pll_reconfig_0 avalon_s int @@ -11417,16 +12120,16 @@ parameters are a RESULT of the module parameters. --> true true - pulpino_0 - avalon_master_lsu + ibex_0 + avalon_master_bus_data hw_crc32_0 avalon_slave int @@ -11468,16 +12171,16 @@ parameters are a RESULT of the module parameters. --> true true - pulpino_0 - avalon_master_lsu + ibex_0 + avalon_master_bus_data i2c_opencores_0 avalon_slave_0 int @@ -11519,17 +12222,68 @@ parameters are a RESULT of the module parameters. --> true true - pulpino_0 - avalon_master_lsu + ibex_0 + avalon_master_bus_data i2c_opencores_1 avalon_slave_0 + version="24.1" + start="ibex_0.avalon_master_bus_data" + end="ibex_0.avalon_slave_dm"> + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x0000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + ibex_0 + avalon_master_bus_data + ibex_0 + avalon_slave_dm + + int 1 @@ -11570,17 +12324,17 @@ parameters are a RESULT of the module parameters. --> true true - pulpino_0 - avalon_master_lsu - epcq_controller2_0 + ibex_0 + avalon_master_bus_data + intel_generic_serial_flash_interface_top_0 avl_csr + version="24.1" + start="ibex_0.avalon_master_bus_data" + end="intel_generic_serial_flash_interface_top_0.avl_mem"> int 1 @@ -11591,7 +12345,7 @@ parameters are a RESULT of the module parameters. --> java.math.BigInteger - 0x00800000 + 0x02000000 false true true @@ -11621,16 +12375,16 @@ parameters are a RESULT of the module parameters. --> true true - pulpino_0 - avalon_master_lsu - epcq_controller2_0 + ibex_0 + avalon_master_bus_data + intel_generic_serial_flash_interface_top_0 avl_mem int @@ -11672,16 +12426,16 @@ parameters are a RESULT of the module parameters. --> true true - pulpino_0 - avalon_master_lsu + ibex_0 + avalon_master_bus_data timer_0 s1 int @@ -11723,16 +12477,16 @@ parameters are a RESULT of the module parameters. --> true true - pulpino_0 - avalon_master_lsu + ibex_0 + avalon_master_bus_data pio_0 s1 int @@ -11774,16 +12528,169 @@ parameters are a RESULT of the module parameters. --> true true - pulpino_0 - avalon_master_lsu + ibex_0 + avalon_master_bus_data pio_1 s1 + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00010000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + ibex_0 + avalon_master_bus_data + onchip_memory2_0 + s2 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x0000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + ibex_0 + avalon_master_bus_instr + ibex_0 + avalon_slave_dm + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x02000000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + ibex_0 + avalon_master_bus_instr + intel_generic_serial_flash_interface_top_0 + avl_mem + + int @@ -11825,17 +12732,17 @@ parameters are a RESULT of the module parameters. --> true true - pulpino_0 - avalon_master_lsu + ibex_0 + avalon_master_bus_instr onchip_memory2_0 s1 + end="ibex_0.avalon_slave_dbgreg"> int 1 @@ -11878,15 +12785,117 @@ parameters are a RESULT of the module parameters. --> master_0 master - pulpino_0 - avalon_slave_debug + ibex_0 + avalon_slave_dbgreg + end="intel_generic_serial_flash_interface_top_0.avl_csr"> + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00020100 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + master_0 + master + intel_generic_serial_flash_interface_top_0 + avl_csr + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x02000000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + master_0 + master + intel_generic_serial_flash_interface_top_0 + avl_mem + + int 1 @@ -11930,12 +12939,12 @@ parameters are a RESULT of the module parameters. --> master_0 master onchip_memory2_0 - s1 + s2 @@ -11962,7 +12971,7 @@ parameters are a RESULT of the module parameters. --> @@ -11989,7 +12998,7 @@ parameters are a RESULT of the module parameters. --> @@ -12016,7 +13025,7 @@ parameters are a RESULT of the module parameters. --> @@ -12043,7 +13052,7 @@ parameters are a RESULT of the module parameters. --> @@ -12067,10 +13076,37 @@ parameters are a RESULT of the module parameters. --> master_0 clk + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_27 + clk + intel_generic_serial_flash_interface_top_0 + clk + @@ -12094,37 +13130,10 @@ parameters are a RESULT of the module parameters. --> onchip_memory2_0 clk1 - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk - pulpino_0 - clk_sink - @@ -12148,10 +13157,37 @@ parameters are a RESULT of the module parameters. --> hw_crc32_0 clk_sink + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_27 + clk + ibex_0 + clk_sink + @@ -12178,7 +13214,7 @@ parameters are a RESULT of the module parameters. --> @@ -12205,7 +13241,7 @@ parameters are a RESULT of the module parameters. --> @@ -12232,7 +13268,7 @@ parameters are a RESULT of the module parameters. --> @@ -12259,7 +13295,7 @@ parameters are a RESULT of the module parameters. --> @@ -12284,143 +13320,11 @@ parameters are a RESULT of the module parameters. --> clock_sink - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk - epcq_controller2_0 - clock_sink - - - - int - 3 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pulpino_0 - interrupt_receiver - i2c_opencores_0 - interrupt_sender - - - - int - 4 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pulpino_0 - interrupt_receiver - i2c_opencores_1 - interrupt_sender - - - - int - 2 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - pulpino_0 - interrupt_receiver - epcq_controller2_0 - interrupt_sender - - int 0 @@ -12445,17 +13349,17 @@ parameters are a RESULT of the module parameters. --> true true - pulpino_0 + ibex_0 interrupt_receiver - timer_0 - irq + i2c_opencores_1 + interrupt_sender + version="24.1" + start="ibex_0.interrupt_receiver" + end="i2c_opencores_0.interrupt_sender"> int 1 @@ -12480,15 +13384,85 @@ parameters are a RESULT of the module parameters. --> true true - pulpino_0 + ibex_0 + interrupt_receiver + i2c_opencores_0 + interrupt_sender + + + + int + 2 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + ibex_0 interrupt_receiver jtag_uart_0 irq + + + int + 3 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + ibex_0 + interrupt_receiver + timer_0 + irq + @@ -12515,7 +13489,7 @@ parameters are a RESULT of the module parameters. --> @@ -12542,7 +13516,7 @@ parameters are a RESULT of the module parameters. --> @@ -12569,7 +13543,7 @@ parameters are a RESULT of the module parameters. --> @@ -12596,7 +13570,7 @@ parameters are a RESULT of the module parameters. --> @@ -12623,7 +13597,7 @@ parameters are a RESULT of the module parameters. --> @@ -12650,7 +13624,7 @@ parameters are a RESULT of the module parameters. --> @@ -12675,11 +13649,11 @@ parameters are a RESULT of the module parameters. --> reset + end="intel_generic_serial_flash_interface_top_0.reset"> java.lang.String UNKNOWN @@ -12698,13 +13672,13 @@ parameters are a RESULT of the module parameters. --> clk_27 clk_reset - epcq_controller2_0 + intel_generic_serial_flash_interface_top_0 reset @@ -12728,37 +13702,10 @@ parameters are a RESULT of the module parameters. --> onchip_memory2_0 reset1 - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_27 - clk_reset - pulpino_0 - reset_sink - @@ -12785,7 +13732,7 @@ parameters are a RESULT of the module parameters. --> @@ -12812,7 +13759,7 @@ parameters are a RESULT of the module parameters. --> @@ -12839,7 +13786,7 @@ parameters are a RESULT of the module parameters. --> @@ -12863,13 +13810,40 @@ parameters are a RESULT of the module parameters. --> pll_reconfig_0 reset_sink + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_27 + clk_reset + ibex_0 + reset_sink + 1 clock_source com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Clock Source - 23.1 + 24.1 1 @@ -12877,7 +13851,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Clock Input - 23.1 + 24.1 1 @@ -12885,7 +13859,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Reset Input - 23.1 + 24.1 1 @@ -12893,7 +13867,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Clock Output - 23.1 + 24.1 1 @@ -12901,47 +13875,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Reset Output - 23.1 - - - 1 - altera_epcq_controller2 - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Serial Flash Controller II Intel FPGA IP - 23.1 - - - 14 - avalon_slave - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Slave - 23.1 - - - 5 - interrupt_sender - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Sender - 23.1 - - - 14 - clock_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input - 23.1 - - - 14 - reset_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 23.1 + 24.1 1 @@ -12951,6 +13885,30 @@ parameters are a RESULT of the module parameters. --> hw_crc32 1.0 + + 14 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 24.1 + + + 14 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 24.1 + + + 16 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 24.1 + 2 i2c_opencores @@ -12965,23 +13923,31 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Conduit - 23.1 + 24.1 + + + 4 + interrupt_sender + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Sender + 24.1 1 - altera_avalon_jtag_uart + ibex com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - JTAG UART Intel FPGA IP - 23.1 + ibex + 1.0 1 - altera_jtag_avalon_master + interrupt_receiver com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - JTAG to Avalon Master Bridge - 23.1 + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Receiver + 24.1 3 @@ -12989,7 +13955,31 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Avalon Memory Mapped Master - 23.1 + 24.1 + + + 1 + intel_generic_serial_flash_interface_top + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Generic Serial Flash Interface Intel FPGA IP + 24.1 + + + 1 + altera_avalon_jtag_uart + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + JTAG UART Intel FPGA IP + 24.1 + + + 1 + altera_jtag_avalon_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + JTAG to Avalon Master Bridge + 24.1 1 @@ -12997,7 +13987,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint Reset Output - 23.1 + 24.1 1 @@ -13005,7 +13995,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule On-Chip Memory (RAM or ROM) Intel FPGA IP - 23.1 + 24.1 1 @@ -13021,7 +14011,7 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule PIO (Parallel I/O) Intel FPGA IP - 23.1 + 24.1 1 @@ -13031,22 +14021,6 @@ parameters are a RESULT of the module parameters. --> pll_reconfig 1.0 - - 1 - pulpino - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - pulpino - 1.0 - - - 1 - interrupt_receiver - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Receiver - 23.1 - 1 sc_config @@ -13061,15 +14035,15 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule Interval Timer Intel FPGA IP - 23.1 + 24.1 - 16 + 21 avalon com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Avalon Memory Mapped Connection - 23.1 + 24.1 14 @@ -13077,15 +14051,15 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Clock Connection - 23.1 + 24.1 - 5 + 4 interrupt com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Interrupt Connection - 23.1 + 24.1 14 @@ -13093,8 +14067,8 @@ parameters are a RESULT of the module parameters. --> com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection Reset Connection - 23.1 + 24.1 - 23.1 993 + 24.1 1077