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Release 0.67.

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- Code cleanup
- Some project files added
- PAL linetriple added
- FPGA PLL parameters optimized
- Reduced jitter on low video clock sources
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marqs committed 2016-03-27 23:09:31 +03:00
1 parent 388c464f63
commit f502b2e46c
30 files changed
+3680 -2691
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software/sys_controller_bsp/libhal_bsp.a
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software/sys_controller_bsp/settings.bsp
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@@ -2,10 +2,10 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Feb 18, 2016 1:07:07 AM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1455750427597</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>../sys_controller_bsp/settings.bsp</BspSettingsFile>
<BspGeneratedTimeStamp>Mar 22, 2016 7:43:08 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1458668588222</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>/home/markus/Code/ossc/software/sys_controller_bsp</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
<JdiFile>default</JdiFile>
<Cpu>nios2_qsys_0</Cpu>