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SD SPI implementation finished

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This commit is contained in:
marqs 2016-10-21 01:19:53 +03:00
parent 71d60144e8
commit f55e9a877e
46 changed files with 2349 additions and 3392 deletions
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6
ip/i2c_opencores/HAL/inc/i2c_opencores.h
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@ -9,15 +9,15 @@ extern "C"
{
#endif /* __cplusplus */
#define SCL_MIN_CLKDIV 10
void I2C_init(alt_u32 base,alt_u32 clk,alt_u32 speed);
int I2C_start(alt_u32 base, alt_u32 add, alt_u32 read);
alt_u32 I2C_read(alt_u32 base,alt_u32 last);
alt_u32 I2C_write(alt_u32 base,alt_u8 data, alt_u32 last);
alt_u32 SPI_read(alt_u32 base);
void SPI_write(alt_u32 base,alt_u8 data);
void SPI_read(alt_u32 base, alt_u8 *rdata, int len);
void SPI_write(alt_u32 base, alt_u8 *wdata, int len);
#define I2C_OK (0)
#define I2C_ACK (0)
#define I2C_NOACK (1)

38
ip/i2c_opencores/HAL/src/i2c_opencores.c
View File

@ -182,25 +182,31 @@ alt_u32 I2C_write(alt_u32 base,alt_u8 data, alt_u32 last)
}
alt_u32 SPI_read(alt_u32 base)
void SPI_read(alt_u32 base, alt_u8 *rdata, int len)
{
/* start read*/
IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_RD_MSK|I2C_OPENCORES_CR_NACK_MSK|I2C_OPENCORES_CR_SPIM_MSK );
int i;
/* wait for the trnasaction to be over.*/
while( IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK);
/* now read the data */
return (IORD_I2C_OPENCORES_RXR(base));
for (i=0; i<len; i++) {
/* start read*/
IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_RD_MSK|I2C_OPENCORES_CR_NACK_MSK|I2C_OPENCORES_CR_SPIM_MSK );
/* wait for the trnasaction to be over.*/
while( IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK);
/* now read the data */
if (rdata)
rdata[i] = IORD_I2C_OPENCORES_RXR(base);
}
}
void SPI_write(alt_u32 base,alt_u8 data) {
/* transmit the data*/
IOWR_I2C_OPENCORES_TXR(base, data);
void SPI_write(alt_u32 base, alt_u8 *wdata, int len)
{
int i;
/* start write */
IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_WR_MSK|I2C_OPENCORES_CR_NACK_MSK|I2C_OPENCORES_CR_SPIM_MSK );
/* wait for the trnasaction to be over.*/
while( IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK);
for (i=0; i<len; i++) {
/* transmit the data*/
IOWR_I2C_OPENCORES_TXR(base, wdata[i]);
/* start write */
IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_WR_MSK|I2C_OPENCORES_CR_NACK_MSK|I2C_OPENCORES_CR_SPIM_MSK );
/* wait for the trnasaction to be over.*/
while( IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK);
}
}

13
ip/i2c_opencores/i2c_master_bit_ctrl.v
View File

@ -129,7 +129,7 @@
module i2c_master_bit_ctrl(
clk, rst, nReset,
clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,
scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen
scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen, spi_miso
);
//
@ -164,6 +164,9 @@ module i2c_master_bit_ctrl(
output sda_oen; // i2c data line output enable (active low)
reg sda_oen;
// SPI MISO
input spi_miso;
reg spi_rden;
//
// variable declarations
@ -249,7 +252,7 @@ module i2c_master_bit_ctrl(
else
begin
sSCL <= #1 scl_i;
sSDA <= #1 sda_i;
sSDA <= #1 spi_rden ? spi_miso : sda_i;
dSCL <= #1 sSCL;
dSDA <= #1 sSDA;
@ -349,6 +352,7 @@ module i2c_master_bit_ctrl(
scl_oen <= #1 1'b1;
sda_oen <= #1 1'b1;
sda_chk <= #1 1'b0;
spi_rden <= #1 1'b0;
end
else if (rst | al)
begin
@ -357,6 +361,7 @@ module i2c_master_bit_ctrl(
scl_oen <= #1 1'b1;
sda_oen <= #1 1'b1;
sda_chk <= #1 1'b0;
spi_rden <= #1 1'b0;
end
else
begin
@ -546,6 +551,7 @@ module i2c_master_bit_ctrl(
scl_oen <= #1 1'b0; // set SCL low
sda_oen <= #1 1'b1; // tri-state SDA
sda_chk <= #1 1'b0; // don't check SDA output
spi_rden <= #1 1'b0; //clear SPI read enable
end
spi_rd_b:
@ -554,6 +560,7 @@ module i2c_master_bit_ctrl(
scl_oen <= #1 1'b0; // keep SCL low
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
spi_rden <= #1 1'b1; //set SPI read enable
end
spi_rd_c:
@ -562,6 +569,7 @@ module i2c_master_bit_ctrl(
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
spi_rden <= #1 1'b1; //set SPI read enable
end
spi_rd_d:
@ -571,6 +579,7 @@ module i2c_master_bit_ctrl(
scl_oen <= #1 1'b1; // tri-state SCL
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
spi_rden <= #1 1'b0; //clear SPI read enable
end
// write (last SPI bit)

7
ip/i2c_opencores/i2c_master_byte_ctrl.v
View File

@ -74,7 +74,7 @@
module i2c_master_byte_ctrl (
clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, spi_mode, din,
cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen, spi_miso );
//
// inputs & outputs
@ -112,6 +112,8 @@ module i2c_master_byte_ctrl (
output sda_o;
output sda_oen;
// SPI MISO
input spi_miso;
//
// Variable declarations
@ -164,7 +166,8 @@ module i2c_master_byte_ctrl (
.scl_oen ( scl_oen ),
.sda_i ( sda_i ),
.sda_o ( sda_o ),
.sda_oen ( sda_oen )
.sda_oen ( sda_oen ),
.spi_miso (spi_miso)
);
// generate go-signal

9
ip/i2c_opencores/i2c_master_top.v
View File

@ -75,7 +75,7 @@
module i2c_master_top(
wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o, spi_miso_pad_i );
// parameters
parameter ARST_LVL = 1'b0; // asynchronous reset level
@ -112,7 +112,9 @@ module i2c_master_top(
output sda_pad_o; // SDA-line output (always 1'b0)
output sda_padoen_o; // SDA-line output enable (active low)
// extra SPI MISO line
input spi_miso_pad_i;
//
// variable declarations
//
@ -253,7 +255,8 @@ module i2c_master_top(
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
.sda_oen ( sda_padoen_o ),
.spi_miso ( spi_miso_pad_i )
);
// status register block + interrupt request signal

11
ip/i2c_opencores/i2c_opencores.v
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@ -8,9 +8,10 @@ module i2c_opencores
(
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, /*wb_cyc_i,*/ wb_ack_o, wb_inta_o,
scl_pad_io, sda_pad_io
scl_pad_io, sda_pad_io, spi_miso_pad_i
);
parameter drive_scl_high = 0;
// Common bus signals
input wb_clk_i; // WISHBONE clock
@ -30,6 +31,9 @@ output wb_inta_o; // WISHBONE interrupt output
inout scl_pad_io; // I2C clock io
inout sda_pad_io; // I2C data io
// SPI MISO
input spi_miso_pad_i;
wire wb_cyc_i; // WISHBONE cycle input
// Wire tri-state scl/sda
wire scl_pad_i;
@ -39,7 +43,7 @@ wire scl_padoen_o;
assign wb_cyc_i = wb_stb_i;
assign scl_pad_i = scl_pad_io;
assign scl_pad_io = scl_padoen_o ? 1'bZ : scl_pad_o;
assign scl_pad_io = scl_padoen_o ? (drive_scl_high ? 1'b1 : 1'bZ) : scl_pad_o;
wire sda_pad_i;
wire sda_pad_o;
@ -66,7 +70,8 @@ i2c_master_top i2c_master_top_inst
.wb_ack_o(wb_ack_o), .wb_inta_o(wb_inta_o),
.scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_padoen_o(sda_padoen_o)
.sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_padoen_o(sda_padoen_o),
.spi_miso_pad_i(spi_miso_pad_i)
);
endmodule

9
ip/i2c_opencores/i2c_opencores_hw.tcl
View File

@ -59,7 +59,13 @@ add_fileset_file timescale.v VERILOG PATH timescale.v
#
# parameters
#
add_parameter drive_scl_high INTEGER 1
set_parameter_property drive_scl_high DEFAULT_VALUE 0
set_parameter_property drive_scl_high DISPLAY_NAME "Drive SCL high instead of tristate"
set_parameter_property drive_scl_high DISPLAY_HINT boolean
set_parameter_property drive_scl_high TYPE INTEGER
set_parameter_property drive_scl_high UNITS None
set_parameter_property drive_scl_high HDL_PARAMETER true
#
# display items
@ -109,6 +115,7 @@ set_interface_property export SVD_ADDRESS_GROUP ""
add_interface_port export scl_pad_io export Bidir 1
add_interface_port export sda_pad_io export Bidir 1
add_interface_port export spi_miso_pad_i export Input 1
#

4
ossc_sw_bsp.project
View File

@ -268,6 +268,7 @@
<Linker Options="" Required="yes"/>
<ResourceCompiler Options="" Required="no"/>
<General OutputFile="" IntermediateDirectory="./Debug" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
<BuildSystem Name="Default"/>
<Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
<![CDATA[]]>
</Environment>
@ -279,6 +280,7 @@
<PreBuild/>
<PostBuild/>
<CustomBuild Enabled="yes">
<Target Name="nios2-bsp-editor">nios2-bsp-editor</Target>
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>nios2-bsp-generate-files --bsp-dir . --settings settings.bsp</BuildCommand>
@ -306,6 +308,7 @@
<Linker Options="-O2" Required="yes"/>
<ResourceCompiler Options="" Required="no"/>
<General OutputFile="" IntermediateDirectory="./Release" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
<BuildSystem Name="Default"/>
<Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
<![CDATA[]]>
</Environment>
@ -317,6 +320,7 @@
<PreBuild/>
<PostBuild/>
<CustomBuild Enabled="yes">
<Target Name="nios2-bsp-editor">nios2-bsp-editor</Target>
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>nios2-bsp-generate-files --bsp-dir ./ --settings settings.bsp</BuildCommand>

38
rtl/ossc.v
View File

@ -79,8 +79,6 @@ wire VSYNC_out_videogen;
wire PCLK_out_videogen;
wire DATA_enable_videogen;
wire [7:0] lcd_ctrl;
reg [3:0] reset_n_ctr;
reg reset_n_reg = 1'b1;
@ -107,15 +105,16 @@ assign LED_R = videogen_sel ? 1'b0 : ((pll_lock_lost != 3'b000)|h_unstable);
assign LED_G = (ir_code == 0);
`endif
assign LCD_CS_N = lcd_ctrl[0];
assign LCD_RS = lcd_ctrl[1];
assign LCD_BL = sys_ctrl[1]; //reset_n in v1.2 PCB
assign SD_DAT[3] = sys_ctrl[7]; //SD_SPI_SS_N
assign LCD_CS_N = sys_ctrl[6];
assign LCD_RS = sys_ctrl[5];
assign LCD_BL = sys_ctrl[4]; //reset_n in v1.2 PCB
assign reset_n = sys_ctrl[0]; //HDMI_TX_RST_N in v1.2 PCB
`ifdef VIDEOGEN
wire videogen_sel;
assign videogen_sel = ~sys_ctrl[2];
assign videogen_sel = ~sys_ctrl[1];
assign HDMI_TX_RD = videogen_sel ? R_out_videogen : R_out;
assign HDMI_TX_GD = videogen_sel ? G_out_videogen : G_out;
assign HDMI_TX_BD = videogen_sel ? B_out_videogen : B_out;
@ -147,20 +146,19 @@ end
assign cpu_reset_n = reset_n_reg;
sys sys_inst(
.clk_clk (clk27),
.reset_reset_n (cpu_reset_n),
.i2c_opencores_0_export_scl_pad_io (scl),
.i2c_opencores_0_export_sda_pad_io (sda),
.spi_0_external_MISO (SD_DAT[0]),
.spi_0_external_MOSI (SD_CMD),
.spi_0_external_SCLK (SD_CLK),
.spi_0_external_SS_n (SD_DAT[3]),
.pio_0_sys_ctrl_out_export (sys_ctrl),
.pio_1_controls_in_export ({ir_code_cnt, 5'b00000, HDMI_TX_MODE, btn, ir_code}),
.pio_2_horizontal_info_out_export (h_info),
.pio_3_vertical_info_out_export (v_info),
.pio_4_linecount_in_export ({VSYNC_out, 13'h0000, fpga_vsyncgen, 5'h00, lines_out}),
.pio_5_lcd_ctrl_out_export (lcd_ctrl)
.clk_clk (clk27),
.reset_reset_n (cpu_reset_n),
.i2c_opencores_0_export_scl_pad_io (scl),
.i2c_opencores_0_export_sda_pad_io (sda),
.i2c_opencores_0_export_spi_miso_pad_i (1'b0),
.i2c_opencores_1_export_scl_pad_io (SD_CLK),
.i2c_opencores_1_export_sda_pad_io (SD_CMD),
.i2c_opencores_1_export_spi_miso_pad_i (SD_DAT[0]),
.pio_0_sys_ctrl_out_export (sys_ctrl),
.pio_1_controls_in_export ({ir_code_cnt, 5'b00000, HDMI_TX_MODE, btn, ir_code}),
.pio_2_horizontal_info_out_export (h_info),
.pio_3_vertical_info_out_export (v_info),
.pio_4_linecount_in_export ({VSYNC_out, 13'h0000, fpga_vsyncgen, 5'h00, lines_out})
);
scanconverter scanconverter_inst (

3
software/sys_controller/Makefile
View File

@ -160,6 +160,8 @@ C_SRCS += ossc/controls.c
C_SRCS += ossc/firmware.c
C_SRCS += ossc/menu.c
C_SRCS += ossc/userdata.c
C_SRCS += ulibSD/sd_io.c
C_SRCS += ulibSD/spi_io.c
CXX_SRCS :=
ASM_SRCS :=
@ -202,6 +204,7 @@ APP_INCLUDE_DIRS += tvp7002
APP_INCLUDE_DIRS += ths7353
APP_INCLUDE_DIRS += spi_charlcd
APP_INCLUDE_DIRS += memory
APP_INCLUDE_DIRS += ulibSD
APP_INCLUDE_DIRS += ossc
APP_LIBRARY_DIRS :=
APP_LIBRARY_NAMES :=

1
software/sys_controller/it6613/it6613.c
View File

@ -1,6 +1,5 @@
#include <stdio.h>
#include <unistd.h>
#include "sysconfig.h"
#include "system.h"
#include "i2c_opencores.h"
#include "it6613.h"

4
software/sys_controller/it6613/it6613.h
View File

@ -1,9 +1,7 @@
#ifndef IT6613_H_
#define IT6613_H_
//#define I2C_DEBUG
//#define I2CA_HDMI_BASE I2C_OPENCORES_1_BASE
#define I2CA_BASE I2C_OPENCORES_0_BASE
#include "sysconfig.h"
#define IT6613_VENDORID 0xCA
#define IT6613_DEVICEID 0x13

1962
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
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File diff suppressed because it is too large Load Diff

3
software/sys_controller/memory/flash.c
View File

@ -36,7 +36,8 @@ int check_flash()
if ((epcq_controller_dev == NULL) || !(epcq_controller_dev->is_epcs && (epcq_controller_dev->page_size == PAGESIZE)))
return -1;
//printf("Flash size in bytes: %d\nSector size: %d (%d pages)\nPage size: %d\n", epcq_controller_dev->size_in_bytes, epcq_controller_dev->sector_size, epcq_controller_dev->sector_size/epcq_controller_dev->page_size, epcq_controller_dev->page_size);
printf("Flash size in bytes: %d\nSector size: %d (%d pages)\nPage size: %d\n",
epcq_controller_dev->size_in_bytes, epcq_controller_dev->sector_size, epcq_controller_dev->sector_size/epcq_controller_dev->page_size, epcq_controller_dev->page_size);
return 0;
}

38
software/sys_controller/memory/sdcard.c
View File

@ -23,45 +23,19 @@
extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
alt_up_sd_card_dev *sdcard_dev;
int read_sd_block(alt_u32 offset, alt_u32 size, alt_u8 *dstbuf)
{
/*int i;
alt_u32 tmp;
if ((offset % SD_BUFFER_SIZE) || (size > 512)) {
sniprintf(menu_row1, LCD_ROW_LEN+1, "Invalid read cmd");
menu_row2[0] = '\0';
return -1;
}
if (!Read_Sector_Data((offset/SD_BUFFER_SIZE), 0)) {
sniprintf(menu_row1, LCD_ROW_LEN+1, "SD read failure");
menu_row2[0] = '\0';
return -2;
}
// Copy buffer to SW
for (i=0; i<size; i=i+4) {
tmp = IORD_32DIRECT(sdcard_dev->base, i);
*((alt_u32*)(dstbuf+i)) = tmp;
}
*/
return 0;
}
SD_DEV sdcard_dev;
int check_sdcard(alt_u8 *databuf)
{
/* sdcard_dev = alt_up_sd_card_open_dev(ALTERA_UP_SD_CARD_AVALON_INTERFACE_0_NAME);
SDRESULTS res;
if ((sdcard_dev == NULL) || !alt_up_sd_card_is_Present()) {
res = SD_Init(&sdcard_dev);
printf("SD det status: %u\n", res);
if (res) {
sniprintf(menu_row1, LCD_ROW_LEN+1, "No SD card det.");
menu_row2[0] = '\0';
return 1;
}
return read_sd_block(0, 512, databuf);*/
return 0;
return SD_Read(&sdcard_dev, databuf, 0, 0, 512);
}

7
software/sys_controller/memory/sdcard.h
View File

@ -22,12 +22,7 @@
#include "alt_types.h"
#include "sysconfig.h"
#include "Altera_UP_SD_Card_Avalon_Interface_mod.h"
// SD controller uses 512-byte chunks
#define SD_BUFFER_SIZE 512
int read_sd_block(alt_u32 offset, alt_u32 size, alt_u8 *dstbuf);
#include "sd_io.h"
int check_sdcard(alt_u8 *databuf);

21
software/sys_controller/ossc/av_controller.c
View File

@ -32,13 +32,13 @@
#include "sdcard.h"
#include "menu.h"
#include "avconfig.h"
#include "sysconfig.h"
#include "firmware.h"
#include "userdata.h"
#include "it6613.h"
#include "it6613_sys.h"
#include "HDMI_TX.h"
#include "hdmitx.h"
#include "sd_io.h"
#define STABLE_THOLD 1
#define MIN_LINES_PROGRESSIVE 200
@ -47,6 +47,8 @@
#define SYNC_LOSS_THOLD -5
#define STATUS_TIMEOUT 10000
alt_u8 sys_ctrl;
// Current mode
avmode_t cm;
@ -101,7 +103,7 @@ inline void TX_enable(tx_mode_t mode)
void set_lpf(alt_u8 lpf)
{
alt_u32 pclk;
pclk = (clkrate[REFCLK_EXT27]/cm.clkcnt)*video_modes[cm.id].h_total;
pclk = (TVP_EXTCLK_HZ/cm.clkcnt)*video_modes[cm.id].h_total;
printf("PCLK_in: %luHz\n", pclk);
//Auto
@ -353,8 +355,8 @@ void program_mode()
stable_frames = STABLE_THOLD;
if ((cm.clkcnt != 0) && (cm.totlines != 0)) { //prevent div by 0
h_hz = clkrate[REFCLK_EXT27]/cm.clkcnt;
v_hz_x100 = cm.progressive ? ((100*clkrate[REFCLK_EXT27])/cm.totlines)/cm.clkcnt : (2*((100*clkrate[REFCLK_EXT27])/cm.totlines))/cm.clkcnt;
h_hz = TVP_EXTCLK_HZ/cm.clkcnt;
v_hz_x100 = cm.progressive ? ((100*TVP_EXTCLK_HZ)/cm.totlines)/cm.clkcnt : (2*((100*TVP_EXTCLK_HZ)/cm.totlines))/cm.clkcnt;
} else {
h_hz = 15700;
v_hz_x100 = 6000;
@ -440,15 +442,16 @@ int init_hw()
{
alt_u32 chiprev;
// Reset error vector and scan converter
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x03);
// Reset hardware
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, AV_RESET_N|LCD_BL);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x00);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, 0x00000000);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, 0x00000000);
usleep(10000);
// unreset hw
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x03);
sys_ctrl = AV_RESET_N|LCD_BL|SD_SPI_SS_N|LCD_CS_N;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
//wait >500ms for SD card interface to be stable
//over 200ms and LCD may be buggy?
@ -456,6 +459,7 @@ int init_hw()
// IT6613 officially supports only 100kHz, but 400kHz seems to work
I2C_init(I2CA_BASE,ALT_CPU_FREQ,400000);
//I2C_init(I2C_OPENCORES_1_BASE,ALT_CPU_FREQ,400000);
/* Initialize the character display */
lcd_init();
@ -657,7 +661,8 @@ int main()
case ACTIVITY_CHANGE:
if (cm.sync_active) {
printf("Sync up\n");
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, (IORD_ALTERA_AVALON_PIO_DATA(PIO_0_BASE) | (1<<2))); //disable videogen
sys_ctrl |= VIDGEN_OFF;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
enable_outputs();
} else {
printf("Sync lost\n");

9
software/sys_controller/ossc/av_controller.h
View File

@ -21,9 +21,18 @@
#define AV_CONTROLLER_H_
#include "avconfig.h"
#include "sysconfig.h"
#define HDMITX_MODE_MASK 0x00040000
//sys_ctrl bits
#define SD_SPI_SS_N (1<<7)
#define LCD_CS_N (1<<6)
#define LCD_RS (1<<5)
#define LCD_BL (1<<4)
#define VIDGEN_OFF (1<<1)
#define AV_RESET_N (1<<0)
static const char *avinput_str[] = { "Test pattern", "AV1: RGBS", "AV1: RGsB", "AV1: YPbPr", "AV2: YPbPr", "AV2: RGsB", "AV3: RGBHV", "AV3: RGBS", "AV3: RGsB", "AV3: YPbPr" };
typedef enum {

6
software/sys_controller/ossc/controls.c
View File

@ -20,7 +20,6 @@
#include <string.h>
#include <unistd.h>
#include "alt_types.h"
#include "sysconfig.h"
#include "controls.h"
#include "menu.h"
#include "av_controller.h"
@ -37,6 +36,7 @@ extern avmode_t cm;
extern avconfig_t tc;
extern avinput_t target_mode;
extern alt_u8 menu_active;
extern alt_u8 sys_ctrl;
alt_u32 remote_code;
alt_u8 remote_rpt, remote_rpt_prev;
@ -71,7 +71,6 @@ void setup_rc()
confirm = 0;
}
}
}
remote_code_prev = remote_code;
@ -128,7 +127,8 @@ void parse_control()
printf("Lines: %u M: %u\n", IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) & 0xffff, cm.macrovis);
break;
case RC_LCDBL:
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, (IORD_ALTERA_AVALON_PIO_DATA(PIO_0_BASE) ^ (1<<1)));
sys_ctrl ^= LCD_BL;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
break;
case RC_SL_MODE: tc.sl_mode = (tc.sl_mode < SL_MODE_MAX) ? (tc.sl_mode + 1) : 0; break;
case RC_SL_TYPE: tc.sl_type = (tc.sl_type < SL_TYPE_MAX) ? (tc.sl_type + 1) : 0; break;

2
software/sys_controller/ossc/controls.h
View File

@ -20,6 +20,8 @@
#ifndef CONTROLS_H_
#define CONTROLS_H_
#include "sysconfig.h"
#define RC_MASK 0x0000ffff
#define PB_MASK 0x00030000
#define PB0_BIT 0x00010000

31
software/sys_controller/ossc/firmware.c
View File

@ -22,7 +22,6 @@
#include "firmware.h"
#include "sdcard.h"
#include "flash.h"
#include "sysconfig.h"
#include "controls.h"
#include "tvp7002.h"
#include "av_controller.h"
@ -32,6 +31,8 @@
extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
extern alt_u16 rc_keymap[REMOTE_MAX_KEYS];
extern SD_DEV sdcard_dev;
extern alt_u8 sys_ctrl;
static int check_fw_header(alt_u8 *databuf, fw_hdr *hdr)
{
@ -81,9 +82,11 @@ static int check_fw_image(alt_u32 offset, alt_u32 size, alt_u32 golden_crc, alt_
alt_u32 crcval=0, i, bytes_to_read;
int retval;
for (i=0; i<size; i=i+SD_BUFFER_SIZE) {
bytes_to_read = ((size-i < SD_BUFFER_SIZE) ? (size-i) : SD_BUFFER_SIZE);
retval = read_sd_block(offset+i, bytes_to_read, tmpbuf);
for (i=0; i<size; i=i+SD_BLK_SIZE) {
bytes_to_read = ((size-i < SD_BLK_SIZE) ? (size-i) : SD_BLK_SIZE);
retval = SD_Read(&sdcard_dev, tmpbuf, (offset+i)/SD_BLK_SIZE, 0, bytes_to_read);
//retval = read_sd_block(offset+i, bytes_to_read, tmpbuf);
if (retval != 0)
return -2;
@ -112,12 +115,13 @@ int fw_update()
{
int retval, i;
int retries = FW_UPDATE_RETRIES;
alt_u8 databuf[SD_BUFFER_SIZE];
alt_u8 databuf[SD_BLK_SIZE];
alt_u32 btn_vec;
alt_u32 bytes_to_rw;
fw_hdr fw_header;
retval = check_sdcard(databuf);
SPI_CS_High();
if (retval != 0)
goto failure;
@ -143,7 +147,8 @@ int fw_update()
break;
} else if (btn_vec == rc_keymap[RC_BTN2]) {
retval = 2;
return 1;
strncpy(menu_row1, "Cancelled", LCD_ROW_LEN+1);
goto failure;
}
usleep(WAITLOOP_SLEEP_US);
@ -151,7 +156,8 @@ int fw_update()
//disable video output
tvp_disable_output();
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, (IORD_ALTERA_AVALON_PIO_DATA(PIO_0_BASE) | (1<<2)));
sys_ctrl |= VIDGEN_OFF;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
usleep(10000);
strncpy(menu_row1, "Updating FW", LCD_ROW_LEN+1);
@ -159,11 +165,11 @@ update_init:
strncpy(menu_row2, "please wait...", LCD_ROW_LEN+1);
lcd_write_menu();
for (i=0; i<fw_header.data_len; i=i+SD_BUFFER_SIZE) {
bytes_to_rw = ((fw_header.data_len-i < SD_BUFFER_SIZE) ? (fw_header.data_len-i) : SD_BUFFER_SIZE);
retval = read_sd_block(512+i, bytes_to_rw, databuf);
for (i=0; i<fw_header.data_len; i=i+SD_BLK_SIZE) {
bytes_to_rw = ((fw_header.data_len-i < SD_BLK_SIZE) ? (fw_header.data_len-i) : SD_BLK_SIZE);
retval = SD_Read(&sdcard_dev, databuf, (512+i)/SD_BLK_SIZE, 0, bytes_to_rw);
if (retval != 0)
return -200;
goto failure;
retval = write_flash_page(databuf, ((bytes_to_rw < PAGESIZE) ? bytes_to_rw : PAGESIZE), (i/PAGESIZE));
if (retval != 0)
@ -183,10 +189,11 @@ update_init:
if (retval != 0)
goto failure;
SPI_CS_High();
return 0;
failure:
SPI_CS_High();
lcd_write_menu();
usleep(1000000);

1
software/sys_controller/ossc/firmware.h
View File

@ -21,6 +21,7 @@
#define FIRMWARE_H_
#include "alt_types.h"
#include "sysconfig.h"
#define FW_VER_MAJOR 0
#define FW_VER_MINOR 74

14
software/sys_controller/ossc/menu.c
View File

@ -50,8 +50,8 @@ static const char *sl_id_desc[] = { "Top", "Bottom" };
static void sampler_phase_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%d deg", (v*1125)/100); }
static void sync_vth_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%d mV", (v*1127)/100); }
static void intclks_to_time_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u.%.2u us", (unsigned)(((1000000U*v)/(clkrate[REFCLK_INTCLK]/1000))/1000), (unsigned)((((1000000U*v)/(clkrate[REFCLK_INTCLK]/1000))%1000)/10)); }
static void extclks_to_time_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u.%.2u us", (unsigned)(((1000000U*v)/(clkrate[REFCLK_EXT27]/1000))/1000), (unsigned)((((1000000U*v)/(clkrate[REFCLK_EXT27]/1000))%1000)/10)); }
static void intclks_to_time_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u.%.2u us", (unsigned)(((1000000U*v)/(TVP_INTCLK_HZ/1000))/1000), (unsigned)((((1000000U*v)/(TVP_INTCLK_HZ/1000))%1000)/10)); }
static void extclks_to_time_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u.%.2u us", (unsigned)(((1000000U*v)/(TVP_EXTCLK_HZ/1000))/1000), (unsigned)((((1000000U*v)/(TVP_EXTCLK_HZ/1000))%1000)/10)); }
static void sl_str_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u%%", ((v+1)*625)/100); }
static void lines_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u lines", v); }
static void pixels_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u pixels", v); }
@ -118,9 +118,9 @@ MENU(menu_main, P99_PROTECT({ \
{ "Sync opt. >", OPT_SUBMENU, { .sub = { &menu_sync, NULL } } },
{ "Output opt. >", OPT_SUBMENU, { .sub = { &menu_output, NULL } } },
{ "Post-proc. >", OPT_SUBMENU, { .sub = { &menu_postproc, NULL } } },
{ "<Fw. update >", OPT_FUNC_CALL, { .fun = { fw_update, "OK - pls restart" } } },
{ "<Reset settings>", OPT_FUNC_CALL, { .fun = { set_default_avconfig, "Reset done" } } },
{ "<Save settings >", OPT_FUNC_CALL, { .fun = { write_userdata, "Saved" } } },
{ "<Fw. update >", OPT_FUNC_CALL, { .fun = { fw_update, "OK - pls restart", "failed" } } },
{ "<Reset settings>", OPT_FUNC_CALL, { .fun = { set_default_avconfig, "Reset done", "" } } },
{ "<Save settings >", OPT_FUNC_CALL, { .fun = { write_userdata, "Saved", "failed" } } },
}))
// Max 3 levels currently
@ -237,9 +237,9 @@ void display_menu(alt_u8 forcedisp)
break;
case OPT_FUNC_CALL:
if (code == OPT_SELECT)
sniprintf(menu_row2, LCD_ROW_LEN+1, "%s", (retval==0) ? navi[navlvl].m->items[navi[navlvl].mp].fun.text_success : "failed");
sniprintf(menu_row2, LCD_ROW_LEN+1, "%s", (retval==0) ? navi[navlvl].m->items[navi[navlvl].mp].fun.text_success : navi[navlvl].m->items[navi[navlvl].mp].fun.text_failure);
else
menu_row2[0] = 0;
menu_row2[0] = 0;
break;
default:
break;

1
software/sys_controller/ossc/menu.h
View File

@ -62,6 +62,7 @@ typedef struct {
typedef struct {
func_call f;
char *text_success;
char *text_failure;
} opt_func_call;
typedef struct menustruct menu_t;

4
software/sys_controller/ossc/sysconfig.h
View File

@ -20,6 +20,10 @@
#ifndef SYSCONFIG_H_
#define SYSCONFIG_H_
//#define I2C_DEBUG
#define I2CA_BASE I2C_OPENCORES_0_BASE
#define SD_SPI_BASE I2C_OPENCORES_1_BASE
#ifndef DEBUG
#define OS_PRINTF(...)
#define ErrorF(...)

1
software/sys_controller/ossc/userdata.c
View File

@ -19,7 +19,6 @@
#include <string.h>
#include "userdata.h"
#include "sysconfig.h"
#include "flash.h"
#include "firmware.h"
#include "controls.h"

1
software/sys_controller/ossc/userdata.h
View File

@ -21,6 +21,7 @@
#define USERDATA_H_
#include "alt_types.h"
#include "sysconfig.h"
#define USERDATA_HDR_SIZE 11
typedef struct {

84
software/sys_controller/spi_charlcd/lcd.c
View File

@ -23,6 +23,7 @@
#include "alt_types.h"
#include "altera_avalon_pio_regs.h"
#include "i2c_opencores.h"
#include "av_controller.h"
#define LCD_CMD 0x00
#define LCD_DATA 0x40
@ -30,50 +31,46 @@
#define WRDELAY 20
#define CLEARDELAY 800
extern alt_u8 sys_ctrl;
static void lcd_cmd(alt_u8 cmd, alt_u16 postdelay) {
SPI_write(I2CA_BASE, &cmd, 1);
usleep(postdelay);
}
void lcd_init()
{
alt_u8 lcd_ctrl = 0x00;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
sys_ctrl &= ~(LCD_CS_N|LCD_RS);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x38); // function set
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x39); // function set, select extended table (IS=1)
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x14); // osc freq
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x71); // contrast set
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x5E); // power/icon/cont
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x6D); // follower control
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x0C); // display on
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x01); // clear display
usleep(CLEARDELAY);
SPI_write(I2CA_BASE, 0x06); // entry mode set
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x02); // return home
usleep(CLEARDELAY);
lcd_cmd(0x38,WRDELAY); // function set
lcd_cmd(0x39,WRDELAY); // function set, select extended table (IS=1)
lcd_cmd(0x14,WRDELAY); // osc freq
lcd_cmd(0x71,WRDELAY); // contrast set
lcd_cmd(0x5E,WRDELAY); // power/icon/cont
lcd_cmd(0x6D,WRDELAY); // follower control
lcd_cmd(0x0C,WRDELAY); // display on
lcd_cmd(0x01,CLEARDELAY); // clear display
lcd_cmd(0x06,WRDELAY); // entry mode set
lcd_cmd(0x02,CLEARDELAY); // return home
lcd_ctrl |= LCD_CS_N;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
sys_ctrl |= LCD_CS_N;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
}
void lcd_write(char *row1, char *row2)
{
alt_u8 i, rowlen;
alt_u8 lcd_ctrl = 0x00;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
sys_ctrl &= ~(LCD_CS_N|LCD_RS);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
SPI_write(I2CA_BASE, 0x01); // clear display
usleep(CLEARDELAY);
lcd_cmd(0x01,CLEARDELAY); // clear display
// Set RS to enter data write mode
lcd_ctrl |= LCD_RS;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
sys_ctrl |= LCD_RS;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
//ensure no empty row
rowlen = strnlen(row1, LCD_ROW_LEN);
@ -82,19 +79,16 @@ void lcd_write(char *row1, char *row2)
rowlen++;
}
for (i=0; i<rowlen; i++) {
SPI_write(I2CA_BASE, row1[i]);
usleep(WRDELAY);
}
for (i=0; i<rowlen; i++)
lcd_cmd(row1[i],WRDELAY);
// second row
lcd_ctrl &= ~LCD_RS;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
SPI_write(I2CA_BASE, (1<<7)|0x40);
usleep(WRDELAY);
sys_ctrl &= ~LCD_RS;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
lcd_cmd((1<<7)|0x40,WRDELAY);
lcd_ctrl |= LCD_RS;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
sys_ctrl |= LCD_RS;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
//ensure no empty row
rowlen = strnlen(row2, LCD_ROW_LEN);
@ -103,11 +97,9 @@ void lcd_write(char *row1, char *row2)
rowlen++;
}
for (i=0; i<rowlen; i++) {
SPI_write(I2CA_BASE, row2[i]);
usleep(WRDELAY);
}
for (i=0; i<rowlen; i++)
lcd_cmd(row2[i],WRDELAY);
lcd_ctrl |= LCD_CS_N;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
sys_ctrl |= LCD_CS_N;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
}

6
software/sys_controller/spi_charlcd/lcd.h
View File

@ -26,12 +26,6 @@
#define LCD_ROW_LEN 16
//#define I2C_DEBUG
#define I2CA_BASE I2C_OPENCORES_0_BASE
#define LCD_CS_N (1<<0)
#define LCD_RS (1<<1)
void lcd_init();
void lcd_write(char *row1, char *row2);

3
software/sys_controller/ths7353/ths7353.h
View File

@ -51,9 +51,6 @@ typedef enum {
#define THS_LPF_BYPASS 0x03
//#define I2C_DEBUG
#define I2CA_BASE I2C_OPENCORES_0_BASE
int ths_init();
void ths_set_lpf(alt_u8 val);

9
software/sys_controller/tvp7002/tvp7002.c
View File

@ -38,6 +38,9 @@ const ypbpr_to_rgb_csc_t csc_coeffs[] = {
{ "Rec. 709", 0x2000, 0x0000, 0x323E, 0x2000, 0xFA04, 0xF113, 0x2000, 0x3B61, 0x0000 }, // eq. 105
};
static const alt_u8 Kvco[] = {75, 85, 150, 200};
static const char *Kvco_str[] = { "Ultra low", "Low", "Medium", "High" };
extern mode_data_t video_modes[];
static void tvp_set_clamp(video_format fmt)
@ -95,11 +98,11 @@ inline void tvp_writereg(alt_u32 regaddr, alt_u8 data)
inline void tvp_reset()
{
usleep(10000);
/*usleep(10000);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x00);
usleep(10000);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x01);
usleep(10000);
usleep(10000);*/
}
inline void tvp_disable_output()
@ -241,7 +244,7 @@ void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 v_lines, alt_u8 hz, alt_u8 pll
tvp_writereg(TVP_HPLLCTRL, ((vco_range << 6) | (cp_current << 3)));
}
void tvp_sel_clk(alt_u8 refclk)
void tvp_sel_clk(tvp_refclk_t refclk)
{
alt_u8 status = tvp_readreg(TVP_INPMUX2) & 0xFA;

13
software/sys_controller/tvp7002/tvp7002.h
View File

@ -24,21 +24,18 @@
#include "video_modes.h"
#include "sysconfig.h"
//#define I2C_DEBUG
#define I2CA_BASE I2C_OPENCORES_0_BASE
#define DEFAULT_VSYNC_THOLD 0x44
#define DEFAULT_LINELEN_TOL 0x06
#define TVP_INTCLK_HZ 6500000UL
#define TVP_EXTCLK_HZ 27000000UL
typedef enum {
TVP_INPUT1 = 0,
TVP_INPUT2 = 1,
TVP_INPUT3 = 2
} tvp_input_t;
static const alt_u8 Kvco[] = {75, 85, 150, 200};
static const char *Kvco_str[] = { "Ultra low", "Low", "Medium", "High" };
typedef enum {
REFCLK_EXT27 = 0,
REFCLK_INTCLK = 1
@ -66,8 +63,6 @@ typedef struct {
alt_u8 b_f_gain;
} __attribute__((packed)) color_setup_t;
static const alt_u32 clkrate[] = {27000000, 6500000}; //in MHz
inline alt_u32 tvp_readreg(alt_u32 regaddr);
@ -91,7 +86,7 @@ void tvp_set_fine_gain_offset(color_setup_t *col);
void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 v_lines, alt_u8 hz, alt_u8 plldivby2);
void tvp_sel_clk(alt_u8 refclk);
void tvp_sel_clk(tvp_refclk_t refclk);
void tvp_sel_csc(const ypbpr_to_rgb_csc_t *csc);

5
software/sys_controller/ulibSD/integer.h
View File

@ -13,7 +13,8 @@
#define _INTEGER_H_
#include <stdint.h>
#include <typedef.h>
#if 0
/* 16-bit, 32-bit or larger integer */
typedef int16_t INT;
typedef uint16_t UINT;
@ -37,8 +38,8 @@ typedef uint32_t DWORD;
/* Boolean type */
typedef enum { FALSE = 0, TRUE } BOOLEAN;
#endif
typedef enum { LOW = 0, HIGH } THROTTLE;
#endif
// «integer.h» is part of:

165
software/sys_controller/ulibSD/sd_io.c
View File

@ -109,6 +109,7 @@ void __SD_Speed_Transfer(BYTE throttle) {
BYTE __SD_Send_Cmd(BYTE cmd, DWORD arg)
{
BYTE wiredata[10];
BYTE crc, res;
// ACMD«n» is the command sequense of CMD55-CMD«n»
if(cmd & 0x80) {
@ -118,29 +119,29 @@ BYTE __SD_Send_Cmd(BYTE cmd, DWORD arg)
}
// Select the card
__SD_Deassert();
SPI_RW(0xFF);
__SD_Assert();
SPI_RW(0xFF);
// Send complete command set
SPI_RW(cmd); // Start and command index
SPI_RW((BYTE)(arg >> 24)); // Arg[31-24]
SPI_RW((BYTE)(arg >> 16)); // Arg[23-16]
SPI_RW((BYTE)(arg >> 8 )); // Arg[15-08]
SPI_RW((BYTE)(arg >> 0 )); // Arg[07-00]
wiredata[0] = cmd; // Start and command index
wiredata[1] = (arg >> 24); // Arg[31-24]
wiredata[2] = (arg >> 16); // Arg[23-16]
wiredata[3] = (arg >> 8 ); // Arg[15-08]
wiredata[4] = (arg >> 0 ); // Arg[07-00]
// CRC?
crc = 0x01; // Dummy CRC and stop
if(cmd == CMD0) crc = 0x95; // Valid CRC for CMD0(0)
if(cmd == CMD8) crc = 0x87; // Valid CRC for CMD8(0x1AA)
SPI_RW(crc);
wiredata[5] = crc;
SPI_W(wiredata, 6);
// Receive command response
// Wait for a valid response in timeout of 5 milliseconds
SPI_Timer_On(5);
do {
res = SPI_RW(0xFF);
SPI_R(&res, 1);
} while((res & 0x80)&&(SPI_Timer_Status()==TRUE));
SPI_Timer_Off();
// Return with the response value
@ -185,8 +186,8 @@ SDRESULTS __SD_Write_Block(SD_DEV *dev, void *dat, BYTE token)
DWORD __SD_Sectors (SD_DEV *dev)
{
BYTE csd[16];
BYTE idx;
BYTE csd[18];
BYTE tkn;
DWORD ss = 0;
WORD C_SIZE = 0;
BYTE C_SIZE_MULT = 0;
@ -194,12 +195,18 @@ DWORD __SD_Sectors (SD_DEV *dev)
if(__SD_Send_Cmd(CMD9, 0)==0)
{
// Wait for response
while (SPI_RW(0xFF) == 0xFF);
for (idx=0; idx!=16; idx++) csd[idx] = SPI_RW(0xFF);
// Dummy CRC
SPI_RW(0xFF);
SPI_RW(0xFF);
SPI_Release();
SPI_Timer_On(5); // Wait for data packet (timeout of 5ms)
do {
SPI_R(&tkn, 1);
} while((tkn==0xFF)&&(SPI_Timer_Status()==TRUE));
SPI_Timer_Off();
if(tkn!=0xFE)
return 0;
// TODO: CRC check
SPI_R(csd, 18);
if(dev->cardtype & SDCT_SD1)
{
ss = csd[0];
@ -225,12 +232,15 @@ DWORD __SD_Sectors (SD_DEV *dev)
C_SIZE <<= 8;
C_SIZE |= (csd[9] & 0xFF);
// C_SIZE_MULT [--]. don't exits
C_SIZE_MULT = 0;
C_SIZE_MULT = 17; //C_SIZE_MULT+2 = 19
printf("csize: %u\n", C_SIZE);
}
ss = (C_SIZE + 1);
ss *= __SD_Power_Of_Two(C_SIZE_MULT + 2);
ss *= __SD_Power_Of_Two(READ_BL_LEN);
ss /= SD_BLK_SIZE;
// SD_BLK_SIZE = 2^9
//ss *= __SD_Power_Of_Two(C_SIZE_MULT + 2 + READ_BL_LEN - 9);
ss *= 1 << (C_SIZE_MULT + 2 + READ_BL_LEN - 9);
//ss /= SD_BLK_SIZE;
printf("ss: %u\n", ss);
return (ss);
} else return (0); // Error
}
@ -242,6 +252,7 @@ DWORD __SD_Sectors (SD_DEV *dev)
SDRESULTS SD_Init(SD_DEV *dev)
{
BYTE initdata[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
#if defined(_M_IX86) // x86
dev->fp = fopen(dev->fn, "r+");
if (dev->fp == NULL)
@ -265,67 +276,68 @@ SDRESULTS SD_Init(SD_DEV *dev)
// Initialize SPI for use with the memory card
SPI_Init();
SPI_CS_High();
__SD_Deassert();
SPI_Freq_Low();
// 80 dummy clocks
for(idx = 0; idx != 10; idx++) SPI_RW(0xFF);
//for(idx = 0; idx != 10; idx++) SPI_RW(0xFF);
SPI_W(initdata, sizeof(initdata));
SPI_Timer_On(500);
/*SPI_Timer_On(500);
while(SPI_Timer_Status()==TRUE);
SPI_Timer_Off();
SPI_Timer_Off();*/
dev->mount = FALSE;
SPI_Timer_On(500);
while ((__SD_Send_Cmd(CMD0, 0) != 1)&&(SPI_Timer_Status()==TRUE));
SPI_Timer_Off();
// Idle state
if (__SD_Send_Cmd(CMD0, 0) == 1) {
// SD version 2?
if (__SD_Send_Cmd(CMD8, 0x1AA) == 1) {
// Get trailing return value of R7 resp
for (n = 0; n < 4; n++) ocr[n] = SPI_RW(0xFF);
// VDD range of 2.7-3.6V is OK?
if ((ocr[2] == 0x01)&&(ocr[3] == 0xAA))
{
// Wait for leaving idle state (ACMD41 with HCS bit)...
SPI_Timer_On(1000);
while ((SPI_Timer_Status()==TRUE)&&(__SD_Send_Cmd(ACMD41, 1UL << 30)));
SPI_Timer_Off();
// CCS in the OCR?
if ((SPI_Timer_Status()==TRUE)&&(__SD_Send_Cmd(CMD58, 0) == 0))
{
for (n = 0; n < 4; n++) ocr[n] = SPI_RW(0xFF);
// SD version 2?
ct = (ocr[0] & 0x40) ? SDCT_SD2 | SDCT_BLOCK : SDCT_SD2;
}
}
} else {
// SD version 1 or MMC?
if (__SD_Send_Cmd(ACMD41, 0) <= 1)
{
// SD version 1
ct = SDCT_SD1;
cmd = ACMD41;
} else {
// MMC version 3
ct = SDCT_MMC;
cmd = CMD1;
}
// Wait for leaving idle state
SPI_Timer_On(250);
while((SPI_Timer_Status()==TRUE)&&(__SD_Send_Cmd(cmd, 0)));
// SD version 2?
if (__SD_Send_Cmd(CMD8, 0x1AA) == 1) {
// Get trailing return value of R7 resp
SPI_R(ocr, 4);
// VDD range of 2.7-3.6V is OK?
if ((ocr[2] == 0x01)&&(ocr[3] == 0xAA))
{
// Wait for leaving idle state (ACMD41 with HCS bit)...
SPI_Timer_On(1000);
while ((SPI_Timer_Status()==TRUE)&&(__SD_Send_Cmd(ACMD41, 1UL << 30)));
SPI_Timer_Off();
if(SPI_Timer_Status()==FALSE) ct = 0;
if(__SD_Send_Cmd(CMD59, 0)) ct = 0; // Deactivate CRC check (default)
if(__SD_Send_Cmd(CMD16, 512)) ct = 0; // Set R/W block length to 512 bytes
// CCS in the OCR?
if ((SPI_Timer_Status()==TRUE)&&(__SD_Send_Cmd(CMD58, 0) == 0))
{
SPI_R(ocr, 4);
// SD version 2?
ct = (ocr[0] & 0x40) ? SDCT_SD2 | SDCT_BLOCK : SDCT_SD2;
}
}
} else {
// SD version 1 or MMC?
if (__SD_Send_Cmd(ACMD41, 0) <= 1)
{
// SD version 1
ct = SDCT_SD1;
cmd = ACMD41;
} else {
// MMC version 3
ct = SDCT_MMC;
cmd = CMD1;
}
// Wait for leaving idle state
SPI_Timer_On(250);
while((SPI_Timer_Status()==TRUE)&&(__SD_Send_Cmd(cmd, 0)));
SPI_Timer_Off();
if(SPI_Timer_Status()==FALSE) ct = 0;
if(__SD_Send_Cmd(CMD59, 0)) ct = 0; // Deactivate CRC check (default)
if(__SD_Send_Cmd(CMD16, 512)) ct = 0; // Set R/W block length to 512 bytes
}
}
if(ct) {
dev->cardtype = ct;
dev->mount = TRUE;
dev->last_sector = __SD_Sectors(dev) - 1;
printf("lastsec %u\n", dev->last_sector);
#ifdef SD_IO_DBG_COUNT
dev->debug.read = 0;
dev->debug.write = 0;
@ -365,11 +377,14 @@ SDRESULTS SD_Read(SD_DEV *dev, void *dat, DWORD sector, WORD ofs, WORD cnt)
WORD remaining;
res = SD_ERROR;
if ((sector > dev->last_sector)||(cnt == 0)) return(SD_PARERR);
// Convert sector number to byte address (sector * SD_BLK_SIZE)
if (__SD_Send_Cmd(CMD17, sector * SD_BLK_SIZE) == 0) {
// Convert sector number to byte address (sector * SD_BLK_SIZE) for SDC1
if (!(dev->cardtype & SDCT_BLOCK))
sector *= SD_BLK_SIZE;
if (__SD_Send_Cmd(CMD17, sector) == 0) {
SPI_Timer_On(100); // Wait for data packet (timeout of 100ms)
do {
tkn = SPI_RW(0xFF);
SPI_R(&tkn, 1);
} while((tkn==0xFF)&&(SPI_Timer_Status()==TRUE));
SPI_Timer_Off();
// Token of single block?
@ -377,20 +392,14 @@ SDRESULTS SD_Read(SD_DEV *dev, void *dat, DWORD sector, WORD ofs, WORD cnt)
// Size block (512 bytes) + CRC (2 bytes) - offset - bytes to count
remaining = SD_BLK_SIZE + 2 - ofs - cnt;
// Skip offset
if(ofs) {
do {
SPI_RW(0xFF);
} while(--ofs);
if(ofs) {
SPI_R(NULL, ofs);
}
// I receive the data and I write in user's buffer
do {
*(BYTE*)dat = SPI_RW(0xFF);
dat++;
} while(--cnt);
SPI_R((BYTE*)dat, cnt);
// Skip remaining
do {
SPI_RW(0xFF);
} while (--remaining);
// TODO: CRC
SPI_R(NULL, remaining);
res = SD_OK;
}
}

2
software/sys_controller/ulibSD/sd_io.h
View File

@ -56,6 +56,8 @@ typedef struct _SD_DEV {
#else // For use with uControllers
#include "sysconfig.h"
#include "stddef.h"
#include "spi_io.h" /* Provide the low-level functions */
/* Definitions of SD commands */

46
software/sys_controller/ulibSD/spi_io.c
View File

@ -1,16 +1,35 @@
#include <alt_types.h>
#include <altera_avalon_spi.h>
#include <altera_avalon_spi_regs.h>
#include <altera_avalon_pio_regs.h>
#include <sys/alt_timestamp.h>
#include <system.h>
#include <io.h>
#include "i2c_opencores.h"
#include "spi_io.h"
#include "av_controller.h"
#define SD_SLAVE_ID 0
extern alt_u8 sys_ctrl;
alt_u32 sd_timer_ts;
void SPI_Init (void) {
return;
I2C_init(SD_SPI_BASE,ALT_CPU_FREQ,400000);
}
void SPI_W(BYTE *wd, int len) {
SPI_write(SD_SPI_BASE, wd, len);
}
void SPI_R(BYTE *rd, int len) {
SPI_read(SD_SPI_BASE, rd, len);
}
BYTE SPI_RW (BYTE d) {
BYTE rdata;
BYTE w;
SPI_R(&w, 1);
alt_avalon_spi_command(SPI_0_BASE, SD_SLAVE_ID, 1, &d, 1, &rdata, 0);
return rdata;
return w;
}
void SPI_Release (void) {
@ -18,29 +37,32 @@ void SPI_Release (void) {
}
inline void SPI_CS_Low (void) {
return;
sys_ctrl &= ~SD_SPI_SS_N;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
}
inline void SPI_CS_High (void){
return;
sys_ctrl |= SD_SPI_SS_N;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
}
inline void SPI_Freq_High (void) {
return;
I2C_init(SD_SPI_BASE,ALT_CPU_FREQ,ALT_CPU_FREQ/SCL_MIN_CLKDIV);
}
inline void SPI_Freq_Low (void) {
return;
I2C_init(SD_SPI_BASE,ALT_CPU_FREQ,400000);
}
void SPI_Timer_On (WORD ms) {
sd_timer_ts = ms*(ALT_CPU_FREQ/1000);
alt_timestamp_start();
}
inline BOOL SPI_Timer_Status (void) {
return alt_timestamp() < sd_timer_ts;
}
inline void SPI_Timer_Off (void) {
return;
}

15
software/sys_controller/ulibSD/spi_io.h
View File

@ -8,6 +8,7 @@
#ifndef _SPI_IO_H_
#define _SPI_IO_H_
#include "sysconfig.h"
#include "integer.h" /* Type redefinition for portability */
@ -20,6 +21,20 @@
*/
void SPI_Init (void);
/**
\brief Read sequence of bytes
\param *rd Pointer to array where read bytes are written.
\param len Length of the array.
*/
void SPI_R (BYTE *rd, int len);
/**
\brief Write sequence of bytes
\param *wd Pointer to array which holds the bytes.
\param len Length of the array.
*/
void SPI_W (BYTE *wd, int len);
/**
\brief Read/Write a single byte.
\param d Byte to send.

8
software/sys_controller_bsp/Makefile
View File

@ -217,13 +217,6 @@ altera_avalon_jtag_uart_driver_C_LIB_SRCS := \
altera_avalon_pio_driver_SRCS_ROOT := drivers
# altera_avalon_pio_driver sources
# altera_avalon_spi_driver sources root
altera_avalon_spi_driver_SRCS_ROOT := drivers
# altera_avalon_spi_driver sources
altera_avalon_spi_driver_C_LIB_SRCS := \
$(altera_avalon_spi_driver_SRCS_ROOT)/src/altera_avalon_spi.c
# altera_avalon_timer_driver sources root
altera_avalon_timer_driver_SRCS_ROOT := drivers
@ -355,7 +348,6 @@ nios2_hw_crc32_driver_C_LIB_SRCS := \
# Assemble all component C source files
COMPONENT_C_LIB_SRCS += \
$(altera_avalon_jtag_uart_driver_C_LIB_SRCS) \
$(altera_avalon_spi_driver_C_LIB_SRCS) \
$(altera_avalon_timer_driver_C_LIB_SRCS) \
$(altera_epcq_controller_mod_driver_C_LIB_SRCS) \
$(altera_nios2_gen2_hal_driver_C_LIB_SRCS) \

7
software/sys_controller_bsp/alt_sys_init.c
View File

@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
* SOPC Builder design path: ../../sys.sopcinfo
*
* Generated: Sun Oct 16 12:18:06 EEST 2016
* Generated: Thu Oct 20 01:24:13 EEST 2016
*/
/*
@ -60,7 +60,6 @@
#include "altera_nios2_gen2_irq.h"
#include "altera_avalon_jtag_uart.h"
#include "altera_avalon_spi.h"
#include "altera_avalon_timer.h"
#include "altera_epcq_controller_mod.h"
#include "i2c_opencores.h"
@ -71,10 +70,10 @@
ALTERA_NIOS2_GEN2_IRQ_INSTANCE ( NIOS2_QSYS_0, nios2_qsys_0);
ALTERA_AVALON_JTAG_UART_INSTANCE ( JTAG_UART_0, jtag_uart_0);
ALTERA_AVALON_SPI_INSTANCE ( SPI_0, spi_0);
ALTERA_AVALON_TIMER_INSTANCE ( TIMER_0, timer_0);
ALTERA_EPCQ_CONTROLLER_MOD_AVL_MEM_AVL_CSR_INSTANCE ( EPCQ_CONTROLLER_0, EPCQ_CONTROLLER_0_AVL_MEM, EPCQ_CONTROLLER_0_AVL_CSR, epcq_controller_0);
I2C_OPENCORES_INSTANCE ( I2C_OPENCORES_0, i2c_opencores_0);
I2C_OPENCORES_INSTANCE ( I2C_OPENCORES_1, i2c_opencores_1);
/*
* Initialize the interrupt controller devices
@ -99,7 +98,7 @@ void alt_sys_init( void )
{
ALTERA_AVALON_TIMER_INIT ( TIMER_0, timer_0);
ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART_0, jtag_uart_0);
ALTERA_AVALON_SPI_INIT ( SPI_0, spi_0);
ALTERA_EPCQ_CONTROLLER_MOD_INIT ( EPCQ_CONTROLLER_0, epcq_controller_0);
I2C_OPENCORES_INIT ( I2C_OPENCORES_0, i2c_opencores_0);
I2C_OPENCORES_INIT ( I2C_OPENCORES_1, i2c_opencores_1);
}

6
software/sys_controller_bsp/drivers/inc/i2c_opencores.h
View File

@ -9,15 +9,15 @@ extern "C"
{
#endif /* __cplusplus */
#define SCL_MIN_CLKDIV 10
void I2C_init(alt_u32 base,alt_u32 clk,alt_u32 speed);
int I2C_start(alt_u32 base, alt_u32 add, alt_u32 read);
alt_u32 I2C_read(alt_u32 base,alt_u32 last);
alt_u32 I2C_write(alt_u32 base,alt_u8 data, alt_u32 last);
alt_u32 SPI_read(alt_u32 base);
void SPI_write(alt_u32 base,alt_u8 data);
void SPI_read(alt_u32 base, alt_u8 *rdata, int len);
void SPI_write(alt_u32 base, alt_u8 *wdata, int len);
#define I2C_OK (0)
#define I2C_ACK (0)
#define I2C_NOACK (1)

38
software/sys_controller_bsp/drivers/src/i2c_opencores.c
View File

@ -182,25 +182,31 @@ alt_u32 I2C_write(alt_u32 base,alt_u8 data, alt_u32 last)
}
alt_u32 SPI_read(alt_u32 base)
void SPI_read(alt_u32 base, alt_u8 *rdata, int len)
{
/* start read*/
IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_RD_MSK|I2C_OPENCORES_CR_NACK_MSK|I2C_OPENCORES_CR_SPIM_MSK );
int i;
/* wait for the trnasaction to be over.*/
while( IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK);
/* now read the data */
return (IORD_I2C_OPENCORES_RXR(base));
for (i=0; i<len; i++) {
/* start read*/
IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_RD_MSK|I2C_OPENCORES_CR_NACK_MSK|I2C_OPENCORES_CR_SPIM_MSK );
/* wait for the trnasaction to be over.*/
while( IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK);
/* now read the data */
if (rdata)
rdata[i] = IORD_I2C_OPENCORES_RXR(base);
}
}
void SPI_write(alt_u32 base,alt_u8 data) {
/* transmit the data*/
IOWR_I2C_OPENCORES_TXR(base, data);
void SPI_write(alt_u32 base, alt_u8 *wdata, int len)
{
int i;
/* start write */
IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_WR_MSK|I2C_OPENCORES_CR_NACK_MSK|I2C_OPENCORES_CR_SPIM_MSK );
/* wait for the trnasaction to be over.*/
while( IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK);
for (i=0; i<len; i++) {
/* transmit the data*/
IOWR_I2C_OPENCORES_TXR(base, wdata[i]);
/* start write */
IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_WR_MSK|I2C_OPENCORES_CR_NACK_MSK|I2C_OPENCORES_CR_SPIM_MSK );
/* wait for the trnasaction to be over.*/
while( IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK);
}
}

BIN
software/sys_controller_bsp/libhal_bsp.a
View File

Binary file not shown.

28
software/sys_controller_bsp/settings.bsp
View File

@ -2,9 +2,9 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Oct 16, 2016 12:18:06 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1476609486611</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>/home/markus/Code/ossc/software/sys_controller_bsp</BspGeneratedLocation>
<BspGeneratedTimeStamp>Oct 21, 2016 1:18:01 AM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1477001881487</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
<JdiFile>default</JdiFile>
@ -26,7 +26,7 @@
<SettingName>hal.timestamp_timer</SettingName>
<Identifier>ALT_TIMESTAMP_CLK</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<Value>timer_0</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>system_h_define</DestinationFile>
<Description>Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h.</Description>
@ -899,7 +899,7 @@
<attributes>memory</attributes>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>spi_0</slaveDescriptor>
<slaveDescriptor>i2c_opencores_1</slaveDescriptor>
<addressRange>0x00821000 - 0x0082101F</addressRange>
<addressSpan>32</addressSpan>
<attributes/>
@ -923,44 +923,38 @@
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_5</slaveDescriptor>
<slaveDescriptor>pio_4</slaveDescriptor>
<addressRange>0x00821080 - 0x0082108F</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_4</slaveDescriptor>
<slaveDescriptor>pio_3</slaveDescriptor>
<addressRange>0x00821090 - 0x0082109F</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_3</slaveDescriptor>
<slaveDescriptor>pio_2</slaveDescriptor>
<addressRange>0x008210A0 - 0x008210AF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_2</slaveDescriptor>
<slaveDescriptor>pio_1</slaveDescriptor>
<addressRange>0x008210B0 - 0x008210BF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_1</slaveDescriptor>
<slaveDescriptor>pio_0</slaveDescriptor>
<addressRange>0x008210C0 - 0x008210CF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_0</slaveDescriptor>
<addressRange>0x008210D0 - 0x008210DF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>jtag_uart_0</slaveDescriptor>
<addressRange>0x008210E0 - 0x008210E7</addressRange>
<addressRange>0x008210D0 - 0x008210D7</addressRange>
<addressSpan>8</addressSpan>
<attributes>printable</attributes>
</MemoryMap>

95
software/sys_controller_bsp/system.h
View File

@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
* SOPC Builder design path: ../../sys.sopcinfo
*
* Generated: Sun Oct 16 12:18:06 EEST 2016
* Generated: Thu Oct 20 01:24:13 EEST 2016
*/
/*
@ -150,7 +150,6 @@
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_SPI
#define __ALTERA_AVALON_TIMER
#define __ALTERA_EPCQ_CONTROLLER_MOD
#define __ALTERA_NIOS2_GEN2
@ -176,19 +175,19 @@
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart_0"
#define ALT_STDERR_BASE 0x8210e0
#define ALT_STDERR_BASE 0x8210d0
#define ALT_STDERR_DEV jtag_uart_0
#define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/jtag_uart_0"
#define ALT_STDIN_BASE 0x8210e0
#define ALT_STDIN_BASE 0x8210d0
#define ALT_STDIN_DEV jtag_uart_0
#define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart_0"
#define ALT_STDOUT_BASE 0x8210e0
#define ALT_STDOUT_BASE 0x8210d0
#define ALT_STDOUT_DEV jtag_uart_0
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
@ -243,7 +242,7 @@
#define ALT_MAX_FD 32
#define ALT_SYS_CLK none
#define ALT_TIMESTAMP_CLK none
#define ALT_TIMESTAMP_CLK TIMER_0
/*
@ -260,13 +259,27 @@
#define I2C_OPENCORES_0_TYPE "i2c_opencores"
/*
* i2c_opencores_1 configuration
*
*/
#define ALT_MODULE_CLASS_i2c_opencores_1 i2c_opencores
#define I2C_OPENCORES_1_BASE 0x821000
#define I2C_OPENCORES_1_IRQ 4
#define I2C_OPENCORES_1_IRQ_INTERRUPT_CONTROLLER_ID 0
#define I2C_OPENCORES_1_NAME "/dev/i2c_opencores_1"
#define I2C_OPENCORES_1_SPAN 32
#define I2C_OPENCORES_1_TYPE "i2c_opencores"
/*
* jtag_uart_0 configuration
*
*/
#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
#define JTAG_UART_0_BASE 0x8210e0
#define JTAG_UART_0_BASE 0x8210d0
#define JTAG_UART_0_IRQ 1
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
@ -313,7 +326,7 @@
*/
#define ALT_MODULE_CLASS_pio_0 altera_avalon_pio
#define PIO_0_BASE 0x8210d0
#define PIO_0_BASE 0x8210c0
#define PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_0_CAPTURE 0
@ -340,7 +353,7 @@
*/
#define ALT_MODULE_CLASS_pio_1 altera_avalon_pio
#define PIO_1_BASE 0x8210c0
#define PIO_1_BASE 0x8210b0
#define PIO_1_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_1_CAPTURE 0
@ -367,7 +380,7 @@
*/
#define ALT_MODULE_CLASS_pio_2 altera_avalon_pio
#define PIO_2_BASE 0x8210b0
#define PIO_2_BASE 0x8210a0
#define PIO_2_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_2_CAPTURE 0
@ -394,7 +407,7 @@
*/
#define ALT_MODULE_CLASS_pio_3 altera_avalon_pio
#define PIO_3_BASE 0x8210a0
#define PIO_3_BASE 0x821090
#define PIO_3_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_3_CAPTURE 0
@ -421,7 +434,7 @@
*/
#define ALT_MODULE_CLASS_pio_4 altera_avalon_pio
#define PIO_4_BASE 0x821090
#define PIO_4_BASE 0x821080
#define PIO_4_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_4_CAPTURE 0
@ -442,64 +455,6 @@
#define PIO_4_TYPE "altera_avalon_pio"
/*
* pio_5 configuration
*
*/
#define ALT_MODULE_CLASS_pio_5 altera_avalon_pio
#define PIO_5_BASE 0x821080
#define PIO_5_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_5_CAPTURE 0
#define PIO_5_DATA_WIDTH 8
#define PIO_5_DO_TEST_BENCH_WIRING 0
#define PIO_5_DRIVEN_SIM_VALUE 0
#define PIO_5_EDGE_TYPE "NONE"
#define PIO_5_FREQ 27000000
#define PIO_5_HAS_IN 0
#define PIO_5_HAS_OUT 1
#define PIO_5_HAS_TRI 0
#define PIO_5_IRQ -1
#define PIO_5_IRQ_INTERRUPT_CONTROLLER_ID -1
#define PIO_5_IRQ_TYPE "NONE"
#define PIO_5_NAME "/dev/pio_5"
#define PIO_5_RESET_VALUE 0
#define PIO_5_SPAN 16
#define PIO_5_TYPE "altera_avalon_pio"
/*
* spi_0 configuration
*
*/
#define ALT_MODULE_CLASS_spi_0 altera_avalon_spi
#define SPI_0_BASE 0x821000
#define SPI_0_CLOCKMULT 1
#define SPI_0_CLOCKPHASE 0
#define SPI_0_CLOCKPOLARITY 0
#define SPI_0_CLOCKUNITS "Hz"
#define SPI_0_DATABITS 8
#define SPI_0_DATAWIDTH 16
#define SPI_0_DELAYMULT "1.0E-9"
#define SPI_0_DELAYUNITS "ns"
#define SPI_0_EXTRADELAY 0
#define SPI_0_INSERT_SYNC 0
#define SPI_0_IRQ 4
#define SPI_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define SPI_0_ISMASTER 1
#define SPI_0_LSBFIRST 0
#define SPI_0_NAME "/dev/spi_0"
#define SPI_0_NUMSLAVES 1
#define SPI_0_PREFIX "spi_"
#define SPI_0_SPAN 32
#define SPI_0_SYNC_REG_DEPTH 2
#define SPI_0_TARGETCLOCK 13500000u
#define SPI_0_TARGETSSDELAY "0.0"
#define SPI_0_TYPE "altera_avalon_spi"
/*
* timer_0 configuration
*

189
sys.qsys
View File

@ -57,6 +57,22 @@
type = "String";
}
}
element i2c_opencores_1
{
datum _sortIndex
{
value = "10";
type = "int";
}
}
element i2c_opencores_1.avalon_slave_0
{
datum baseAddress
{
value = "8523776";
type = "String";
}
}
element jtag_uart_0
{
datum _sortIndex
@ -69,7 +85,7 @@
{
datum baseAddress
{
value = "8524000";
value = "8523984";
type = "String";
}
}
@ -141,7 +157,7 @@
{
datum baseAddress
{
value = "8523984";
value = "8523968";
type = "String";
}
}
@ -157,7 +173,7 @@
{
datum baseAddress
{
value = "8523968";
value = "8523952";
type = "String";
}
}
@ -173,7 +189,7 @@
{
datum baseAddress
{
value = "8523952";
value = "8523936";
type = "String";
}
}
@ -189,7 +205,7 @@
{
datum baseAddress
{
value = "8523936";
value = "8523920";
type = "String";
}
}
@ -202,22 +218,6 @@
}
}
element pio_4.s1
{
datum baseAddress
{
value = "8523920";
type = "String";
}
}
element pio_5
{
datum _sortIndex
{
value = "16";
type = "int";
}
}
element pio_5.s1
{
datum baseAddress
{
@ -225,22 +225,6 @@
type = "String";
}
}
element spi_0
{
datum _sortIndex
{
value = "10";
type = "int";
}
}
element spi_0.spi_control_port
{
datum baseAddress
{
value = "8523776";
type = "String";
}
}
element timer_0
{
datum _sortIndex
@ -284,6 +268,11 @@
internal="i2c_opencores_0.export"
type="conduit"
dir="end" />
<interface
name="i2c_opencores_1_export"
internal="i2c_opencores_1.export"
type="conduit"
dir="end" />
<interface
name="pio_0_sys_ctrl_out"
internal="pio_0.external_connection"
@ -309,17 +298,7 @@
internal="pio_4.external_connection"
type="conduit"
dir="end" />
<interface
name="pio_5_lcd_ctrl_out"
internal="pio_5.external_connection"
type="conduit"
dir="end" />
<interface name="reset" internal="clk_27.clk_in_reset" type="reset" dir="end" />
<interface
name="spi_0_external"
internal="spi_0.external"
type="conduit"
dir="end" />
<module name="clk_27" kind="clock_source" version="15.1" enabled="1">
<parameter name="clockFrequency" value="27000000" />
<parameter name="clockFrequencyKnown" value="true" />
@ -343,7 +322,16 @@
name="i2c_opencores_0"
kind="i2c_opencores"
version="13.0"
enabled="1" />
enabled="1">
<parameter name="drive_scl_high" value="0" />
</module>
<module
name="i2c_opencores_1"
kind="i2c_opencores"
version="13.0"
enabled="1">
<parameter name="drive_scl_high" value="1" />
</module>
<module
name="jtag_uart_0"
kind="altera_avalon_jtag_uart"
@ -399,7 +387,7 @@
<parameter name="dataAddrWidth" value="24" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='epcq_controller_0.avl_mem' start='0x0' end='0x800000' type='altera_epcq_controller_mod.avl_mem' /><slave name='onchip_memory2_0.s1' start='0x810000' end='0x81A000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_qsys_0.debug_mem_slave' start='0x820800' end='0x821000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='spi_0.spi_control_port' start='0x821000' end='0x821020' type='altera_avalon_spi.spi_control_port' /><slave name='timer_0.s1' start='0x821020' end='0x821040' type='altera_avalon_timer.s1' /><slave name='epcq_controller_0.avl_csr' start='0x821040' end='0x821060' type='altera_epcq_controller_mod.avl_csr' /><slave name='i2c_opencores_0.avalon_slave_0' start='0x821060' end='0x821080' type='i2c_opencores.avalon_slave_0' /><slave name='pio_5.s1' start='0x821080' end='0x821090' type='altera_avalon_pio.s1' /><slave name='pio_4.s1' start='0x821090' end='0x8210A0' type='altera_avalon_pio.s1' /><slave name='pio_3.s1' start='0x8210A0' end='0x8210B0' type='altera_avalon_pio.s1' /><slave name='pio_2.s1' start='0x8210B0' end='0x8210C0' type='altera_avalon_pio.s1' /><slave name='pio_1.s1' start='0x8210C0' end='0x8210D0' type='altera_avalon_pio.s1' /><slave name='pio_0.s1' start='0x8210D0' end='0x8210E0' type='altera_avalon_pio.s1' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x8210E0' end='0x8210E8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='epcq_controller_0.avl_mem' start='0x0' end='0x800000' type='altera_epcq_controller_mod.avl_mem' /><slave name='onchip_memory2_0.s1' start='0x810000' end='0x81A000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_qsys_0.debug_mem_slave' start='0x820800' end='0x821000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='i2c_opencores_1.avalon_slave_0' start='0x821000' end='0x821020' type='i2c_opencores.avalon_slave_0' /><slave name='timer_0.s1' start='0x821020' end='0x821040' type='altera_avalon_timer.s1' /><slave name='epcq_controller_0.avl_csr' start='0x821040' end='0x821060' type='altera_epcq_controller_mod.avl_csr' /><slave name='i2c_opencores_0.avalon_slave_0' start='0x821060' end='0x821080' type='i2c_opencores.avalon_slave_0' /><slave name='pio_4.s1' start='0x821080' end='0x821090' type='altera_avalon_pio.s1' /><slave name='pio_3.s1' start='0x821090' end='0x8210A0' type='altera_avalon_pio.s1' /><slave name='pio_2.s1' start='0x8210A0' end='0x8210B0' type='altera_avalon_pio.s1' /><slave name='pio_1.s1' start='0x8210B0' end='0x8210C0' type='altera_avalon_pio.s1' /><slave name='pio_0.s1' start='0x8210C0' end='0x8210D0' type='altera_avalon_pio.s1' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x8210D0' end='0x8210D8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
@ -668,36 +656,6 @@
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="32" />
</module>
<module name="pio_5" kind="altera_avalon_pio" version="15.1" enabled="1">
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="27000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="8" />
</module>
<module name="spi_0" kind="altera_avalon_spi" version="15.1" enabled="1">
<parameter name="avalonSpec" value="2.0" />
<parameter name="clockPhase" value="0" />
<parameter name="clockPolarity" value="0" />
<parameter name="dataWidth" value="8" />
<parameter name="disableAvalonFlowControl" value="false" />
<parameter name="inputClockRate" value="27000000" />
<parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
<parameter name="insertSync" value="false" />
<parameter name="lsbOrderedFirst" value="false" />
<parameter name="masterSPI" value="true" />
<parameter name="numberOfSlaves" value="1" />
<parameter name="syncRegDepth" value="2" />
<parameter name="targetClockRate" value="13500000" />
<parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
</module>
<module name="timer_0" kind="altera_avalon_timer" version="15.1" enabled="1">
<parameter name="alwaysRun" value="false" />
<parameter name="counterSize" value="32" />
@ -716,7 +674,7 @@
start="nios2_qsys_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x008210e0" />
<parameter name="baseAddress" value="0x008210d0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@ -728,6 +686,15 @@
<parameter name="baseAddress" value="0x00821060" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="nios2_qsys_0.data_master"
end="i2c_opencores_1.avalon_slave_0">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00821000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
@ -770,7 +737,7 @@
start="nios2_qsys_0.data_master"
end="pio_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x008210d0" />
<parameter name="baseAddress" value="0x008210c0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@ -779,7 +746,7 @@
start="nios2_qsys_0.data_master"
end="pio_1.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x008210c0" />
<parameter name="baseAddress" value="0x008210b0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@ -788,7 +755,7 @@
start="nios2_qsys_0.data_master"
end="pio_2.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x008210b0" />
<parameter name="baseAddress" value="0x008210a0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@ -797,15 +764,6 @@
start="nios2_qsys_0.data_master"
end="pio_3.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x008210a0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="nios2_qsys_0.data_master"
end="pio_4.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00821090" />
<parameter name="defaultConnection" value="false" />
</connection>
@ -813,7 +771,7 @@
kind="avalon"
version="15.1"
start="nios2_qsys_0.data_master"
end="pio_5.s1">
end="pio_4.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00821080" />
<parameter name="defaultConnection" value="false" />
@ -827,15 +785,6 @@
<parameter name="baseAddress" value="0x00821020" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="nios2_qsys_0.data_master"
end="spi_0.spi_control_port">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00821000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
@ -861,9 +810,7 @@
<connection kind="clock" version="15.1" start="clk_27.clk" end="pio_2.clk" />
<connection kind="clock" version="15.1" start="clk_27.clk" end="pio_3.clk" />
<connection kind="clock" version="15.1" start="clk_27.clk" end="pio_4.clk" />
<connection kind="clock" version="15.1" start="clk_27.clk" end="pio_5.clk" />
<connection kind="clock" version="15.1" start="clk_27.clk" end="timer_0.clk" />
<connection kind="clock" version="15.1" start="clk_27.clk" end="spi_0.clk" />
<connection
kind="clock"
version="15.1"
@ -874,6 +821,11 @@
version="15.1"
start="clk_27.clk"
end="i2c_opencores_0.clock" />
<connection
kind="clock"
version="15.1"
start="clk_27.clk"
end="i2c_opencores_1.clock" />
<connection
kind="clock"
version="15.1"
@ -893,6 +845,13 @@
end="epcq_controller_0.interrupt_sender">
<parameter name="irqNumber" value="2" />
</connection>
<connection
kind="interrupt"
version="15.1"
start="nios2_qsys_0.irq"
end="i2c_opencores_1.interrupt_sender">
<parameter name="irqNumber" value="4" />
</connection>
<connection
kind="interrupt"
version="15.1"
@ -907,13 +866,6 @@
end="timer_0.irq">
<parameter name="irqNumber" value="0" />
</connection>
<connection
kind="interrupt"
version="15.1"
start="nios2_qsys_0.irq"
end="spi_0.irq">
<parameter name="irqNumber" value="4" />
</connection>
<connection
kind="nios_custom_instruction"
version="15.1"
@ -946,6 +898,11 @@
version="15.1"
start="clk_27.clk_reset"
end="i2c_opencores_0.clock_reset" />
<connection
kind="reset"
version="15.1"
start="clk_27.clk_reset"
end="i2c_opencores_1.clock_reset" />
<connection
kind="reset"
version="15.1"
@ -986,21 +943,11 @@
version="15.1"
start="clk_27.clk_reset"
end="epcq_controller_0.reset" />
<connection
kind="reset"
version="15.1"
start="clk_27.clk_reset"
end="pio_5.reset" />
<connection
kind="reset"
version="15.1"
start="clk_27.clk_reset"
end="timer_0.reset" />
<connection
kind="reset"
version="15.1"
start="clk_27.clk_reset"
end="spi_0.reset" />
<connection
kind="reset"
version="15.1"

2778
sys.sopcinfo
View File

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