13 Commits

Author	SHA1	Message	Date
marqs	94c0526265	update project configuration and IP files	2023-02-13 18:55:14 +02:00
marqs	fd37e4275b	update to Quartus 21.1	2022-12-27 14:59:47 +02:00
marqs	73dd1963b9	update to Quartus 20.1.1	2021-07-31 18:06:21 +03:00
marqs	a076c6d2db	update quartus to 19.1	2020-02-09 21:28:24 +02:00
marqs	9feb96888b	fix PLL reference clock switchover logic	2019-10-09 23:58:55 +03:00
marqs	9d496383c3	optimize clock network ... * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl	2019-10-06 23:54:32 +03:00
marqs	dd4ffde231	update to Quartus 17.1	2017-12-07 21:35:08 +02:00
marqs	d98c23c8c1	Update project files to Quartus 17.0.	2017-05-29 19:15:34 +03:00
marqs	6e043ef577	Improve input mode handling ... * New options and better compatibility for Line5x * Add support for 960i and 1080i * Make TVP HPLL2x option user-selectable	2017-02-07 23:04:30 +02:00
marqs	3b19b2843c	Preliminary Line5x implementation	2017-01-29 13:02:12 +02:00
marqs	03bf4c2c9a	Update to Quartus 16.1.	2016-12-13 20:55:10 +02:00
marqs	f502b2e46c	Release 0.67. ... - Code cleanup - Some project files added - PAL linetriple added - FPGA PLL parameters optimized - Reduced jitter on low video clock sources	2016-03-27 23:09:31 +03:00
marqs	388c464f63	Initial public release (FW 0.64)	2016-02-23 01:03:50 +02:00