54 Commits

Author	SHA1	Message	Date
marqs	4548bf0b8c	Reset sync processing when disabling output	2016-05-25 01:06:48 +03:00
marqs	c83653c880	Release 0.69 ... * Improved remote control handling code * Fixed occasional mode change loop when switching to a non-interlace mode utilizing odd-field sync signal * Fixed randomly missing blue channel at power-on when using DVI output mode * Added H-PLL coast options * Finer tuning range for scanline strength and mask	2016-04-15 22:05:53 +03:00
marqs	f502b2e46c	Release 0.67. ... - Code cleanup - Some project files added - PAL linetriple added - FPGA PLL parameters optimized - Reduced jitter on low video clock sources	2016-03-27 23:09:31 +03:00
marqs	388c464f63	Initial public release (FW 0.64)	2016-02-23 01:03:50 +02:00